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path: root/drivers/devfreq/exynos-bus.c (follow)
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2016-12-08devfreq: exynos: Don't use OPP structures outside of RCU locksViresh Kumar1-15/+14
The OPP structures are abused to the best here, without understanding how the OPP core and RCU locks work. In short, the OPP pointer saved 'struct exynos_bus' can become invalid under your nose, as the OPP core may free it. Fix various abuses around OPP structures and calls. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Tested-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2016-07-06PM / devfreq: exynos-bus: add missing of_node_put after calling of_parse_phandlePeter Chen1-3/+6
of_node_put needs to be called when the device node which is got from of_parse_phandle has finished using. [Commit updated to fix an error by MyungJoo] Cc: Chanwoo Choi <cw00.choi@samsung.com> Cc: MyungJoo Ham <myungjoo.ham@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Kukjin Kim <kgene@kernel.org> Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Peter Chen <peter.chen@nxp.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com>
2016-07-06PM / devfreq: exynos: fix error path in exynos_bus_probe()Bartlomiej Zolnierkiewicz1-1/+1
In case of exynos_bus_parse_of() failure the code shouldn't try to remove the OPP table and disable+unprepare bus->clk as it has been already handled in exynos_bus_parse_of(). Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com>
2016-05-03PM / devfreq: style/typo fixesMyungJoo Ham1-2/+2
- Typo in comments fixed - Unnecessary return statement removed Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com>
2016-05-03PM / devfreq: exynos: Add support of bus frequency of sub-blocks using passive governorChanwoo Choi1-46/+173
This patch adds the support of bus frequency feature for sub-blocks which share the one power line. If each bus depends on the power line, each bus is not able to change the voltage by oneself. To optimize the power-consumption on runtime, some buses using the same power line should change the source clock and regulator at the same time. So, this patch uses the passive governor to support the bus frequency for all buses which sharing the one power line. For example, Exynos3250 include the two power line for AXI buses as following: : VDD_MIF : MIF (Memory Interface) provide the DMC (Dynamic Memory Controller) with the power (regulator). : VDD_INT : INT (Internal) provide the various sub-blocks with the power (regulator). Each bus is included in as follwoing block. In the case of VDD_MIF, only DMC bus use the power line. So, there is no any depencency between buese. But, in the case of VDD_INT, various buses share the one power line of VDD_INT. We need to make the depenency between buses. When using passive governor, there is no problem to support the bus frequency as DVFS for all buses. One bus should be operated as the parent bus device which gathering the current load of INT block and then decides the new frequency with some governors except of passive governor. After deciding the new frequency by the parent bus device, the rest bus devices will change the each source clock according to new frequency of the parent bus device. - MIF (Memory Interface) block : VDD_MIF |--- DMC - INT (Internal) block : VDD_INT |--- LEFTBUS (parent) |--- PERIL |--- MFC |--- G3D |--- RIGHTBUS |--- FSYS |--- LCD0 |--- PERIR |--- ISP |--- CAM Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> [tjakobi: Reported debugfs error during booting and cw00.choi fix it.] Reported-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de> Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com> Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
2016-05-03PM / devfreq: exynos: Add generic exynos bus frequency driverChanwoo Choi1-0/+443
This patch adds the generic exynos bus frequency driver for AMBA AXI bus of sub-blocks in exynos SoC with DEVFREQ framework. The Samsung Exynos SoC have the common architecture for bus between DRAM and sub-blocks in SoC. This driver can support the generic bus frequency driver for Exynos SoCs. In devicetree, Each bus block has a bus clock, regulator, operation-point and devfreq-event devices which measure the utilization of each bus block. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> [m.reichl and linux.amoon: Tested it on exynos4412-odroidu3 board] Tested-by: Markus Reichl <m.reichl@fivetechno.de> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com> Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>