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path: root/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c (follow)
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2018-02-19drm/amdgpu: separate PASID mapping from VM flush v2Christian König1-3/+2
Stuffing the PASID mapping into the VM flush isn't flexible enough since the PASID mapping changes not as often as we need a VM flush. v2: add missing use of gmc_v7_0_emit_pasid_mapping Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amdgpu: move waiting for VM flush into gmc_v9_0_emit_flush_gpu_tlbChristian König1-6/+3
Keep that at a common place instead of spread over all engines. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amdgpu: implement vce_v4_0_emit_reg_wait v2Christian König1-8/+14
Add emit_reg_wait implementation for VCE v4. v2: call new function directly from existing code Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amdgpu: implement gmc_v9_0_emit_flush_gpu_tlbChristian König1-18/+4
Unify tlb flushing for gmc v9. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amdgpu: wire up emit_wreg for VCE v4Christian König1-0/+9
Needed for vm_flush unification. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amdgpu: forward pasid to backend flush implementationsChristian König1-1/+2
rd the pasid from the VM code to the emit_vm_flush function and update all implementations with the new parameter. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-02-19drm/amdgpu: move struct gart_funcs into amdgpu_gmc.hChristian König1-2/+2
And rename it to struct gmc_funcs. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Samuel Li <Samuel.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-27drm/amdgpu: rename vm_id to vmidChristian König1-9/+9
sed -i "s/vm_id/vmid/g" drivers/gpu/drm/amd/amdgpu/*.c sed -i "s/vm_id/vmid/g" drivers/gpu/drm/amd/amdgpu/*.h Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-12drm/amdgpu: correct vce fw data and stack sizeFrank Min1-1/+1
this fix the VCE world switch hang issue Signed-off-by: Frank Min <Frank.Min@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-12drm/amdgpu: allow get_vm_pde to change flags as wellChristian König1-2/+3
And also provide the level for which we need a PDE. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-08drm/admgpu: Reduce the usage of soc15ip.hShaoyun Liu1-1/+0
Remove the header where it's not used. Acked-by: Christian Konig <christian.koenig@amd.com> Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-06drm/amdgpu: correct vce4.0 fw config for SRIOV (V2)Frank Min1-13/+25
1. program vce 4.0 fw with 48 bit address 2. correct vce 4.0 fw stack and date offset Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-06drm/amd/include:cleanup vega10 header files.Feifei Xu1-1/+1
Remove asic_reg/vega10 folder. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-06drm/amd/include:cleanup vega10 mmhub header files.Feifei Xu1-2/+2
Cleanup asic_reg/vega10/MMHUB folder. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-12-06drm/amd/include:cleanup vega10 vce header files.Feifei Xu1-3/+3
Cleanup asic_reg/vega10/VCE folder. Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-09-26drm/amdgpu: remove the clearance of vce 4.0 interrupt maskLeo Liu1-4/+0
Requested by SRIOV, the clearance of the bit moved into firmware Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-15drm/amdgpu/vce4: optimize vce 4.0 init table sequence for SRIOVFrank Min1-1/+2
Optimize init table sequence for sriov. Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang.Yu <Xiangliang.Yu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-15drm/amdgpu: According hardware design revert vce and uvd doorbell assignmentFrank Min1-4/+6
Now uvd doorbell is from 0xf8-0xfb and vce doorbell is from 0xfc-0xff Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang.Yu <Xiangliang.Yu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-15drm/amdgpu/vce4: Remove vce interrupt enable related code for sriovFrank Min1-4/+6
Interrupt enable is contained in vce init table and this register could not be accessed in secure ASICs, so just remove it. Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang.Yu <Xiangliang.Yu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-15drm/amdgpu: Enable uvd and vce gpu re-init for SRIOV gpu resetFrank Min1-3/+1
Add uvd and vce re-init after gpu reset. Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang.Yu <Xiangliang.Yu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-15drm/amdgpu: Clear vce&uvd ring wptr for SRIOVFrank Min1-1/+5
MMSCH FW need to get the wptr from 0 after it get the mailbox request from driver, since every time kick the mailbox, mmsch thinks that it is the first time engine start to initialize. Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang.Yu <Xiangliang.Yu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-06-01drm/amdgpu: add saved_bo to save vce 4.0 context when suspendLeo Liu1-8/+37
We are using PSP to resume firmware after suspend, and it is resumed at where it got suspended, so we'd better save the the context. Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-05-31drm/amdgpu: cleanup adjust_mc_addr handling v4Christian König1-4/+2
Rename adjust_mc_addr to get_vm_pde and check the address bits in one place. v2: handle vcn as well, keep setting the valid bit manually, add a BUG_ON() for GMC v6, v7 and v8 as well. v3: handle vcn_v1_0_enc_ring_emit_vm_flush as well. v4: fix the BUG_ON mask for GFX6-8 Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-05-24drm/amdgpu: move adjust adjust_mc_addr into the GFX9 vm_flush functionsChristian König1-0/+1
That GFX9 needs a PDE in the registers is entirely GFX9 specific. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-05-24drm/amdgpu: clean doorbell after sending init table to mmschFrank Min1-0/+1
According to HW design, need to clean doorbell after setup MMSCH table. Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Monk Liu <Monk.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-05-24drm/amdgpu: Bypass GMC/UVD/VCE hw_fini in SR-IOVTrigger Huang1-2/+8
On vega10, some hw finish operations should not be applied in SR-IOV case. This works as workaround to fix multi-VFs reboot/shutdown issues. Signed-off-by: Trigger Huang <trigger.huang@amd.com> Reviewed-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-28drm/amdgpu/vce4: replaced with virt_alloc_mm_tableXiangliang Yu1-17/+3
Used virt_alloc_mm_table function to allocate MM table memory. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-28drm/amdgpu/vce4: move mm table constructions functions into mmsch header fileFrank Min1-97/+46
Move mm table construction functions into mmsch header file so that UVD can reuse it. Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-28drm/amdgpu/vce4: fix a PSP loading VCE issueDaniel Wang1-3/+15
Fixed PSP loading issue for sriov. Signed-off-by: Daniel Wang <Daniel.Wang2@amd.com> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-28drm/amdgpu: assign VM invalidation engine manually v2Christian König1-1/+1
For Vega10 we have 18 VM invalidation engines for each VMHUB. Start to assign them manually to the rings. v2: add a BUG_ON if we use to many engines Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Andres Rodriguez <andresx7@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-28drm/amdgpu: invalidate only the currently needed VMHUB v2Christian König1-32/+25
Drop invalidating both hubs from each engine. v2: don't use hardcoded values Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Andres Rodriguez <andresx7@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-28drm/amdgpu: add VMHUB to ring associationChristian König1-0/+1
Add the info which ring belonging to which VMHUB. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Andres Rodriguez <andresx7@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-28drm/amdgpu/vce4: update VCE initialization sequence for SRIOVFrank Min1-7/+2
Update the initialization sequence of VCE to make VCE work. Signed-off-by: Frank Min <Frank.Min@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-06drm/amdgpu: cleanup get_invalidate_req v2Christian König1-1/+1
The two hubs are just instances of the same hardware, so the register bits are identical. v2: keep the function pointer Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-04-04drm/amdgpu: various cleanups for uvd/vce.Rex Zhu1-15/+3
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29drm/amd/amdgpu: Fix some warnings in vce4Harry Wentland1-4/+4
Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29drm/amdgpu/vce4: impl vce & mmsch sriov startXiangliang Yu1-1/+204
For MM sriov, need use MMSCH to init engine and the init procedures are all saved in mm table. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29drm/amdgpu/vce4: alloc mm table for MM sriovXiangliang Yu1-0/+21
Allocate MM table for sriov device. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29drm/amdgpu/vce4: enable doorbell for SRIOVXiangliang Yu1-1/+24
VCE SRIOV need use doorbell and only works on VCN0 ring now Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-03-29drm/amdgpu: add initial vce 4.0 support for vega10Leo Liu1-0/+894
Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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