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path: root/drivers/gpu/drm/i915/display/intel_cdclk.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2022-08-31drm/i915: move and group cdclk under display.cdclkJani Nikula1-103/+103
2022-08-29drm/i915: move and group gmbus members under display.gmbusJani Nikula1-3/+3
2022-08-29drm/i915: move cdclk_funcs to display.funcsJani Nikula1-35/+35
2022-08-25drm/i915/mtl: Fix rawclk for Meteorlake PCHClint Taylor1-0/+7
2022-07-08drm/i915/dg2: Bump up CDCLK for DG2Stanislav Lisovskiy1-2/+2
2022-05-20drm/i915/pcode: Extend pcode functions for multiple gt'sAshutosh Dixit1-8/+8
2022-03-21drm/i915: Fix DBUF bandwidth vs. cdclk handlingVille Syrjälä1-39/+28
2022-03-21drm/i915: Nuke intel_bw_calc_min_cdclk()Ville Syrjälä1-30/+1
2022-02-16drm/i915: Move MCHBAR registers to their own headerMatt Roper1-0/+1
2022-02-09drm/i915: Move the IPS code to its own fileVille Syrjälä1-0/+1
2022-01-24drm/i915/cdclk: convert to drm device based loggingJani Nikula1-1/+1
2022-01-24drm/i915/cdclk: update intel_dump_cdclk_config() loggingJani Nikula1-10/+11
2022-01-13drm/i915/pcode: rename sandybridge_pcode_* to snb_pcode_*Jani Nikula1-16/+14
2022-01-10drm/i915: split out PCI config space registers from i915_reg.hJani Nikula1-0/+1
2021-12-14drm/i915/cdclk: move struct intel_cdclk_funcs to intel_cdclk.cJani Nikula1-0/+11
2021-12-13drm/i915/cdclk: hide struct intel_cdclk_valsJani Nikula1-0/+8
2021-12-13drm/i915/cdclk: move intel_atomic_check_cdclk() to intel_cdclk.cJani Nikula1-1/+54
2021-12-09drm/i915/trace: split out display trace to a separate fileJani Nikula1-0/+1
2021-12-07drm/i915: Allow cdclk squasher to be reconfigured liveVille Syrjälä1-3/+37
2021-12-07drm/i915/display/dg2: Read CD clock from squasher tableMika Kahola1-1/+16
2021-12-07drm/i915/display/dg2: Set CD clock squashing registersMika Kahola1-1/+40
2021-12-07drm/i915/display/dg2: Sanitize CD clockMika Kahola1-3/+12
2021-12-07drm/i915/display/dg2: Introduce CD clock squashing tableMika Kahola1-6/+13
2021-12-02drm/i915/display: remove intel_wait_for_vblank()Jani Nikula1-1/+1
2021-12-02drm/i915/crtc: rename intel_get_crtc_for_pipe() to intel_crtc_for_pipe()Jani Nikula1-1/+1
2021-11-02drm/i915/display: program audio CDCLK-TS for keepalivesKai Vehmanen1-0/+5
2021-10-22drm/i915/cdclk: put the cdclk vtables in const dataJani Nikula1-22/+22
2021-10-14drm/i915: split out intel_pcode.[ch] to separate fileJani Nikula1-1/+1
2021-10-14drm/i915: split out vlv sideband to a separate fileJani Nikula1-0/+1
2021-09-29drm/i915: constify the cdclk vtableDave Airlie1-95/+205
2021-09-29drm/i915: split cdclk functions from display vtable.Dave Airlie1-71/+71
2021-09-29drm/i915: add wrappers around cdclk vtable funcs.Dave Airlie1-8/+39
2021-09-28drm/i915/display: Fix the dsc check while selecting min_cdclkVandita Kulkarni1-6/+4
2021-09-08drm/i915: Get proper min cdclk if vDSC enabledLee Shawn C1-0/+10
2021-07-30drm/i915/display: remove explicit CNL handling from intel_cdclk.cLucas De Marchi1-56/+16
2021-07-22drm/i915/dg2: Add cdclk table and reference clockMatt Roper1-2/+20
2021-07-21drm/i915: Make display workaround upper bounds exclusiveMatt Roper1-1/+1
2021-07-13drm/i915/display: Settle on "adl-x" in WA commentsJosé Roberto de Souza1-1/+1
2021-07-08drm/i915: Handle cdclk crawling flag in standard mannerMatt Roper1-7/+2
2021-06-09drm/i915/adl_p: CDCLK crawl support for ADLStanislav Lisovskiy1-9/+63
2021-06-08drm/i915: Disable PSR around cdclk changesVille Syrjälä1-0/+13
2021-05-14drm/i915/display/adl_p: Implement Wa_22011320316José Roberto de Souza1-1/+20
2021-05-14drm/i915: Move intel_modeset_all_pipes()Ville Syrjälä1-38/+0
2021-05-14drm/i915/adl_p: Add cdclk support for ADL-PAnusha Srivatsa1-13/+28
2021-05-05drm/i915: Use intel_de_wait_for_*() in cnl+ cdclk programmingVille Syrjälä1-6/+4
2021-05-05drm/i915: Use intel_de_rmw() in bxt/glk/cnl+ cdclk programmingVille Syrjälä1-10/+4
2021-05-05drm/i915: Use intel_de_rmw() in skl cdclk programmingVille Syrjälä1-14/+11
2021-05-05drm/i915: Use intel_de_rmw() in bdw cdclk programmingVille Syrjälä1-11/+6
2021-05-05drm/i915: Extract some helpers to compute cdclk register valuesVille Syrjälä1-98/+88
2021-05-05drm/i915: Don't include intel_de.h from intel_display_types.hVille Syrjälä1-0/+1
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