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path: root/drivers/gpu/drm/i915/display/intel_dpll_mgr.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2022-09-08drm/i915: Set active dpll early for icl+Ville Syrjälä1-0/+6
2022-09-08drm/i915: Feed the DPLL output freq back into crtc_stateVille Syrjälä1-1/+23
2022-09-07drm/i915: Shuffle some PLL code aroundVille Syrjälä1-85/+85
2022-08-31drm/i915/dpll: replace BUG_ON() with drm_WARN_ON()Jani Nikula1-2/+4
2022-08-31drm/i915: move vbt to display.vbtJani Nikula1-9/+9
2022-08-31drm/i915: move and group cdclk under display.cdclkJani Nikula1-2/+2
2022-08-29drm/i915: move dpll under display.dpllJani Nikula1-56/+56
2022-06-28drm/i915: Fix error code in icl_compute_combo_phy_dpll()Dan Carpenter1-1/+1
2022-06-17drm/i915/dpll: move shared dpll state verification to intel_dpll_mgr.cJani Nikula1-0/+88
2022-06-16drm/i915: Implement w/a 22010492432 for adl-sVille Syrjälä1-2/+2
2022-05-31drm/i915: Clean up DPLL related debugsVille Syrjälä1-39/+9
2022-05-31drm/i915: Split shared dpll .get_dplls() into compute and get phasesVille Syrjälä1-66/+215
2022-04-25drm/i915: Move the dpll_hw_state clearing to intel_dpll_crtc_compute_clock()Ville Syrjälä1-15/+0
2022-04-25drm/i915: Pass dev_priv to intel_shared_dpll_init()Ville Syrjälä1-5/+4
2022-04-25drm/i915: Make .get_dplls() return intVille Syrjälä1-123/+121
2022-03-10drm/i915: Replace hand rolled bxt vco calculation with chv_calc_dpll_params()Ville Syrjälä1-10/+13
2022-03-10drm/i915: Replace bxt_clk_div with struct dpllVille Syrjälä1-34/+16
2022-03-10drm/i915: Store the m2 divider as a whole in bxt_clk_divVille Syrjälä1-14/+13
2022-03-10drm/i915: Clean up bxt/glk PLL registersVille Syrjälä1-16/+16
2022-03-04drm/i915: Use designated initializers for bxt_dp_clk_val[]Ville Syrjälä1-7/+7
2022-03-04drm/i915: Remove bxt m2_frac_enVille Syrjälä1-10/+8
2022-03-04drm/i915: Clean up some struct/array initializersVille Syrjälä1-9/+9
2022-03-04drm/i915: Move a bunch of stuff into rodata from the stackVille Syrjälä1-12/+12
2022-03-04drm/i915: Nuke skl_wrpll_context_init()Ville Syrjälä1-10/+3
2022-03-02drm/i915: Use str_on_off()Lucas De Marchi1-2/+5
2022-02-18drm/i915/display/tgl+: Implement new PLL programming stepJosé Roberto de Souza1-13/+31
2022-01-19drm/i915/dpll: make intel_shared_dpll_funcs internal to intel_dpll_mgr.cJani Nikula1-0/+35
2022-01-11drm/i915: Move TC PHY registers to their own headerMatt Roper1-0/+1
2021-10-20drm/i915/display: Rename POWER_DOMAIN_DPLL_DC_OFF to POWER_DOMAIN_DC_OFFJosé Roberto de Souza1-3/+3
2021-10-19drm/i915: Move PCH refclock stuff into its own fileVille Syrjälä1-0/+1
2021-09-29drm/i915/tc: Add/use helpers to retrieve TypeC port propertiesImre Deak1-2/+3
2021-08-25drm/i915: Nuke intel_prepare_shared_dpll()Ville Syrjälä1-28/+0
2021-08-25drm/i915: Fold ibx_pch_dpll_prepare() into ibx_pch_dpll_enable()Ville Syrjälä1-10/+3
2021-08-12Merge tag 'drm-intel-next-2021-08-10-1' of git://anongit.freedesktop.org/drm/drm-intel into drm-nextDave Airlie1-494/+131
2021-08-03drm/i915: Apply CMTG clock disabling WA while DPLL0 is enabledImre Deak1-1/+33
2021-07-30drm/i915/display: remove explicit CNL handling from intel_dpll_mgr.cLucas De Marchi1-492/+94
2021-07-22drm/i915/dg2: Skip shared DPLL handlingMatt Roper1-1/+4
2021-07-14Merge branch 'topic/revid_steppings' into drm-intel-gt-nextMatt Roper1-1/+1
2021-07-14drm/i915/jsl_ehl: Use revid->stepping tablesMatt Roper1-1/+1
2021-06-15drm/i915/adl_p: Add initial ADL_P WorkaroundsClint Taylor1-2/+2
2021-05-19drm/i915/adl_p: Add PLL SupportAnusha Srivatsa1-17/+52
2021-05-05drm/i915: Don't include intel_de.h from intel_display_types.hVille Syrjälä1-0/+1
2021-04-28drm/i915/display: move crtc and dpll declarations where they belongJani Nikula1-0/+1
2021-04-14drm/i915/display: rename display version macrosLucas De Marchi1-1/+1
2021-04-14drm/i915/display: Eliminate IS_GEN9_{BC,LP}Matt Roper1-3/+3
2021-03-23drm/i915/display: Eliminate most usage of INTEL_GEN()Matt Roper1-10/+10
2021-03-19drm/i915/display: Fix a typoBhaskar Chowdhury1-1/+1
2021-03-08drm/i915: Use pipes instead crtc indices in PLL state trackingVille Syrjälä1-23/+25
2021-03-08drm/i915: Do intel_dpll_readout_hw_state() after encoder readoutVille Syrjälä1-3/+6
2021-01-26drm/i915/adl_s: Configure DPLL for ADL-SAditya Swarup1-4/+34
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