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path: root/drivers/gpu/drm/i915/display/intel_psr.c (follow)
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2024-05-20drm/i915/psr: PSR2_CTL[Block Count Number] not needed for LunarLakeJouni Högander1-1/+1
PSR2_CTL[Block Count Number] is not used by LunarLake do not configure it. Bspec: 69885 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240517073005.2414293-4-jouni.hogander@intel.com
2024-05-20drm/i915/psr: LunarLake PSR2_CTL[IO Wake Lines] is 6 bits wideJouni Högander1-0/+2
On LunarLake PSR2_CTL[IO Wake Lines] contains now bit 13:18. Take this into account when enabling PSR2_CTL. Bspec: 69885 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240517073005.2414293-3-jouni.hogander@intel.com
2024-05-20drm/i915/psr: LunarLake IO and Fast Wake time line count maximums are 68Jouni Högander1-2/+3
On LunarLake maximum for IO and Fast Wake time line counts are 68: 6 bits + 5 lines added by the HW. Take this into account in calculation and when writing the IO Wake lines. v2: maximum line count is 68 (6 bits + 5 lines added by HW) Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240517073005.2414293-2-jouni.hogander@intel.com
2024-05-16drm/i915: pass dev_priv explicitly to CURSURFLIVEJani Nikula1-4/+9
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the CURSURFLIVE register macro. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/86aa98ad9f883681f5c2e3aba839d02d8591bfbf.1715774156.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-15drm/i915: Extract intel_cursor_regs.hVille Syrjälä1-0/+1
Move most cursor register definitions into their own file. Declutters i915_reg.h a bit more. Cc: Zhenyu Wang <zhenyuw@linux.intel.com> CC: Zhi Wang <zhi.wang.linux@gmail.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-4-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-05-15drm/i915/psr: Add panel replay sel update support to debugfs interfaceJouni Högander1-3/+6
Add panel replay selective update support to debugfs status interface. In case of sink supporting panel replay we will print out: Sink support: PSR = no, Panel Replay = yes, Panel Replay Selective Update = yes and PSR mode will look like this if printing out enabled panel replay selective update: PSR mode: Panel Replay Selective Update Enabled Current PSR and panel replay printouts remain same. Cc: Kunal Joshi <kunal1.joshi@intel.com> Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-13-jouni.hogander@intel.com
2024-05-15drm/i915/psr: Split intel_psr2_config_valid for panel replayJouni Högander1-30/+46
Part of intel_psr2_config_valid is valid for panel replay. rename it as intel_sel_update_config_valid. Split psr2 specific part and name it as intel_psr2_config_valid. v3: - move early transport check to psr2 specific check - check intel_psr2_config_valid only for non-Panel Replay case v2: - use psr2_global_enabled for panel replay as well - goto unsupported instead of return when global enabled check fails Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-12-jouni.hogander@intel.com
2024-05-15drm/i915/psr: Do not apply workarounds in case of panel replayJouni Högander1-6/+10
There are some workarounds that are not applicable for panel replay. Do not apply these if panel replay is used. Bspec: 66624, 50422 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-10-jouni.hogander@intel.com
2024-05-15drm/i915/psr: Panel replay uses SRD_STATUS to track it's statusJouni Högander1-4/+16
DP Panel replay uses SRD_STATUS to track it's status despite selective update mode. Bspec: 53370, 68920 v4: - use PSR2_STATUS for eDP Panel Replay - handle intel_psr_wait_exit_locked as well v3: - do not use PSR2_STATUS for PSR1 v2: - use intel_dp_is_edp to differentiate - modify debugfs status as well Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-9-jouni.hogander@intel.com
2024-05-15drm/i915/psr: Modify intel_dp_get_su_granularity to support panel replayJouni Högander1-7/+55
Currently intel_dp_get_su_granularity doesn't support panel replay. This fix modifies it to support panel replay as well. v4: - use drm_dp_dpcd_readb instead of drm_dp_dpcd_read - ensure return value is 0 if drm_dp_dpcd_readb fails v3: use correct offset for DP_PANEL_PANEL_REPLAY_CAPABILITY v2: rely on PSR definitions on common bits Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-8-jouni.hogander@intel.com
2024-05-15drm/i915/psr: Detect panel replay selective update supportJouni Högander1-2/+8
Add new boolean to store panel replay selective update support of sink into intel_psr struct. Detect panel replay selective update support and store it into this new boolean. v3: Clear sink_panel_replay_su_support in intel_dp_detect v2: Merge adding new boolean into this patch Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-7-jouni.hogander@intel.com
2024-05-15drm/i915/psr: Rename psr2_enabled as sel_update_enabledJouni Högander1-26/+26
We are about to reuse psr2_enabled for panel replay as well. Rename it as sel_update_enabled to avoid confusion. v3: Rebase v2: Rebase Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-5-jouni.hogander@intel.com
2024-05-15drm/i915/psr: Rename has_psr2 as has_sel_updateJouni Högander1-5/+5
We are going to reuse has_psr2 for panel_replay as well. Rename it as has_sel_update to avoid confusion. v3: do not add has_psr check into psr2 case in intel_dp_compute_vsc_sdp v2: Rebase Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-2-jouni.hogander@intel.com
2024-05-06drm/i915: pass dev_priv explicitly to PORT_ALPM_LFPS_CTLJani Nikula1-1/+2
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PORT_ALPM_LFPS_CTL register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/f8a3bbade94258852b8129c5f5918fb06ceab54b.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06drm/i915: pass dev_priv explicitly to PORT_ALPM_CTLJani Nikula1-2/+4
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PORT_ALPM_CTL register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/86e8f5649c822ff6fa0502ad88964bfcb269c6c5.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06drm/i915: pass dev_priv explicitly to ALPM_CTLJani Nikula1-2/+2
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the ALPM_CTL register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/96da9be36dc93fa9a7c329f25ff963e4998998c1.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06drm/i915: pass dev_priv explicitly to PIPE_SRCSZ_ERLY_TPTJani Nikula1-1/+1
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_SRCSZ_ERLY_TPT register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/b37217f55702fc10190c2c5aded7d845a36766f6.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06drm/i915: pass dev_priv explicitly to PSR2_MAN_TRK_CTLJani Nikula1-8/+15
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PSR2_MAN_TRK_CTL register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/72934c8ac3a923ca0c12fc6cdeec1e0b87ecc4a4.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06drm/i915: pass dev_priv explicitly to PSR2_SU_STATUSJani Nikula1-1/+2
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PSR2_SU_STATUS register macro. v2: Expand from _PSR2_SU_STATUS to PSR2_SU_STATUS (Rodrigo) Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240502103925.1829104-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR2_STATUSJani Nikula1-4/+5
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the EDP_PSR2_STATUS register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/5d86a48f51ae6fa4c5a3abf098440a94d07de870.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06drm/i915: pass dev_priv explicitly to PSR_EVENTJani Nikula1-1/+3
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PSR_EVENT register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/9bc5819afa46416eb8f12ac050ed4d3bcde34b63.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR2_CTLJani Nikula1-6/+9
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the EDP_PSR2_CTL register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/e7df99445716ce404bbfe733dd962288a529cf0d.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR_DEBUGJani Nikula1-1/+1
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the EDP_PSR_DEBUG register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/187dd49632d46e67705bd258ed7f9eabdeb108b2.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR_PERF_CNTJani Nikula1-1/+1
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the EDP_PSR_PERF_CNT register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/21805960967ab88c1418037b98fe3e051eb00608.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR_STATUSJani Nikula1-1/+1
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the EDP_PSR_STATUS register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/4aaa0187b16d2b96b5b4b1d775d7349c9fc28c7c.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR_AUX_DATAJani Nikula1-1/+1
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the EDP_PSR_AUX_DATA register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/4e3dc15b170c2b64168e46ebf1802d63df34b4a2.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR_AUX_CTLJani Nikula1-1/+1
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the EDP_PSR_AUX_CTL register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/66ec1f81be49c87cd9613ba052ce6fd50362d0e0.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06drm/i915: pass dev_priv explicitly to TRANS_PSR_IIRJani Nikula1-1/+1
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_PSR_IIR register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/3a03109d11e7f55a456c3e5ef28d3ffa69582d3d.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06drm/i915: pass dev_priv explicitly to TRANS_PSR_IMRJani Nikula1-1/+1
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_PSR_IMR register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/09e9c11ffb669dac901c2416462a8f3dabc86020.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06drm/i915: pass dev_priv explicitly to EDP_PSR_CTLJani Nikula1-1/+1
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the EDP_PSR_CTL register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/198858bc3925c02c0975670e3ebb5ce2084ac658.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-05-06drm/i915: pass dev_priv explicitly to TRANS_EXITLINEJani Nikula1-2/+5
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_EXITLINE register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/eb1e5fe155daf2d271af76e683a1f3f33e34403a.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-04-11drm/i915/psr: Use crtc_state->port_clock instead of intel_dp->link_rateJouni Högander1-1/+1
Intel_dp->link_rate is not yet set at this point. Instead use crtc_state->port_clock. Fixes: 0dd21f836983 ("drm/i915/psr: Silence period and lfps half cycle") Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240409085759.178235-1-jouni.hogander@intel.com
2024-04-08drm/i915/psr: Disable PSR when bigjoiner is usedVille Syrjälä1-0/+11
Bigjoiner seem to be causing all kinds of grief to the PSR code currently. I don't believe there is any hardware issue but the code simply not handling this correctly. For now just disable PSR when bigjoiner is needed. Cc: stable@vger.kernel.org Link: https://patchwork.freedesktop.org/patch/msgid/20240404213441.17637-3-ville.syrjala@linux.intel.com Reviewed-by: Arun R Murthy <arun.r.mruthy@intel.com> Acked-by: Jouni Högander <jouni.hogander@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2024-04-08drm/i915/psr: Panel replay has to be enabled before link trainingJouni Högander1-3/+0
Panel replay has to be enabled on sink side before link training. Take this into account in fastset check and in initial fastset check. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240405113602.992714-9-jouni.hogander@intel.com
2024-04-08drm/i915/psr: Unify panel replay enable/disable sinkJouni Högander1-17/+43
Unify enabling and disabling of psr/panel replay for a sink. Modify intel_psr_enable_sink accordingly and use it for both cases. v3: - move psr2_su_region_et_valid to be check for PSR2 only v2: - enable panel replay for sink before link training - write ALPM_CONFIG only for PSR - add DP_PSR_CRC_VERIFICATION only for PSR - take care of disable sink as well Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240405113602.992714-8-jouni.hogander@intel.com
2024-04-08drm/i915/psr: Do not write registers/bits not applicable for panel replayJouni Högander1-25/+45
Bspec is saying this mask register: Only PSR_MASK[Mask FBC modify] and PSR_MASK[Mask Hotplug] are used in panel replay mode. Status register: Only SRD_STATUS[SRD state] field is used in panel replay mode. Due to this stop writing and reading registers and bits not used by panel replay if panel replay is used. Bspec: 53370, 68920 v2: - use intel_dp_is_edp with PSR_MASK register - handle LunarLake as well - hanle ALPM configuration as well Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240405113602.992714-7-jouni.hogander@intel.com
2024-04-08drm/i915/psr: Check possible errors for panel replay as wellJouni Högander1-5/+16
On HPD interrupt we want to check if the reason for HPD was some panel replay error detected by monitor/panel. This is already done for PSR. We want to do this for panel replay as well. Modify intel_psr_short_pulse to support panel replay as well. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240405113602.992714-6-jouni.hogander@intel.com
2024-04-08drm/i915/psr: Do not update phy power state in case of non-eDP panel replayJouni Högander1-4/+8
Currently panel replay is supporting only main link on mode -> Do not update phy power state for non-eDP panel replay. Bspec: 53370 v2: use intel_dp_is_edp to differentiate Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240405113602.992714-5-jouni.hogander@intel.com
2024-04-08drm/i915/psr: Intel_psr_pause/resume needs to support panel replayJouni Högander1-2/+2
Currently intel_psr_pause and intel_psr_resume do nothing in case of panel replay. Change them to perform pause and return also in case of panel replay. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240405113602.992714-4-jouni.hogander@intel.com
2024-04-08drm/i915/psr: Set intel_crtc_state->has_psr on panel replay as wellJouni Högander1-5/+6
Current code is setting only intel_crtc_state->has_panel_replay in panel replay case. There are lots of stuff behind intel_crtc_state->has_psr that is needed for panel replay as well. Instead of converting each check to has_psr || has_panel_replay set has_psr in case of panel replay as well. Code can then differentiate between psr and panel replay by using intel_crtc_state->has_panel_replay. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240405113602.992714-3-jouni.hogander@intel.com
2024-04-08drm/i915/psr: Add some documentation of variables used in psr codeJouni Högander1-0/+16
We are adding more boolean variable into intel_psr and intel_crtc_state structs. Add some documentation about these for sake of clarity. v2: Modify has_psr + has_panel_replay to mean panel replay Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240405113602.992714-2-jouni.hogander@intel.com
2024-04-02drm/i915/psr: Do not write ALPM configuration for PSR1 or DP2.0 Panel ReplayJouni Högander1-1/+2
No need to write ALPM configuration for DP2.0 Panel Replay or PSR1. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240328141928.1311284-6-jouni.hogander@intel.com
2024-04-02drm/i915/psr: Enable ALPM on source side for eDP Panel replayJouni Högander1-4/+43
Enable ALPM AUX-Less on source side for Panel Replay eDP. Also write all calculated AUX-Less configuration values accordingly. Enabling it on sink side is in upcoming patch. Bspec: 71477 v5: - mention enable is only on source side in commit message v4: - add comment explaining why AUX less is enabled on eDP panel replay without any extra checks v3: - do not use alpm_ctl as uninitialized variable v2: - do not set AUX-Wake related bits for AUX-Less case - drop switch to active latency - add SLEEP_HOLD_TIME_50_SYMBOLS - add PORT_ALPM_CTL_MAX_PHY_SWING_HOLD Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240328141928.1311284-5-jouni.hogander@intel.com
2024-04-02drm/i915/psr: Silence period and lfps half cycleJouni Högander1-2/+80
Add get function for silence period and lfps half cycle. Values are taken from the tables in bspec. Bspec: 71632 v3: - use PORT_ALPM_CTL_SILENCE_PERIOD_MASK instead of value 255 - use PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK instead of value 31 v2: - fix some checks - add some more comments Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240328141928.1311284-4-jouni.hogander@intel.com
2024-04-02drm/i915/psr: Calculate aux less wake timeJouni Högander1-0/+60
Calculate aux less wake time and store it into alpm_params struct Bspec: 71477 v4: - re-use fast_wake_lines to store aux_less_wake_lines v3: - use ALPM_CTL_AUX_LESS_WAKE_TIME_MASK instead of value 63 v2: - use variables instead of values directly - fix max value - move converting port clock to Mhz into _lnl_compute_aux_less_wake_time Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240328141928.1311284-3-jouni.hogander@intel.com
2024-03-28drm/i915/display: Implement Wa_16021440873Jouni Högander1-6/+14
This patch is implementing Wa_16021440873. Bspec: 74151 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240319123327.1661097-6-jouni.hogander@intel.com
2024-03-28drm/i915/psr: Fix intel_psr2_sel_fetch_et_alignment usageJouni Högander1-22/+33
Currently we are not aligning selective update area to cover cursor fully when cursor is not updated by itself but still in the selective update area. Fix this by checking cursor separately after drm_atomic_add_affected_planes. Bspec: 68927 Fixes: 1bff93b8bc27 ("drm/i915/psr: Extend SU area to cover cursor fully if needed") Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240319123327.1661097-4-jouni.hogander@intel.com
2024-03-28drm/i915/psr: Move writing early transport pipe srcJouni Högander1-0/+7
Currently PIPE_SRCSZ_ERLY_TPT is written in intel_display.c:intel_set_pipe_src_size. This doesn't work as intel_set_pipe_src_size is called only on modeset. Bspec: 68927 Fixes: 3291bbb93e16 ("drm/i915/psr: Configure PIPE_SRCSZ_ERLY_TPT for psr2 early transport") Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240319123327.1661097-3-jouni.hogander@intel.com
2024-03-28drm/i915/psr: Calculate PIPE_SRCSZ_ERLY_TPT valueJouni Högander1-0/+16
When early transport is enabled we need to write PIPE_SRCSZ_ERLY_TPT on every flip doing selective update. This patch calculates PIPE_SRCSZ_ERLY_TPT same way as is done for PSR2_MAN_TRK_CTL value and stores i in intel_crtc_state->pipe_srcsz_early_tpt to be written later during flip. Bspec: 68927 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240319123327.1661097-2-jouni.hogander@intel.com
2024-03-21drm/i915/snps: pass encoder to intel_snps_phy_update_psr_power_state()Jani Nikula1-5/+2
Pass encoder to intel_snps_phy_update_psr_power_state(). The encoder will be more helpful than just port in the subsequent changes. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/4711919a9834cf4a49fd665009ba9d44b4b42bc4.1710949619.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
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