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path: root/drivers/gpu/drm/i915/i915_reg.h (follow)
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2024-04-30drm/i915/dpio: Extract vlv_dpio_phy_regs.hVille Syrjälä1-298/+0
2024-04-30drm/i915/dpio: Clean up the vlv/chv PHY register bitsVille Syrjälä1-125/+155
2024-04-30drm/i915/dpio: Clean up VLV/CHV DPIO PHY register definesVille Syrjälä1-175/+100
2024-04-30drm/i915/dpio: Rename a few CHV DPIO PHY registersVille Syrjälä1-12/+11
2024-04-30drm/i915/dpio: Give VLV DPIO group register a clearer nameVille Syrjälä1-45/+45
2024-04-30drm/i915/dpio: Fix VLV DPIO PLL register dword numberingVille Syrjälä1-12/+12
2024-04-30drm/i915/dpio: s/VLV_PLL_DW9_BCAST/VLV_PCS_DW17_BCAST/Ville Syrjälä1-1/+2
2024-04-30drm/i915/dpio: s/VLV_REF_DW13/VLV_REF_DW11/Ville Syrjälä1-2/+2
2024-04-29drm/i915/display: split out intel_sprite_regs.h from i915_reg.hJani Nikula1-340/+0
2024-04-29drm/i915/display: split out intel_fbc_regs.h from i915_reg.hJani Nikula1-123/+0
2024-04-29drm/i915/color: move palette registers to intel_color_regs.hJani Nikula1-30/+0
2024-04-29drm/i915/audio: move LPE audio regs to intel_audio_regs.hJani Nikula1-16/+0
2024-04-25drm/i915: pass dev_priv to _MMIO_PIPE2, _MMIO_TRANS2, _MMIO_CURSOR2Jani Nikula1-94/+94
2024-04-25drm/i915: convert _MMIO_PIPE3()/_MMIO_PORT3() to accept baseJani Nikula1-38/+42
2024-04-19drm/i915/dpio: Extract bxt_dpio_phy_regs.hVille Syrjälä1-262/+0
2024-04-19drm/i915/dpio: Add per-lane PHY TX register definitons for bxt/glkVille Syrjälä1-19/+19
2024-04-19drm/i915/dpio: Clean up bxt/glk PHY registersVille Syrjälä1-37/+37
2024-04-10drm/i915/mtl: Add DP FEC BS jitter WAImre Deak1-0/+1
2024-04-10drm/i915/mtl+: Disable DP/DSC SF insertion at EOL WAImre Deak1-0/+1
2024-04-10drm/i915/adlp+: Add DSC early pixel count scaling WA (Wa_1409098942)Imre Deak1-0/+3
2024-04-10drm/i915/adlp: Add DP MST DPT/DPTP alignment WA (Wa_14014143976)Imre Deak1-0/+1
2024-04-10drm/i915/adlp: Add MST short HBlank WA (Wa_14014143976)Imre Deak1-0/+1
2024-04-10drm/i915/adlp: Add MST FEC BS jitter WA (Wa_14013163432)Imre Deak1-0/+3
2024-04-04drm/i915/display: Compute vrr_vsync paramsMitul Golani1-0/+7
2024-04-04drm/i915/dp: Add Read/Write support for Adaptive Sync SDPMitul Golani1-0/+8
2024-03-28drm/i915/display: Add definition for MCURSOR_MODE_64_2BJouni Högander1-0/+1
2024-03-22drm/i915: Drop dead code for pvcLucas De Marchi1-1/+0
2024-03-22drm/i915: Drop dead code for xehpsdvLucas De Marchi1-2/+1
2024-03-13drm/i915/cdclk: Add and use mdclk_source_is_cdclk_pll()Gustavo Sousa1-1/+3
2024-03-07drm/i915: Rename ICL_AUX_ANAOVRD1 to ICL_PORT_TX_DW6_AUXVille Syrjälä1-9/+0
2024-03-07drm/i915/vrr: Generate VRR "safe window" for DSBVille Syrjälä1-1/+1
2024-02-07drm/i915: Rename the DSM/GSM registersVille Syrjälä1-3/+4
2024-02-07drm/i915: Bypass LMEMBAR/GTTMMADR for MTL stolen memory accessVille Syrjälä1-0/+3
2024-01-30drm/i915/xe2lpd: Move D2D enable/disableLucas De Marchi1-0/+2
2024-01-09drm/i915/psr: Calculate and configure CUR_POS_ERLY_TPTJouni Högander1-0/+2
2023-12-19drm/i915/dp: Add TPS4 PHY test pattern supportKhaled Almahallawy1-0/+4
2023-11-17drm/i915: add vlv_pipe_to_phy() helper to replace DPIO_PHY()Jani Nikula1-2/+0
2023-10-11drm/i915/xe2lpd: display capability register definitionsVinod Govindapillai1-0/+7
2023-10-03drm/i915/lnl: possibility to enable FBC on first three planesVinod Govindapillai1-0/+2
2023-09-21drm/i915/lnl: Start using CDCLK through PLLStanislav Lisovskiy1-0/+1
2023-09-21drm/i915/xe2lpd: Read pin assignment from IOMLuca Coelho1-0/+1
2023-09-21drm/i915/xe2lpd: Handle port AUX interruptsGustavo Sousa1-3/+2
2023-08-25drm/i915/regs: split out intel_color_regs.hJani Nikula1-274/+0
2023-08-07Merge tag 'drm-intel-gt-next-2023-08-04' of git://anongit.freedesktop.org/drm/drm-intel into drm-nextDave Airlie1-2/+24
2023-07-26drm/i915/hotplug: Reduce SHPD_FILTER to 250usSuraj Kandpal1-0/+1
2023-06-13drm/i915/mtl/gsc: Add a gsc_info debugfsDaniele Ceraolo Spurio1-2/+24
2023-06-10Merge drm/drm-next into drm-intel-nextJani Nikula1-0/+3
2023-06-09Merge tag 'drm-intel-gt-next-2023-06-08' of git://anongit.freedesktop.org/drm/drm-intel into drm-nextDave Airlie1-0/+3
2023-06-07drm/i915/mtl: Add support for PM DEMANDMika Kahola1-2/+24
2023-06-05drm/i915/huc: differentiate the 2 steps of the MTL HuC auth flowDaniele Ceraolo Spurio1-0/+3
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