aboutsummaryrefslogtreecommitdiffstatshomepage
path: root/drivers/gpu
AgeCommit message (Collapse)AuthorFilesLines
2026-08-06drm/amd/display: Remove duplicate in tests/MakefileRoman Li1-1/+0
The duplicate amdgpu_dm_plane_test.o entry causes linker errors during the arm-64 build. Reviewed-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amdgpu/gmc12.1: fix MMHUB0 check in pasid tlb flushAlex Deucher1-1/+1
Check for mmhub0 rather than mmhub1. Looks like a copy paste typo. Fixes: d0c989a0aad3 ("drm/amd/amdgpu : Use the MES INV_TLBS API for tlb invalidation on gfx12_1") Cc: Shaoyun Liu <shaoyun.liu@amd.com> Reviewed-by: Shaoyun Liu <shaoyun.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/display: Enable DCN6 sources compilationAurabindo Pillai121-53/+3081
- Add hooks in various entry points to perform hw/sw init for DCN6 asic - Add dependent changes needed to enable DCN6 asic - Update the Makefiles so that DCN6 related newly added sources are compiled Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amdgpu: Allocate coredump ring buffers per ringLijo Lazar2-26/+27
Allocate each ring buffer separately. A single allocation summing all ring sizes can exceed the page allocator's MAX_ORDER limit and fail; per-ring buffers stay small enough to satisfy. The existing allocation style doesn't capture any ring data if the huge allocation fails. Splitting into multiple allocations helps to capture as much data as possible for the core dump. A failed ring is left with a NULL buffer and skipped when formatting. Fixes: eea85914d15b ("drm/amdgpu: save ring content before resetting the device") Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Assisted-by: Claude Code Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amdgpu: Use virtual alloc during coredumpLijo Lazar1-3/+7
The number of rings with outstanding fences can be large, requiring a bigger allocation. Such allocations don't need to be physically contiguous, so use kvzalloc/kvcalloc which fall back to vmalloc when contiguous memory isn't available. This also matches the existing kvfree used to free these allocations. Also guard the allocation with ring_count to avoid passing 0 size to allocation routines. Fixes: eea85914d15b ("drm/amdgpu: save ring content before resetting the device") Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/display: Add new sources for DCN6Aurabindo Pillai107-1/+48882
Add DCN6 code to DC, DML2, and DMUB Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd: Add DCN6 register headersAurabindo Pillai6-0/+74491
Add new headers for: - dcn 6.0.0 - dpcs 6.0.0 - mmhub 5.0.1 Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amdgpu: reject oversized IBs with per-ring packet limitsCandice Li1-1/+26
On GFX rings, amdgpu_cs_p2_ib() passed user-supplied ib_bytes through to ib->length_dw without a limit, while ring_emit_ib() encodes length into packet fields. Oversized values can corrupt adjacent control bits and destabilize command submission. Add a per-ring IB packet size limit helper and reject command submissions exceeding the corresponding dword limit before IB allocation. Use the documented 20-bit limit for GFX/compute/SDMA/VPE, and apply the MM fallback limit for other ring types. Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amdgpu/userq: serialize queue map against GPU resetJesse Zhang1-0/+5
Creating a user queue can race with a GPU reset. While recovery holds reset_domain->sem for write, MES is unresponsive, so the ADD_QUEUE from amdgpu_userq_map_helper() times out (-110) and an otherwise valid queue create fails: amdgpu: MES(0) failed to respond to msg=ADD_QUEUE [drm:mes_userq_map [amdgpu]] *ERROR* Failed to map queue in HW, err (-110) amdgpu: [drm] *ERROR* ... Failed to map Queue amdgpu: [drm] *ERROR* ... Failed to create usermode queue Take reset_domain->sem for read around the map so it runs only once MES is back up. This mirrors amdgpu_userq_cleanup() and honors the userq_mutex -> reset_domain->sem order; the reset path never takes userq_mutex, so there is no deadlock. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amdgpu/userq: mark a queue unmapped after a per-queue resetJesse Zhang1-1/+11
mes_userq_reset() unmaps the queue via the low-level mes_userq_unmap() (REMOVE_QUEUE) but does not update queue->state, so the queue still looks MAPPED. The destroy path then issues a second, redundant REMOVE_QUEUE for the already-removed queue; for gfx that unmap waits on an EOP that never arrives, times out (-110) and escalates to a full GPU reset. Mark the queue UNMAPPED on a successful reset-path unmap so destroy skips the redundant REMOVE_QUEUE. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amdgpu: recover user queues in the shared priv-fault helperJesse Zhang1-3/+17
If a priv/bad-op fault does not match a kernel queue slot, it belongs to a MES-scheduled user queue. Extend the shared amdgpu_gfx_handle_priv_fault() helper introduced by commit d8ab7636160e ("drm/amd/amdgpu: remove duplicated code in gfx_v11 and gfx_v12") to recover it: gate on adev->gfx.disable_uq, reset a compute user queue directly from its doorbell, and for a gfx user queue (whose IV carries no doorbell) record the HW slot and schedule the per-IP recovery worker. v2: - gate on adev->gfx.disable_uq instead of !adev->enable_mes (Alex) - document why both the doorbell (compute) and HW-slot (gfx) reset paths are needed (Alex) v3: - rebase amd-staging-drm-next. adapt to the commit 9243cf4777fc ("drm/amd/amdgpu: remove duplicated code in gfx_v11 and gfx_v12"); no functional change Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Suggested-by: Mario Sopena-Novales <Mario.Novales@amd.com> Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amdgpu/gfx12: add priv-fault user-queue recovery workerJesse Zhang1-0/+39
Mirror the gfx11 priv-fault user-queue recovery worker for GFX12, reading the doorbell back from the HQD via soc24_grbm_select. The shared amdgpu_gfx_handle_priv_fault() helper schedules this worker for a gfx user-queue fault; wiring the helper up is done in a later patch. v2: - gate on adev->gfx.disable_uq instead of !adev->enable_mes (Alex) - document why both the doorbell (compute) and HW-slot (gfx) reset paths are needed (Alex) v3: - rebase amd-staging-drm-next. adapt to the commit 9243cf4777fc ("drm/amd/amdgpu: remove duplicated code in gfx_v11 and gfx_v12"); no functional change Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Suggested-by: Mario Sopena-Novales <Mario.Novales@amd.com> Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amdgpu/gfx11: add priv-fault user-queue recovery workerJesse Zhang1-0/+39
A gfx user-queue priv/bad-op fault is raised by the ME and carries only the HW slot, not the faulting queue's doorbell. Add a per-IP worker that drains adev->gfx.userq_priv_fault_slots, reads the doorbell back from each HQD via soc21_grbm_select (regCP_RB_DOORBELL_CONTROL), looks up the user queue and kicks its per-queue reset. The shared amdgpu_gfx_handle_priv_fault() helper schedules this worker for a gfx user-queue fault; wiring the helper up is done in a later patch. v2: - gate on adev->gfx.disable_uq instead of !adev->enable_mes (Alex) - document why both the doorbell (compute) and HW-slot (gfx) reset paths are needed (Alex) v3: - rebase amd-staging-drm-next. adapt to the commit 9243cf4777fc ("drm/amd/amdgpu: remove duplicated code in gfx_v11 and gfx_v12"); no functional change Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Suggested-by: Mario Sopena-Novales <Mario.Novales@amd.com> Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amdgpu: track faulted gfx user-queue slotsJesse Zhang1-0/+3
A gfx priv/bad-op fault IV carries only the HW slot (ring_id), not the faulting user queue's doorbell. Add userq_priv_fault_slots (an atomic bitmap of faulted slots, so concurrent faults are not dropped) and userq_priv_fault_work to struct amdgpu_gfx; a worker drains the bitmap and reads the doorbell back from each HQD to locate and reset the queue. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amdgpu: Fix lockdep false positive in amdgpu_lockdep_initVitaly Prosyak1-6/+15
Move fs_reclaim_acquire() to before all lock acquisitions to eliminate false positive circular locking dependency warning. This is a 7.2-cycle regression fix suitable for stable backport. v3: Address Mikhail Gavrilov technical review: - Clarify that fs_reclaim_acquire/release pair only REGISTERS the fs_reclaim lock class, does NOT create a static edge when called with no locks held - Explain that the actual fs_reclaim -> notifier_lock edge is established at runtime during memory reclaim -> MMU notifier path - Add Cc: Arunpravin PaneerSelvam v2: Address Mikhail Gavrilov review feedback: - Fix author name: Michael -> Mikhail Gavrilov in all trailers - Add Fixes: tag to link regression to original commit - Add Tested-by: Mikhail Gavrilov (tested on RX 7900 XTX) Fixes: 1d0f5838b126 ("drm/amdgpu: Add lockdep annotations for lock ordering validation") Reported-by: Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com> Analyzed-by: Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com> Test-case-by: Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com> Tested-by: Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com> Suggested-by: Christian König <christian.koenig@amd.com> Tested-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Arunpravin PaneerSelvam <Arunpravin.PaneerSelvam@amd.com> Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Acked-by: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/pm: smu_v14_0_0: use find_clk_level() for DPM level markingPriya Hosur1-7/+22
Replace the simple exact-match loop in emit_clk_levels with a call to smu_v14_0_0_find_clk_level() introduced in patch 1. The helper already handles both exact and closest-match semantics. Build a stack-local frequency table from the DPM levels (using reverse index for SMU_MCLK since MemPstateTable stores levels high-to-low), then call the helper once to find the active level. The SMU reports time-filtered average frequencies that often do not match any DPM table entry exactly. Without closest-match fallback, MCLK, FCLK and other clocks show DPM levels but never display the * marker, breaking userspace tools that rely on it to identify the active frequency. Signed-off-by: Priya Hosur <Priya.Hosur@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/pm: smu_v14_0_0: add SMU_DCEFCLK support in DPM frequency queriesPriya Hosur1-0/+28
Add SMU_DCEFCLK case to smu_v14_0_1_get_dpm_freq_by_index and smu_v14_0_0_get_dpm_freq_by_index using DcfClocks[] with NumDcfClkLevelsEnabled bounds check. Add matching case in both get_dpm_level_count functions. Add SMU_DCEFCLK case in emit_clk_levels to list DCEF DPM levels. No * marker is emitted since SmuMetrics_t has no DcfclkFrequency field (same firmware limitation as Phoenix). Without this, pp_dpm_dcefclk reports N/A on Strix Halo. Signed-off-by: Priya Hosur <Priya.Hosur@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/pm: add IP_VERSION(11,5,1) to vclk/dclk DPM sysfs whitelistsPriya Hosur1-2/+6
Add IP_VERSION(11,5,1) to pp_dpm_vclk and pp_dpm_dclk visibility whitelists so these sysfs entries are exposed on Strix Halo (GC 11.5.1). Add IP_VERSION(11,5,1) to pp_dpm_vclk1 and pp_dpm_dclk1 whitelists with the existing num_vcn_inst >= 2 guard since Strix Halo has two VCN instances. Without this, amd-smi reports N/A for VCLK0, VCLK1, DCLK0 and DCLK1 clocks. Signed-off-by: Priya Hosur <Priya.Hosur@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/pm: smu_v14_0_0: fix DCLK metric reporting via VCLK level indexPriya Hosur1-0/+52
SmuMetrics_t has no DclkFrequency field but DCLK and VCLK have separate DPM clock tables with different frequencies at each level. Introduce smu_v14_0_0_find_clk_level(), a shared helper that finds the closest DPM level for a given target frequency in a frequency array. For METRICS_AVERAGE_DCLK, use the helper to find the DPM level whose VCLK frequency matches the reported VclkFrequency and return the DCLK frequency at that same level index, since both clocks share the same level count (VcnClkLevelsEnabled / Vcn0ClkLevelsEnabled). The original code returned 0 for METRICS_AVERAGE_DCLK, which broke the active-level marker in pp_dpm_dclk entirely. Signed-off-by: Priya Hosur <Priya.Hosur@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amdgpu/gmc12.1: implement tlb inv semaphoreAlex Deucher1-0/+46
Needed to properly lock the interface before using it. Cc: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Sonny Jiang <sonny.jiang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/pm: restore user PPT limits after GPU resetYang Wang1-1/+2
GPU reset reinitializes PMFW and reloads the platform power table. The saved user policy remains valid, but suspend-only restore does not run because adev->in_suspend is clear. Restore the active PPT policy from SMU late initialization while the device is in reset recovery. Route each value through the common range validation and ASIC setter before updating PMFW. Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/pm: refactor user PPT policy save and restoreYang Wang3-28/+68
The existing user policy representation has three ambiguities: - A numeric value cannot distinguish explicit zero from an unset policy. - One value per controller cannot preserve independent AC and DC requests. - Suspend-only restore misses runtime resume, GPU reset, and table reload. Refactor policy storage and restore as follows: - Store values and validity masks by power source and PPT controller. - Save writes against the active source. - Restore the active source after default SMU setup. - Reapply the target policy after live AC/DC transitions. - Use the target source default when no explicit request exists. The late-init path now covers system resume, runtime resume, GPU reset, and custom PPTable reload. Common code owns persistent policy; PMFW continues to own effective current limits. Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/pm: account for OD percentage in effective PPT limitsYang Wang3-42/+65
SMU 13.0.0, SMU 13.0.7, and SMU 14.0.2 represent limits above the message limit as a base value plus an overdrive percentage. GetPptLimit returns only the base, which causes two incorrect results: - hwmon reports the message limit instead of the effective limit. - Lowering the cap can leave the previous OD percentage active. Export the active overdrive table from PMFW and combine its PPT percentage with the message result. Use the exported percentage to clear OD state before programming a limit within the message range. Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amdgpu: fix userq VA validation for sub-page buffersCandice Li1-9/+16
amdgpu_userq_input_va_validate() converts expected_size to page count with a plain right shift. For expected_size smaller than one GPU page, the computed size becomes 0 and the range check is effectively bypassed. This allows sub-page userq buffers (e.g. EOP/CSA) to pass validation as long as the start VA is mapped, without verifying the full span. Fix it by rejecting zero expected_size, checking overflow when computing end address, and deriving page span from [start_addr, end_addr] inclusive. Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/pm: refactor PPT limits by controller and power sourceYang Wang21-687/+699
The scalar PPT model has several structural limitations: - Controller identity, power source, capability, and PMFW state share the same fields. - Combined callbacks cannot address PPT0 and PPT1 independently. - Cached current limits can become stale after PMFW reset. Refactor the model around these rules: - Index ranges by AC/DC source and PPT0/PPT1 controller. - Store normal and overdrive capabilities separately. - Pass the controller to get and set callbacks. - Keep slow and fast names as semantic aliases. Assign each value to a single owner: - PPTable or platform initialization supplies constant capabilities. - PMFW supplies runtime state. - Common code selects the active source and overdrive range. Van Gogh defaults are initialized once, while firmware without PPT query support remains usable. Capable SMU 13.0.6 and SMU 15.0.8 platforms expose PPT1 through the same interface. A writable controller must also provide a setter callback. Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/pm: derive stable PPT limits from PPTableYang Wang4-40/+53
GetPptLimit reports mutable PMFW runtime state. Using that value for static capabilities causes two externally visible problems: - A userspace override changes the default reported through hwmon. - A firmware reset changes the advertised minimum or maximum range. Derive platform defaults and supported ranges from the driver PPTable for Sienna Cichlid, Navi10, Arcturus, and Aldebaran. Reserve PMFW queries for the effective current limit. Runtime policy can no longer redefine immutable platform capabilities. Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/ras: rename core ras_* files and update include guardsYiPeng Chai26-53/+53
Rename selected RAS core source and header filenames to drop redundant ras_ prefixes in file names only. Update related build object names, header include references, and include guard macros in renamed headers. Function/type prefixes and runtime behavior are unchanged. No functional change intended. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amdkfd: Unmap svm range from GPU set to no-accessPhilip Yang3-42/+76
When KFD_IOCTL_SVM_ATTR_NO_ACCESS is applied to a GPU that has an SVM range mapped, unmap the range from that GPU. Once no GPU maps the range, the MMU notifier can skip queue eviction on CPU page faults. Replace the mapped_to_gpu boolean with bitmap_mapped to track which GPUs currently have the range mapped. Set bits in svm_range_map_to_gpus() and clear them in svm_range_unmap_from_gpus(). This is separate from bitmap_access/bitmap_aip which track user-requested attributes and must not be used to determine mapping state. Add bitmap_needs_unmap to svm_range, set for each GPU given no-access. Add svm_range_needs_unmap() to unmap the range from those GPUs when the app sets the no-access attribute. Bump the checkpoint timestamp on unmap so retry faults queued before the no-access unmap are dropped instead of restoring the mapping. v4: - Rename and set prange->mapping_done to false if validate and map not complete successfully (Felix) v3: - Correct error handling, support app retry update mapping (Felix) v2: - Add bitmap_mapped to not break get_attr (Felix) Signed-off-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amdkfd: Add helper svm_range_update_checkpoint_timestampPhilip Yang2-37/+50
Extract svm_range_update_checkpoint_timestamp() from svm_range_unmap_from_cpu(). The next patch calls it when the app sets the no-access attribute. Change checkpoint_ts in svm_range_list from uint64_t to atomic64_t so svm_range_restore_pages() can read it from the page fault handler without holding the svms lock. No functional change, preparation for the next patch. Signed-off-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/pm/smu15: switch SMU v15.0.0 to DRAM-based accumulator metricsShubhankar Milind Sardeshpande4-115/+218
Replace the legacy SMU table-copy metrics path with a DRAM-mapped, accumulator-based approach for SMU v15.0.0, using a ping-pong buffer to compute averaged metrics from deltas between consecutive samples. - Add GetMetricsTableVersion, GetMetricsTableLogSample and GetMetricsTableLogDramAddr messages and their MSG_MAP entries. - Introduce SMU_15_0_0_MetricsInfo_t holding two MetricsTable_t buffers, the mapped DRAM address, table size and pre-computed avg_metric[] values. - Resolve and ioremap_wc() the firmware log DRAM address once in init_smc_tables(); iounmap() it in fini_smc_tables(). - Fetch samples into the inactive buffer, compute averaged clocks, activity, power and temperature via wrapping_sub() accumulator deltas, then swap the active index. - Rename the old get_metrics_table() to get_gpu_metrics_table() for the gpu_metrics v3.0 export path. - Smartshift sensor reporting is dropped Co-developed-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Co-developed-by: Suresh Guttula <Suresh.Guttula@amd.com> Signed-off-by: Suresh Guttula <Suresh.Guttula@amd.com> Co-developed-by: Kanala Ramalingeswara Reddy <Kanala.RamalingeswaraReddy@amd.com> Signed-off-by: Kanala Ramalingeswara Reddy <Kanala.RamalingeswaraReddy@amd.com> Signed-off-by: Shubhankar Milind Sardeshpande <Shubhankar.MilindSardeshpande@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Acked-by: Yang Wang <kevinyang.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/pm/smu15: add metrics table header for SMU v15.0.0Shubhankar Milind Sardeshpande1-0/+230
Add smu_v15_0_0_metrics.h defining the v0x04 metrics table structures (MetricsTable_IOD_t, MetricsTable_CCX_t, MetricsTable_t) exported by SMU firmware. These structures describe voltage, power, thermal, frequency, bandwidth, activity, and overclock telemetry fields used for PM reporting on SMU v15.0.0 APUs. Signed-off-by: Shubhankar Milind Sardeshpande <Shubhankar.MilindSardeshpande@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/ras: rename rascore directory to coreYiPeng Chai42-3/+3
Rename the RAS core directory from rascore to core and update build-path references accordingly. The change is mechanical and done with git rename semantics so history tracking is preserved. No functional change intended. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amdgpu: Prefer default discovery offsetLijo Lazar1-0/+13
If a valid signature is seen at the default offset, use the default size/offset for discovery. Fixes: 01bdc7e219c4 ("drm/amdgpu: New interface to get IP discovery binary v3") Closes: https://gitlab.freedesktop.org/drm/amd/-/work_items/5447 Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amdgpu: remove obsolete gmc ras helpersHawking Zhang6-29/+0
Remove the obsolete gmc ras helpers including amdgpu_gmc_ras_late_init and amdgpu_gmc_ras_fini and their declarations, and call sites. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Ce Sun <cesun102@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amdgpu: read TRUNCATE_COORD_MODE on gfx12Qiang Yu1-0/+6
TA_CNTL2.TRUNCATE_COORD_MODE selects whether texture coordinate truncation is D3D9/GL/Vulkan conformant. gfx11 reads it and reports it to userspace via AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD, but gfx12 never read it, so the flag was always reported as 0 and userspace fell back to the non-conformant path. Read it in gfx_v12_0_constants_init() like gfx11 does. Fixes: 52cb80c12e8a ("drm/amdgpu: Add gfx v12_0 ip block support (v6)") Signed-off-by: Qiang Yu <Qiang.Yu@amd.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amdgpu: fix JPEG v5.3.0 queue reset failure in DPG modeJesse Zhang1-4/+17
Like jpeg_v5_0_0, in DPG mode the ring reset path only clears the JPEG_PG_MODE bit and never resets a hung JRBC, so the post-reset ring test times out and the driver falls back to a full MODE1 reset. Temporarily force the static power-gating path during the reset so the stop/start sequence power-cycles the JPEG block (JMI soft reset + power off/on), matching the jpeg_v4_0 reset. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amdgpu: fix JPEG v4.0.5 queue reset failure in DPG modeJesse Zhang1-4/+17
Like jpeg_v5_0_0, in DPG mode the ring reset path only clears the JPEG_PG_MODE bit and never resets a hung JRBC, so the post-reset ring test times out and the driver falls back to a full MODE1 reset. Temporarily force the static power-gating path during the reset so the stop/start sequence power-cycles the JPEG block (JMI soft reset + power off/on), matching the jpeg_v4_0 reset. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amdgpu: fix JPEG v5.0.0 queue reset failure in DPG modeJesse Zhang1-4/+17
In DPG mode jpeg_v5_0_0_ring_reset() takes the DPG stop path, which only clears the JPEG_PG_MODE bit and never resets the JRBC. A hung ring is not recovered: the post-reset ring test times out and the driver falls back to a full MODE1 reset. Temporarily force the static power-gating path during the reset so the stop/start sequence power-cycles the JPEG block (JMI soft reset + power off/on), matching the jpeg_v4_0 reset which has no DPG path. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/ssd130x: Add per-family update backlight logicAmit Barzilai1-3/+21
ssd130x_update_bl() runs for every SSD13xx panel, but it only works for SSD130x and SSD132x: it writes the single global SSD13XX_CONTRAST (0x81) command, which those two families expose. SSD133x has no such command -- it has three per-channel contrast registers (CONTRAST_A/B/C) that must be scaled together -- so ssd130x_update_bl() has no effect on it. Make backlight_ops.update_status a per-family choice. SSD130x and SSD132x keep ssd130x_update_bl() because they share the SSD13XX_CONTRAST interface, while SSD133x gets ssd133x_update_bl(), which drives the three channels through ssd133x_set_contrast(). Signed-off-by: Amit Barzilai <amit.barzilai22@gmail.com> Reviewed-by: Javier Martinez Canillas <javierm@redhat.com> Link: https://patch.msgid.link/20260729053054.29374-3-amit.barzilai22@gmail.com Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
2026-08-06drm/ssd130x: Scale ssd133x per-channel contrast by brightness on initAmit Barzilai1-3/+38
ssd133x_init() wrote the SSD133X_CONTRAST_A/B/C commands with magic hex values (0x91/0x50/0x7d). These are a per-channel white-balance calibration: the A/B/C channels drive sub-pixels whose OLED materials differ in luminous efficiency, so the values set the white point at full brightness. Extract them into ssd133x_set_contrast(), which scales each channel by a requested brightness via ssd130x_scale_contrast(), instead of writing the calibration unconditionally. This makes the sequence readable, avoids repetition, and is a prerequisite for wiring up an ssd133x backlight controller that dims while preserving the white point. Note this changes the ssd133x power-on brightness. Previously the init wrote the calibration unscaled and ignored ssd130x->contrast, so the panel always booted at full brightness. It now scales by the shared default contrast of 127, i.e. half of MAX_CONTRAST (255). This is intentional and matches ssd130x, whose contrast register also defaults to 127 (mid-scale), so all families now power on at ~50% and report props.brightness = 127 / max_brightness = 255 to userspace. Assisted-by: Claude:claude-fable-5 Signed-off-by: Amit Barzilai <amit.barzilai22@gmail.com> Reviewed-by: Javier Martinez Canillas <javierm@redhat.com> Link: https://patch.msgid.link/20260729053054.29374-2-amit.barzilai22@gmail.com Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
2026-08-06drm/tests/gpu_buddy: fix interleaving in buffer clearance testArunpravin Paneer Selvam1-24/+33
The resume clearance test skipped every other allocation, expecting an interleaved clear/dirty layout. But the buddy allocator hands out blocks contiguously, so this just allocated half the pages in one chunk and never exercised gpu_buddy_reset_clear()'s force-merge of opposite-state buddies. Allocate all pages into two lists instead and free one cleared, one dirty, to build a truly interleaved pattern. v2: Use for loops instead of do-while for the allocation loops (Jani Nikula) Fixes: e3335ccbf4da ("drm/tests/gpu_buddy: add a new test case for buffer clearance during resume") Reported-by: Sashiko-bot <sashiko-bot@kernel.org> Closes: https://sashiko.dev/#/patchset/20260721114236.507578-1-Arunpravin.PaneerSelvam@amd.com?part=1 Cc: Matthew Auld <matthew.auld@intel.com> Cc: Christian König <christian.koenig@amd.com> Assisted-by: GitHub_Copilot:claude-opus-4.8 Signed-off-by: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patch.msgid.link/20260803065656.2960810-1-Arunpravin.PaneerSelvam@amd.com
2026-08-06gpu/tests/gpu_buddy: Add KUnit test for gpu_buddy_allocated_addr_to_blockTejas Upadhyay1-0/+45
Add a new KUnit test gpu_test_buddy_addr_to_block() that validates the gpu_buddy_allocated_addr_to_block() helper which traces a address back to its allocated buddy block. The test covers: - Exact address matching returns the correct allocated block - An unallocated address inside the manager should return NULL - An address outside the manager should return -ENXIO v4(MattA): - Add test for unaligned address v3(Sashiko): - remove unused target_addr variable v2(Sashiko): - Drop the mutex and lockdep annotation; standalone KUnit tests do not register a driver lock. Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Signed-off-by: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com> Link: https://patch.msgid.link/20260806053624.3215216-6-tejas.upadhyay@intel.com
2026-08-06drm/gpu: Add gpu_buddy_allocated_addr_to_block helperTejas Upadhyay1-0/+53
Add helper with primary purpose is to efficiently trace a specific physical memory address back to its corresponding TTM buffer object. v3: - use mm->chunk_size minimum allocation granularity (Arun) v2: - %s/gpu_buddy_addr_to_block/gpu_buddy_allocated_addr_to_block(MattA) - remove clear->avail and split nodes check(MattA) - Adapt lockdep(MattB) Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com> Cc: Arunpravin Paneer Selvam <arunpravin.paneerselvam@amd.com> Cc: dri-devel@lists.freedesktop.org Reviewed-by: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com> Signed-off-by: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com> Link: https://patch.msgid.link/20260806053624.3215216-5-tejas.upadhyay@intel.com
2026-08-06drm/panthor: Check VMA boundaries for PMD mappingsChristian A. Ehrhardt1-1/+5
When checking a different patch[1] sashiko AI pointed out that panthor needs the same fix[2]: In the ->huge_fault handler do not install a PMD huge page mapping if the huge page exceeds the boundaries of the VMA. [1] https://lore.kernel.org/lkml/20260622215718.1532689-1-lk@c--e.de/ [2] https://sashiko.dev/#/patchset/20260622215718.1532689-1-lk%40c--e.de Cc: Boris Brezillon <boris.brezillon@collabora.com> Cc: Steven Price <steven.price@arm.com> Cc: Liviu Dudau <liviu.dudau@arm.com> Fixes: 68cbf96b1e9b ("drm/panthor: Part ways with drm_gem_shmem_object") Signed-off-by: Christian A. Ehrhardt <lk@c--e.de> Reviewed-by: Steven Price <steven.price@arm.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Link: https://lore.kernel.org/lkml/20260622215718.1532689-1-lk@c--e.de/ Link: https://patch.msgid.link/20260623181942.1536598-1-lk@c--e.de Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2026-08-06drm/sun4i: hdmi-phy: Fix H6 8-bit MPLL config at 594 MHzJernej Skrabec1-1/+1
The 8-bit entry of the last MPLL row (594 MHz) doesn't lock reliably on H6. 4K@60 RGB/YUV444, which is the mode that reaches this entry, doesn't come up. Align the value with the vendor driver. Other entries are left alone, they are used by lower pixel clocks which work fine. Tested with 4K@60 on a LG TV. Fixes: 0fb4b858b102 ("drm/sun4i: Add support for H6 HDMI PHY") Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Acked-by: Chen-Yu Tsai <wens@kernel.org> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Link: https://patch.msgid.link/aec9060209473b8176eb43bc7c63c20b21306adf.1785772659.git.jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2026-08-06drm/sun4i: Drop node references while building component listJernej Skrabec1-0/+3
Two references are leaked every time the display pipeline is walked: the output port node in sun4i_drv_traverse_endpoints(), which was never released since the driver was introduced, and each node taken out of the endpoint fifo in sun4i_drv_probe(), which stopped being released when the fifo was introduced. The latter is still safe to drop right after processing, since drm_of_component_match_add() takes its own reference. Fixes: 9026e0d122ac ("drm: Add Allwinner A10 Display Engine support") Fixes: 8b11aaface2b ("drm/sun4i: Implement endpoint parsing using kfifo") Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Acked-by: Chen-Yu Tsai <wens@kernel.org> Link: https://patch.msgid.link/759c74e3a22b97ca066ef7910ca4b91b852011e6.1785772659.git.jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2026-08-06drm/sun4i: dw-hdmi: Drop TCON TOP port referenceJernej Skrabec1-0/+2
When the HDMI controller is fed by TCON TOP, the port node used to enumerate the possible CRTCs is never released. Fixes: 57e23de02f48 ("drm/sun4i: DW HDMI: Expand algorithm for possible crtcs") Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Acked-by: Chen-Yu Tsai <wens@kernel.org> Link: https://patch.msgid.link/43ffcc17f7c3f94c1d7bd1ee89134c766e84df35.1785772659.git.jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2026-08-06drm/sun4i: tcon: Drop remote endpoint referenceJernej Skrabec1-0/+1
sun4i_tcon_of_get_id_from_port() never drops the reference taken by of_graph_get_remote_endpoint(). The function is not only called during bind, but also on every mode set through sun8i_r40_tcon_tv_set_mux(), so the leak accumulates. Fixes: e8d5bbf7f4c4 ("drm/sun4i: tcon: get TCON ID and matching engine with remote endpoint ID") Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Acked-by: Chen-Yu Tsai <wens@kernel.org> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/3f5ec952ad80cb51efebf2fe230df50259041a23.1785772659.git.jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2026-08-06drm/sun4i: crtc: Propagate layer initialization errorJernej Skrabec1-1/+1
sun4i_crtc_init() returns plain NULL when layer initialization fails, while all its other error paths return an error pointer. The only caller, sun4i_tcon_bind(), checks the result with IS_ERR() and happily continues with tcon->crtc set to NULL. sun4i_rgb_init() and sun4i_lvds_init() then dereference it in drm_crtc_mask(), which oopses. Return the error pointer instead. Fixes: dcd215801b02 ("drm/sun4i: Drop primary layer pointer from sun4i_drv") Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Acked-by: Chen-Yu Tsai <wens@kernel.org> Link: https://patch.msgid.link/b26a0d427d9dfae9c82e3ca90a67d24d8ece5a28.1785772659.git.jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2026-08-06drm/sun4i: hdmi: Don't leak sync polarity bits into packet controlJernej Skrabec1-1/+1
sun4i_hdmi_enable() keeps using the same variable after it programmed the video timing polarity register with it. The leftover TX_CLK, HSYNC and VSYNC bits are then ORed into the packet control register, where each nibble selects the packet type sent in one slot. As a result, slot 0 selects packet type 3 instead of the AVI infoframe whenever the mode has positive HSYNC polarity, and the TX_CLK bits set nibbles which the driver never programs. Assign the packet types instead of ORing them into the stale value. Fixes: 9ca6bc246035 ("drm/sun4i: hdmi: Move mode_set into enable") Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Acked-by: Chen-Yu Tsai <wens@kernel.org> Link: https://patch.msgid.link/51ba0918ce016a4b45313d5df1b6ce31b8c8731e.1785772659.git.jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
Copyright © 1996 – 2026 Jason A. Donenfeld. All Rights Reverse Engineered.