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2026-06-17drm/amd/display: Refactor surface_update_flags to flat struct with helpersRafal Ostrowski14-233/+343
[Why] The union surface_update_flags type uses a union with a raw uint32_t member to allow bulk clear/set/test operations on the bitfield. This couples the struct layout to a specific integer width, breaks when the number of flag bits exceeds 32, and scatters raw-access patterns across many call sites. Replacing the union with a plain struct and adding explicit helper functions makes the intent clearer and prepares the code for future flag-set expansion. [How] Rename union surface_update_flags to struct pipe_update_bits and remove the union wrapper, the .bits sub-struct, and the .raw member. Add inline helpers in dc.h: surface_update_flags_clear(), surface_update_flags_set_full(), and surface_update_flags_is_any_set() that operate on the new struct via memset/memcmp. Add stream_update_flags_clear() and stream_update_flags_set_full() in dc_stream.h for the stream update flags union. Update all callers: change the type name, replace .bits.field with .field, replace .raw = 0 with the clear helper, replace .raw = 0xFFFFFFFF with the set_full helper, and replace .raw boolean tests with is_any_set. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Rafal Ostrowski <rafal.ostrowski@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Enable pstate for DCN4 non-emulation buildsGabe Teeger1-1/+1
[Why] Pstate was disabled during bring-up to avoid interference. Now that bring-up is complete it can be enabled for non-emulation builds. [How] Set pstate_enabled to true in debug_defaults_drv for non-emulation DCN4 builds. Reviewed-by: Matthew Stewart <matthew.stewart2@amd.com> Signed-off-by: Gabe Teeger <gabe.teeger@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Add PSR Active VTotal Control capabilityRobin Chen3-1/+7
[WHY] The PSRSU-RC capability should be populated in DC during edp detection. Reviewed-by: Aric Cyr <aric.cyr@amd.com> Signed-off-by: Robin Chen <robin.chen@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Extract connector and encoder code to amdgpu_dm_connectorAlex Hung7-3646/+3820
Move connector lifecycle functions (init, detect, mode validation, property handling, EDID parsing, hotplug processing) and encoder functions (init, destroy, atomic_check, helper_funcs) from amdgpu_dm.c to amdgpu_dm_connector.c. No functional change intended. Assisted-by: Copilot:Claude-Opus-4.6 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Move HPD and IRQ handler code to amdgpu_dm_irqAlex Hung4-1500/+1538
Move HPD handling (workqueue creation, debounce, handler registration) and IRQ handler callbacks (vblank, pflip, vupdate, vline0, outbox) from amdgpu_dm.c into the existing amdgpu_dm_irq.c. This keeps all IRQ-related code together rather than creating additional files. No functional change intended. Assisted-by: Copilot:Claude-Opus-4.6 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Extract DMUB code to amdgpu_dm_dmubAlex Hung4-920/+1002
Move DMUB-related functions and firmware defines from amdgpu_dm.c into new amdgpu_dm_dmub.c and amdgpu_dm_dmub.h files to reduce the size of amdgpu_dm.c and improve code organization. No functional change intended. Assisted-by: Copilot:Claude-Opus-4.6 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Extract audio code to amdgpu_dm_audioAlex Hung4-267/+350
Move audio component, init/fini, ELD notification, fill_audio_info, and commit_audio functions from amdgpu_dm.c into a dedicated amdgpu_dm_audio.c file with its own header. No functional change intended. Assisted-by: Copilot:Claude-Opus-4.6 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Extract backlight code to amdgpu_dm_backlightAlex Hung6-619/+710
Move backlight-related functions from amdgpu_dm.c into a new amdgpu_dm_backlight.c file to improve code organization and reduce the size of the monolithic amdgpu_dm.c. No functional change intended. Assisted-by: Copilot:Claude-Opus-4.6 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Introduce dc_plane_cm and migrate surface update color pathRafal Ostrowski18-429/+587
[Why] Begin convergence with upstream Color Manager refactor (fda768acb2a1 "drm/amd/display: Sync dcn42 with DC 3.2.373") by consolidating fragmented per-plane CM state (shaper, 3DLUT, blend, CM2) into a single dc_plane_cm structure shared by dc_plane_state and dc_surface_update. Legacy fields are gated behind TRIM_CM2 so that it keeps compatibility with other repositories. [How] Refactored to use newer structures. No functional behavior change intended. Under !TRIM_CM2 the legacy fields are still populated for compatibility with other repositories. v2: squash in conflicting types fix Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Rafal Ostrowski <rafal.ostrowski@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Remove unused project_id from DML2 core instanceWenjing Liu3-5/+0
[Why] The project_id field stored in dml2_core_instance and related context structs was not consumed after initial setup and represents unnecessary coupling between the core layer and project-specific identifiers. [How] - Remove project_id field from dml2_core_instance - Remove the corresponding assignment in dml2_core_create Reviewed-by: Austin Zheng <austin.zheng@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Remove get_utm_qos_model from soc_and_ip_translatorWenjing Liu1-14/+0
[Why] The QoS model is now populated directly in clock manager from firmware data. The translator function pointer is no longer needed. [How] - Remove get_utm_qos_model function pointer from soc_and_ip_translator_funcs - Remove associated forward declarations from soc_and_ip_translator.h Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Add utm_qos_model pointer to clk_bw_paramsWenjing Liu1-0/+2
[Why] Add support for passing QoS model data from clock manager to bandwidth calculation consumers. [How] - Add forward declaration and const pointer for utm_qos_model in clk_bw_params Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Add a new interface to set idle opts in clock managerNicholas Kazlauskas1-0/+2
[Why & How] For future use in migrating the idle optimizations message to PMFW to DC core. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Increase dcn42b uclk valueGabe Teeger1-1/+1
Increase uclk value in order to enable UHBR20. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Gabe Teeger <gabe.teeger@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdgpu/ras: Add address sanity check for unirasCe Sun7-7/+68
Add address sanity check for uniras Signed-off-by: Ce Sun <cesun102@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdgpu: correct reservation fence slots for userq per-vm BOs evictionPrike Liang1-1/+2
It fixes both the move overflow and the eviction fence add for evicting these per-vm BOs. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdkfd: add sdma queue counter for gfxv9.4.3Eric Huang6-8/+107
since gfx 9.4.3 HW is calculating accumulated activity counter per-queue in register sdmax_rlcx_utilization_hi/lo, CPFW adds it in sdma MQD for save/restore, KFD will read it from there. gfx 9.4.2 will still keep the way to read from memory at rptr+8. v2: read dynamic counter directly from utilization register v3: add CPFW supported version check (Harish) Signed-off-by: Eric Huang <jinhuieric.huang@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdkfd: Add gfx11 queue/pipe reset support to topologyAmber Lin2-0/+4
Add gfx11 queue/pipe reset support to KFD topology Signed-off-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Jesse Zhang <jesse.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdkfd: Fix reset event signalAmber Lin1-1/+5
During the KFD/KCQ coordination rework, bad queues not requiring reset were combined into the rework and generated wrong reset signals to the process. Fix it by adding the reset check. Signed-off-by: Amber Lin <Amber.Lin@amd.com> Reviewed-by: Shaoyun Liu <shaoyun.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdgpu: Don't use UTS_RELEASE directlyUwe Kleine-König (The Capable Hub)1-2/+2
UTS_RELEASE evaluates to a static string and changes quite easily (e.g. uncommitted changes in the source tree or new commits). So when checking if a patch introduces changes to the resulting binary each usage of UTS_RELEASE is source of annoyance. Instead of using UTS_RELEASE directly use init_utsname()->release which evaluates to the same string but with that a change of UTS_RELEASE doesn't affect amdgpu_dev_coredump.o. Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org> Signed-off-by: Uwe Kleine-König (The Capable Hub) <u.kleine-koenig@baylibre.com> Link: https://patch.msgid.link/20260428144704.1114562-2-u.kleine-koenig@baylibre.com Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdgpu/gfx: fix cleaner shader IB buffer overflowAsad Kamal1-5/+5
The cleaner shader sysfs path allocates a 16-dword (64 byte) IB but incorrectly fills (align_mask + 1) dwords. On GFX rings align_mask is 0xff, so the loop wrote 256 dwords into a 64-byte buffer, causing a kernel page fault. The IB only needs to be a minimal NOP shell to schedule the job; the cleaner shader itself is emitted on the ring via emit_cleaner_shader(). Fill 16 dwords to match the allocation. v2: Use ib_size_dw variable (Lijo) Fixes: d361ad5d2fc0 ("drm/amdgpu: Add sysfs interface for running cleaner shader") Suggested-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Asad Kamal <asad.kamal@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdgpu/ras: Add flag to make VBIOS read optionalCe Sun1-1/+1
Add flag to make VBIOS read optional Signed-off-by: Ce Sun <cesun102@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdgpu: allocate lockdep mutex on the heap to fix stack overflowPrike Liang1-50/+53
Replace the stack-allocated amdgpu_lockdep mutex with a heap allocation via kmalloc to fix a stack overflow caused by the large struct size. Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdgpu/ras: added RAS EEPROM device support checkCe Sun1-1/+17
Added RAS EEPROM device support check Signed-off-by: Ce Sun <cesun102@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdgpu/ras: Parse all deferred errors with UMC aca handleCe Sun1-7/+6
We should only increase the deferred errors in UMC block Signed-off-by: Ce Sun <cesun102@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Promote DC to 3.2.385Taimur Hassan1-1/+1
Summary: * Display connectivity & HPD: - Retry link detection on resume, boot, and hotplug - Refactor HPD RX to use handle_hpd_irq_helper with detect reason - Always create delayed HPD work queue - Restore periodic detection for DCN35 * DCN42B support: - Fix DCN42B version detection - Add DCN42B to dml21_translation_helper * KUnit testing infrastructure: - Add KUnit tests for amdgpu_dm_pp_smu, amdgpu_dm_mst_types, and writeback connector - Extract HDCP and DPRX CRC transition helpers for KUnit - Export symbols for KUnit test modules - Enable warnings as errors for KUnit tests * Fixes & cleanups: - Fix compressed buffer config routine waiting time - Fix incorrect logic in CRC source handling - Fix writeback format loop and variable init - Fix max dispclk_khz/dppclk_khz double 1000 - Remove duplicate pp_rn_set_wm_ranges - Remove dead code in dm_dp_mst_get_modes - Remove redundant code in amdgpu_dm_replay - Skip PHY SSC reduction on some 8K panels - Temp disable repeater FGCG as workaround - Deprecate DMUB register offload functionality - TEST_HARNESS FSN could be 0 * Firmware: - DMUB FW promotion to 0.1.62.0 Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Alex Hung <alex.hung@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: fix compressed buffer config routine waiting timeAntonio Quartulli1-4/+4
Replace the four open-coded REG_WAIT calls with calls to dcn31_wait_for_det_apply() so the compressed buffer (compbuf) sizing path waits long enough for the DET size update to take effect, and the wait timing stays consistent across the driver. No functional change beyond the corrected timeout. Signed-off-by: Antonio Quartulli <antonio@mandelbit.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Alex Hung <alex.hung@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Use handle_hpd_irq_helper for HPD RXTimur Kristóf1-40/+1
Remove duplicated code and just call handle_hpd_irq_helper with the appropriate detect reason. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Alex Hung <alex.hung@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdkfd: Fix SMI event PID reporting for containersAndrew Martin5-56/+77
SMI events were reporting incorrect PIDs in containerized environments, causing test failures where container processes expected to see their namespace-local PIDs but instead received global host PIDs. The issue had two root causes: 1. Event functions were called from kernel context (page fault handlers, migration workers) where 'current' refers to the kernel worker thread, not the userspace GPU process that triggered the event. 2. PID conversion used task_tgid_vnr() which returns the PID in the caller's namespace (init namespace for kernel threads), not the task's own namespace. This patch updates the SMI event interface: - Change 8 event function signatures to accept task_struct pointer instead of pid_t, allowing proper namespace-aware PID conversion - Convert PIDs using task_tgid_nr_ns(task, task_active_pid_ns(task)) which returns the PID as the process sees it via getpid() - Update 10 call sites to pass p->lead_thread (the GPU process) instead of p->lead_thread->pid or current (kernel worker) This ensures SMI events report container-local PIDs, which is critical for containerized GPU workloads to correctly correlate events with their processes. Tested-by: Andrew Martin <andmarti@amd.com> Assisted-by: Claude:Sonnet 4-5 Signed-off-by: Andrew Martin <andrew.martin@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Add detect reason to handle_hpd_irq_helperTimur Kristóf1-7/+11
This makes it possible to reuse the function for other purposes in the next few commits, such as HPD RX. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Alex Hung <alex.hung@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdgpu/gfx: defer per-queue helper_end until after MES resumeJesse Zhang2-8/+65
amdgpu_gfx_reset_mes_compute() runs amdgpu_mes_suspend(adev, 0) to quiesce all gangs, resets the offending queue(s), then resumes. The existing amdgpu_gfx_mes_reset_queue() called amdgpu_ring_reset_helper_end() right after unmap/restore/map of the reset queue, which re-emits backed-up commands and rings the doorbell. That doorbell hits a still-suspended CP: on the subsequent resume the queue partially wedges -- the first new IB after the reset may execute but later submissions stall, which surfaces as repeated timeouts on the same ring under concurrent workloads. Split out amdgpu_gfx_mes_reset_queue_start() (backup + MES reset + unmap/restore/map only) and defer helper_end. amdgpu_gfx_reset_mes_compute() collects the (ring, fence) pair for every queue it resets and runs helper_end on each after amdgpu_mes_resume(), so the re-emit doorbells land on a running CP. amdgpu_gfx_reset_mes_kcq() now reports the matched ring/fence back to the caller for the same reason. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Jesse Zhang <jesse.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Add KUnit tests for amdgpu_dm_pp_smuAlex Hung4-2/+265
[WHAT] Add KUnit tests for two functions in amdgpu_dm_pp_smu.c: get_default_clock_levels and dc_to_pp_clock_type. Assisted-by: Copilot:Claude-Opus-4.6 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Remove duplicate pp_rn_set_wm_rangesAlex Hung1-12/+1
[WHAT] Remove pp_rn_set_wm_ranges and reuse the identical pp_nv_set_wm_ranges for the DCN_VERSION_2_1 case instead. Assisted-by: Copilot:Claude-Opus-4.6 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Restore periodic detection for DCN35Ivan Lipski3-4/+2
[Why&How] Periodic detection callbacks from DCN35 was removed for higher IPS residency causing some displays to fail to recover after DPMS sleep. The monitors bounces HPD ~1.2s after link training, and without periodic detection the system enters IPS with no mechanism to wake and rediscover the display. Restore the periodic detection calls in dcn35_clk_mgr for now. It should be replaced with a proper IPS-aware solution long term using DMUB. Also remove it from dcn31 and dcn314_clk_mgr.c since they do not have IPS, thus should not affect them. Fixes: 3f6c060846be ("drm/amd/display: Remove periodic detection callbacks from dcn35+") Closes: https://gitlab.freedesktop.org/drm/amd/-/work_items/5318 Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Extract HDCP testable helpers for KUnitAlex Hung3-54/+370
[WHAT] Extract hdcp_get_content_protection_from_status() and hdcp_get_link_display_adjustments() from event_property_update() and hdcp_update_display() so the pure decision logic can be KUnit-tested. Also update function comments to kernel-doc formats. Assisted-by: Copilot:Claude-Opus-4.6 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Extract DPRX CRC transition helpers for KUnit testingAlex Hung3-17/+203
Extract three pure predicate functions from amdgpu_dm_crtc_set_crc_source(): - dm_need_dp_aux - dm_crc_source_should_start_dprx - dm_crc_source_should_stop_dprx Refactor set_crc_source() to use these helpers, replacing the nested if/else if structure with flat, mutually-exclusive branches driven by the new predicates. Add KUnit test cases covering all relevant source combinations for each helper, including the regression case where DPRX→NONE must trigger drm_dp_stop_crc(). Assisted-by: Copilot:Claude-Sonnet-4.6 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Fix incorrect logic in CRC source handlingAlex Hung1-5/+5
[WHAT] Fix three issues amdgpu_dm_crc.c: - Use cur_crc_src instead of source when deciding whether to call drm_dp_stop_crc() in the disable path of set_crc_source(). When disabling CRC, source is always NONE so dm_is_crc_source_dprx(source) was always false, meaning drm_dp_stop_crc() was never called when stopping a DPRX CRC source. Use cur_crc_src to check what was previously active instead. - Replace fragile 'source < 0' comparisons in verify_crc_source() and set_crc_source() with AMDGPU_DM_PIPE_CRC_SOURCE_INVALID. and avoiding signed/unsigned enum comparison concerns. - Remove redundant NULL initializations for drm_dev and acrtc in handle_crc_irq(). Both variables are unconditionally assigned right after. Assisted-by: Copilot:Claude-Sonnet-4.6 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Add KUnit tests for amdgpu_dm_mst_typesAlex Hung4-0/+133
[WHAT] Add KUnit test coverage for needs_dsc_aux_workaround() in amdgpu_dm_mst_types.c. Tests verify the function correctly identifies links requiring the DSC AUX workaround based on branch device ID, DPCD revision, and sink count. Assisted-by: Copilot:Claude-Opus-4.6 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Remove dead code in dm_dp_mst_get_modesAlex Hung1-14/+9
[WHAT] Remove unreachable null check on aconnector after container_of, and redundant dc_sink checks where dc_sink is guaranteed non-NULL after earlier null-check with early return. Assisted-by: Copilot:Claude-Opus-4.6 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Enable warnings as errors for KUnit testsAlex Hung1-0/+3
[WHAT] Add CONFIG_WERROR=y to .kunitconfig to treat compiler warnings as errors during KUnit builds, ensuring warnings are caught early. Assisted-by: Copilot:Claude-Opus-4.6 Reviewed-by: Ray Wu <ray.wu@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: remove redundant code in amdgpu_dm_replayAlex Hung1-5/+2
[WHAT] In amdgpu_dm_link_setup_replay(), nom_coasting_vtotal was used only once immediately after in set_replay_coasting_vtotal(). Inline the value directly to remove the no-op alias. In amdgpu_dm_set_replay_caps(), replace link->ctx->dc->debug with dc->debug since dc is already assigned as link->ctx->dc, eliminating a redundant pointer round-trip. Assisted-by: Copilot:Claude-Sonnet-4.6 Reviewed-by: Ray Wu <ray.wu@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: fix max dispclk_khz/dppclk_khz double 1000Charlene Liu1-4/+4
[why] Fix regresson caused by double roundup and index out of range Reviewed-by: Dillon Varone <dillon.varone@amd.com> Reviewed-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Add KUnit tests for writeback connectorAlex Hung4-2/+355
[WHAT] Add KUnit tests for amdgpu_dm_wb_encoder_atomic_check() and amdgpu_dm_wb_connector_get_modes(). Tests cover null job, null fb, size mismatch, format validation, and mode count bounds using DRM KUnit mock devices. Assisted-by: Copilot:Claude-Opus-4.6 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Fix writeback format loop and variable initAlex Hung1-3/+5
[WHAT] 1. Use ARRAY_SIZE() instead of manual sizeof division for the format array iteration. Add a break statement to exit the loop early once a matching format is found. 2. Remove redundant zero initialization of res since all paths assign before use. Assisted-by: Copilot:Claude-Opus-4.6 Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Temp disable repeater FGCG as workaroundOvidiu Bunea5-2/+21
[why & how] There is an issue that is seemingly limited to DCN42 where systems with IOMMU enabled will hang during reboot stress testing. The hang happens shortly after DCN PG exit happens and HUBP is programmed for the first flip, but before the first surface address is latched. Testing has shown that disabling DCCG_GLOBAL_FGCG_REP_DIS, HUBP_FGCG_REP_DIS, and DCFCLK_GATE_DIS can mask this issue. Disable FGCG for these three repeater bits to avoid issue while debug is on-going. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Deprecate DMUB register offload functionalityAustin Zheng20-330/+0
[Why] The DMUB register offload feature should no longer be used. This was originally a debug feature for DCN21. No longer applicable to the DMUB programming model. [How] Remove DMUB register offload infrastructure including helper functions, structures, debug options, and register sequence macros. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Austin Zheng <Austin.Zheng@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: TEST_HARNESS FSN could be 0ChunTao Tso1-5/+4
The frame skipping number could be 0 if needed. Reviewed-by: Robin Chen <robin.chen@amd.com> Signed-off-by: ChunTao Tso <ChunTao.Tso@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amd/display: Skip PHY SSC reduction on some 8K panelsRoman Li1-3/+10
[Why] Some 8K displays cannot tolerate the reduced phy ssc value at high link utilization and show corruption or black screen. [How] Add an EDID panel-id quirk to utilize existing skip_phy_ssc_reduction flag. To pass the link into the quirk handler, change the signature of apply_edid_quirks() to take link as an argument. The dev local in dm_helpers_parse_edid_caps() becomes unused and is removed. Fixes: 5fa62c87cffd ("drm/amd/display: Add option to disable PHY SSC reduction on transmitter enable") Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Roman Li <Roman.Li@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdkfd: Extend MQDs in HBM to gfx944Kent Russell1-0/+1
This has proven stable and performant on gfx943 and gfx950, so extend it to gfx944 as well Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: David Francis <David.Francis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdkfd: Extend MQDs in HBM to gfx942Kent Russell1-0/+1
This has proven stable and performant on gfx943 and gfx950, so extend it to the Aldebaran/gfx942 series Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: David Francis <David.Francis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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