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2026-03-10drm/xe: Translate C-state "reset value" into RC6Gustavo Sousa2-0/+9
There are higher level sleep states that will cause RC6 state readout to come back with an "in-reset" value. That is the case with NVL-P. As those states are only possible if the GT is already in C6, let's just translate the "reset value" into C6 when doing the readout. Bspec: 67651 Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patch.msgid.link/20260309-extra-nvl-p-enabling-patches-v5-7-be9c902ee34e@intel.com Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
2026-03-10drm/xe/xe3p: Drop Wa_16028780921Gustavo Sousa2-7/+0
Wa_16028780921 involves writing to a register that is locked by firmware prior to driver loading and doesn't have any effect if implemented by the KMD. Since the implementation of the workaround actually belongs the firmware, just drop the ineffective implementation by the KMD. Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patch.msgid.link/20260309-extra-nvl-p-enabling-patches-v5-6-be9c902ee34e@intel.com Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
2026-03-10drm/xe/nvlp: Implement Wa_14026539277Gustavo Sousa3-0/+44
Implement the KMD part of Wa_14026539277, which applies to NVL-P A0. The KMD implementation is just one component of the workaround, which also depends on Pcode to implement its part in order to be complete. v2: - Add FUNC(xe_rtp_match_not_sriov_vf) to skip applying the workaround to SRIOV VFs. (Matt) v3: - Make Wa_14026539277 a device workaround instead of a GT workaround. (Matt) v4: - Drop FUNC(xe_rtp_match_not_sriov_vf) and use a direct check with IS_SRIOV_VF() in the workaround implementation. (Matt) Reviewed-by: Matt Roper <matthew.d.roper@intel.com> # v3 Link: https://patch.msgid.link/20260309-extra-nvl-p-enabling-patches-v5-5-be9c902ee34e@intel.com Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
2026-03-10drm/xe/rtp: Add support for matching platform-level steppingGustavo Sousa3-0/+28
Add support for matching platform-level stepping, which will be used for an upcoming NVL-P workaround. As support for reading platform-level stepping information is added only as needed in the driver, add a warning when the rule finds a STEP_NONE value, which is an indication that the driver is missing such a support. Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patch.msgid.link/20260309-extra-nvl-p-enabling-patches-v5-4-be9c902ee34e@intel.com Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
2026-03-10drm/xe/nvlp: Read platform-level stepping infoGustavo Sousa4-0/+27
There will be a NVL-P workaround for which we will need to know the platform-level stepping information in order to decide whether to apply it or not. While NVL-P has a nice mapping between the PCI revid and our symbolic stepping enumeration, not all platforms are like that: (i) Some platforms will have a single PCI revid used for a set platform level steppings (ii) and some might even require specific mappings. To make things simpler, let's include stepping information in the device info only on demand, for those platforms where it is needed for workaround checks. v2: - Call xe_step_platform_get() very early, to allow device workarounds to use it in early stages of device initialization. (Matt) Bspec: 74201 Reviewed-by: Matt Roper <matthew.d.roper@intel.com> # v1 Link: https://patch.msgid.link/20260309-extra-nvl-p-enabling-patches-v5-3-be9c902ee34e@intel.com Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
2026-03-10drm/xe: Drop unused IS_PLATFORM_STEP() and IS_SUBPLATFORM_STEP()Gustavo Sousa1-10/+0
The macros IS_PLATFORM_STEP() and IS_SUBPLATFORM_STEP() are unused since commit 87c299fa3a97 ("drm/xe/guc: Port Wa_14014475959 to xe_wa and fix it") and commit 63bbd800ff01 ("drm/xe/guc: Port Wa_22012727170/Wa_22012727685 to xe_wa"), respectively, and we can drop them now. Furthermore, in upcoming changes we will add logic to read platform-level step information from PCI RevID and keeping those macros around would potentially cause confusion. v2: - Cite commits that made the macros unused. (Matt) Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patch.msgid.link/20260309-extra-nvl-p-enabling-patches-v5-2-be9c902ee34e@intel.com Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
2026-03-10drm/xe: Modify stepping info directly in xe_step_*_get()Gustavo Sousa3-30/+36
In an upcoming change, we will add a member to struct xe_step_info to represent the platform-level stepping. As such, we should stop assigning the value returned by functions xe_step_pre_gmdid_get() and xe_step_gmdid_get() directly to xe->info.step. Since there are no other users for those functions, let's simply update them to modify xe->info.step directly. Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patch.msgid.link/20260309-extra-nvl-p-enabling-patches-v5-1-be9c902ee34e@intel.com Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
2026-03-10gpu: nova-core: fix stack overflow in GSP memory allocationTim Kovalenko2-17/+29
The `Cmdq::new` function was allocating a `PteArray` struct on the stack and was causing a stack overflow with 8216 bytes. Modify the `PteArray` to calculate and write the Page Table Entries directly into the coherent DMA buffer one-by-one. This reduces the stack usage quite a lot. Reported-by: Gary Guo <gary@garyguo.net> Closes: https://rust-for-linux.zulipchat.com/#narrow/channel/509436-Nova/topic/.60Cmdq.3A.3Anew.60.20uses.20excessive.20stack.20size/near/570375549 Link: https://lore.kernel.org/rust-for-linux/CANiq72mAQxbRJZDnik3Qmd4phvFwPA01O2jwaaXRh_T+2=L-qA@mail.gmail.com/ Fixes: f38b4f105cfc ("gpu: nova-core: Create initial Gsp") Acked-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Tim Kovalenko <tim.kovalenko@proton.me> Link: https://patch.msgid.link/20260309-drm-rust-next-v4-4-4ef485b19a4c@proton.me [ * Use PteArray::entry() in LogBuffer::new(), * Add TODO comment to use IoView projections once available, * Add PTE_ARRAY_SIZE constant to avoid duplication. - Danilo ] Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2026-03-10drm/i915: handle failure from vga_get_uninterruptible()Simon Richter1-7/+26
The vga_get_uninterruptible() function can return an error if it fails to set up VGA decoding for the requested device. If VGA decoding is unavailable, we don't need to be careful to leave the VGA emulation in a usable state, as vgacon will also be unable to get access later on, so just skip over the VGA accesses and the vga_put() call matching the failed vga_get_uninterruptible(). Signed-off-by: Simon Richter <Simon.Richter@hogyros.de> Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/1824 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260306151347.758836-1-Simon.Richter@hogyros.de
2026-03-10drm/xe: Allow per queue programming of COMMON_SLICE_CHICKEN3 bit13Lionel Landwerlin6-1/+33
Similar to i915's commit cebc13de7e704b1355bea208a9f9cdb042c74588 ("drm/i915: Whitelist COMMON_SLICE_CHICKEN3 for UMD access"), except that instead of putting the register on the allowlist for UMD to program, the KMD is doing the programming at context initialization based on a queue creation flag. This is a recommended tuning setting for both gen12 and Xe_HP platforms. If a render queue is created with DRM_XE_EXEC_QUEUE_SET_STATE_CACHE_PERF_FIX, COMMON_SLICE_CHICKEN3 will be programmed at initialization to enable the render color cache to key with BTP+BTI (binding table pool + binding table entry) instead of just BTI (binding table entry). This enables the UMD to avoid emitting render-target-cache-flush + stall-at-pixel-scoreboard every time a binding table entry pointing to a render target is changed. v2: Use xe_lrc_write_ring() v3: Update xe_query.c to report availability v4: Rename defines to add DISABLE_ v5: update commit message v6: rebase Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39982 Bspec: 73993, 73994, 72161, 31870, 68331 Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patch.msgid.link/20260306075504.1288676-1-lionel.g.landwerlin@intel.com
2026-03-10gpu/drm: panel: add support for DSI panel used in Motorola Atrix 4G and Droid X2Svyatoslav Ryhel3-0/+257
Add support for the DSI LCD panel module found in Motorola Atrix 4G or Droid X2 smartphones. Exact panel vendor and model are unknown hence panel uses generic compatible based on board where it is used. The panel has a 540x960 resolution with 24 bit RGB per pixel. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260223064630.12720-3-clamor95@gmail.com
2026-03-10drm/panel: Add Novatek/Tianma NT37700F panelRichard Acayan3-0/+309
Some Pixel 3a XL devices have a Tianma panel. Add support for it, with the aid of linux-mdss-dsi-panel-driver-generator. Link: https://github.com/msm8916-mainline/linux-mdss-dsi-panel-driver-generator Signed-off-by: Richard Acayan <mailingradian@gmail.com> Tested-by: Yifei Zhan <yifei@zhan.science> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260310002606.16413-4-mailingradian@gmail.com
2026-03-10drm/panel: simple: Add Waveshare 13.3" panel supportMarek Vasut1-0/+30
Add WaveShare 13.3inch 1920x1080 DSI Capacitive Touch Display support. While the panel is described as DPI panel, it is part of a larger unit in non-removable metal casing, so the actual internal configuration is not known. The panel is attached to "waveshare,dsi2dpi" bridge via DT. It is likely that internally, this panel is an LVDS panel, connected to ICN6211 DSI-to-DPI bridge and then another unknown DPI-to-LVDS bridge. Current device link is at https://www.waveshare.com/13.3inch-dsi-lcd.htm Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260117005028.126361-1-marek.vasut+renesas@mailbox.org
2026-03-10drm/panel: ilitek-ili9882t: use gpiod_set_value_cansleep()John Keeping1-7/+7
All of these GPIO calls are in process context where they can sleep. Use the appropriate function call to allow use of this driver with GPIO controllers that might sleep. Signed-off-by: John Keeping <jkeeping@inmusicbrands.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260303152124.187791-1-jkeeping@inmusicbrands.com
2026-03-10drm/panel: panel-jadard-jd9365da-h3: support for taiguan-xti05101-01a MIPI-DSI panelLangyan Ye1-0/+244
The taiguan-xti05101-01a is a 10.1" TFT panel. The MIPI controller on this panel is the same as the other panels here, so add this panel to this driver. Signed-off-by: Langyan Ye <yelangyan@huaqin.corp-partner.google.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260214085409.3489057-4-yelangyan@huaqin.corp-partner.google.com
2026-03-10drm/panel: add LXD M9189A panel driverRouven Czerwinski3-0/+253
The LXD M9189A panel is based on the EK79007AD3 DSI display controller. It currently supports only 4 lane operation. Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de> Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260218-drm-panel-ek79007ad3-v4-3-8ec448bf3ede@pengutronix.de
2026-03-10drm/panel: mantix: Set the pixel clocks for 60 HzSebastian Krzyszkowiak1-2/+2
These are 60 Hz panels, but the currently set pixel clocks result in modes with refresh rates of 63 Hz and ~63.41 Hz. Adjust the clocks to target 60 Hz. Signed-off-by: Sebastian Krzyszkowiak <sebastian.krzyszkowiak@puri.sm> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260218-mantix-pixel-clock-v1-1-c22c034ba5c1@puri.sm
2026-03-10drm/panel: simple: Add Powertip PH800480T032-ZHC19 panelFlorijan Plohl1-0/+30
Add support for the Powertip PH800480T032-ZHC19 7" (800x480) parallel LCD-TFT panel. Signed-off-by: Florijan Plohl <florijan.plohl@norik.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260217123759.169317-2-florijan.plohl@norik.com
2026-03-10drm/panel: mantix: Drop the shutdown callbackSebastian Krzyszkowiak1-11/+0
It's the responsibility of the DRM modeset driver to unprepare and disable the panel. Doing so here leads to regulator underflows. Signed-off-by: Sebastian Krzyszkowiak <sebastian.krzyszkowiak@puri.sm> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260216-mantix-shutdown-v1-1-d2e93a8ccc4c@puri.sm
2026-03-10drm/panel: r61307/r69328: convert to devm_mipi_dsi_attachSvyatoslav Ryhel2-12/+2
Switch to device managed version of mipi_dsi_attach. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260215085140.20499-6-clamor95@gmail.com Link: https://patch.msgid.link/20251204060627.4727-2-clamor95@gmail.com Link: https://patch.msgid.link/20251204060627.4727-3-clamor95@gmail.com Link: https://patch.msgid.link/20251204060627.4727-5-clamor95@gmail.com Link: https://patch.msgid.link/20251204060627.4727-6-clamor95@gmail.com Link: https://patch.msgid.link/20251204060627.4727-7-clamor95@gmail.com Link: https://patch.msgid.link/20251204060627.4727-8-clamor95@gmail.com
2026-03-10drm/panel: r61307/r69328: return accumulated errorsSvyatoslav Ryhel2-4/+4
Return accumulated errors from dsi function calls. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260215085140.20499-5-clamor95@gmail.com
2026-03-10drm/panel: r61307/r69328: remove redundant checksSvyatoslav Ryhel2-20/+0
This is now done by the DRM framework itself. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260215085140.20499-4-clamor95@gmail.com
2026-03-10drm/panel: r61307/r69328: convert to drm_connector_helper_get_modes_fixedSvyatoslav Ryhel3-28/+8
Switch to use of drm_connector_helper_get_modes_fixed helper for get_modes operation. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260215085140.20499-3-clamor95@gmail.com
2026-03-10drm/panel: r61307: align with schema propertySvyatoslav Ryhel1-1/+1
Rename renesas,inversion to renesas,column-inversion according to schema. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260215085140.20499-2-clamor95@gmail.com
2026-03-10drm/panel: simple: add EDT ET057023UDBA panelMarco Felsch1-0/+32
Add support for the EDT ET057023UDBA 5.7" 24-bit 640x480 DPI panel. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20260119-v6-18-topic-panel-simple-et057023udba-v2-2-3c73f0c9d87a@pengutronix.de
2026-03-10drm/xe: Add Wa_14026578760Varun Gupta2-0/+8
Add GT workaround Wa_14026578760 for graphics versions 35.10, 35.11 and media version 35.03. Signed-off-by: Varun Gupta <varun.gupta@intel.com> Reviewed-by: Tejas Upadhyay <tejas.upadhyay@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patch.msgid.link/20260309063923.4031933-1-varun.gupta@intel.com Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
2026-03-10gpu: nova-core: apply the one "use" item per line policy to commands.rsJohn Hubbard1-3/+9
As per [1], we need one "use" item per line, in order to reduce merge conflicts. Furthermore, we need a trailing ", //" in order to tell rustfmt(1) to leave it alone. This does that for commands.rs, which is the only file in nova-core that has any remaining instances of the old style. [1] https://docs.kernel.org/rust/coding-guidelines.html#imports Reviewed-by: Gary Guo <gary@garyguo.net> Signed-off-by: John Hubbard <jhubbard@nvidia.com> Link: https://patch.msgid.link/20260310021125.117855-7-jhubbard@nvidia.com Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
2026-03-10gpu: nova-core: add FbRange.len() and use it in boot.rsJohn Hubbard2-2/+8
A tiny simplification: now that FbLayout uses its own specific FbRange type, add an FbRange.len() method, and use that to (very slightly) simplify the calculation of Frts::frts_size initialization. Suggested-by: Alexandre Courbot <acourbot@nvidia.com> Reviewed-by: Gary Guo <gary@garyguo.net> Signed-off-by: John Hubbard <jhubbard@nvidia.com> Link: https://patch.msgid.link/20260310021125.117855-3-jhubbard@nvidia.com Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
2026-03-10gpu: nova-core: print FB sizes, along with rangesJohn Hubbard1-17/+66
For convenience of the reader: now you can directly see the sizes of each range. It is surprising just how much this helps. Sample output (using an Ampere GA104): NovaCore 0000:e1:00.0: FbLayout { fb: 0x0..0x3ff800000 (16376 MiB), vga_workspace: 0x3ff700000..0x3ff800000 (1 MiB), frts: 0x3ff600000..0x3ff700000 (1 MiB), boot: 0x3ff5fa000..0x3ff600000 (24 KiB), elf: 0x3fb960000..0x3ff5f9000 (60 MiB), wpr2_heap: 0x3f3900000..0x3fb900000 (128 MiB), wpr2: 0x3f3800000..0x3ff700000 (191 MiB), heap: 0x3f3700000..0x3f3800000 (1 MiB), vf_partition_count: 0x0, } Cc: Timur Tabi <ttabi@nvidia.com> Reviewed-by: Gary Guo <gary@garyguo.net> Signed-off-by: John Hubbard <jhubbard@nvidia.com> Link: https://patch.msgid.link/20260310021125.117855-2-jhubbard@nvidia.com Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
2026-03-10drm/i915/dp: Read ALPM caps after DPCD initArun R Murthy2-6/+7
For eDP read the ALPM DPCD caps after DPCD initalization and just before the PSR init. v2: Move intel_alpm_init to intel_edp_init_dpcd (Jouni) v3: Add Fixes with commit-id (Jouni) v4: Separated the alpm dpcd read caps from alpm_init and moved to intel_edp_init_dpcd. v5: Read alpm_caps always for eDP irrespective of the eDP version (Jouni) v6: replace drm_dp_dpcd_readb with drm_dp_dpcd_read_byte (Jouni) Fixes: 15438b325987 ("drm/i915/alpm: Add compute config for lobf") Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Link: https://patch.msgid.link/20260304072157.1123283-1-arun.r.murthy@intel.com (cherry picked from commit 88442ba208dd5d3405de3f5000cf5b2c86876ae3) Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
2026-03-10drm/i915/psr: Write DSC parameters on Selective Update in ET modeJouni Högander1-0/+10
There are slice row per frame and pic height parameters in DSC that needs to be configured on every Selective Update in Early Transport mode. Use helper provided by DSC code to configure these on Selective Update when in Early Transport mode. Also fill crtc_state->psr2_su_area with full frame area on full frame update for DSC calculation. v2: move psr2_su_area under skip_sel_fetch_set_loop label Bspec: 68927, 71709 Fixes: 467e4e061c44 ("drm/i915/psr: Enable psr2 early transport as possible") Cc: <stable@vger.kernel.org> # v6.9+ Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20260304113011.626542-5-jouni.hogander@intel.com (cherry picked from commit 3140af2fab505a4cd47d516284529bf1585628be) Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
2026-03-10drm/i915/dsc: Add helper for writing DSC Selective Update ET parametersJouni Högander2-0/+26
There are slice row per frame and pic height configuration in DSC Selective Update Parameter Set 1 register. Add helper for configuring these. v2: - Add WARN_ON_ONCE if vdsc instances per pipe > 2 - instead of checking vdsc instances per pipe being > 1 check == 2 Bspec: 71709 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20260304113011.626542-4-jouni.hogander@intel.com (cherry picked from commit c8698d61aeb3f70fe33761ee9d3d0e131b5bc2eb) Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net> [tursulin: fixup forward declaration conflict]
2026-03-10drm/i915/dsc: Add Selective Update register definitionsJouni Högander1-0/+12
Add definitions for DSC_SU_PARAMETER_SET_0_DSC0 and DSC_SU_PARAMETER_SET_0_DSC1 registers. These are for Selective Update Early Transport configuration. Bspec: 71709 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20260304113011.626542-3-jouni.hogander@intel.com (cherry picked from commit 24f96d903daf3dcf8fafe84d3d22b80ef47ba493) Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
2026-03-10drm/i915/psr: Repeat Selective Update area alignmentJouni Högander1-12/+38
Currently we are aligning Selective Update area to cover cursor fully if needed only once. It may happen that cursor is in Selective Update area after pipe alignment and after that covering cursor plane only partially. Fix this by looping alignment as long as alignment isn't needed anymore. v2: - do not unecessarily loop if cursor was already fully covered - rename aligned as su_area_changed Fixes: 1bff93b8bc27 ("drm/i915/psr: Extend SU area to cover cursor fully if needed") Cc: <stable@vger.kernel.org> # v6.9+ Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20260304113011.626542-2-jouni.hogander@intel.com (cherry picked from commit 681e12440d8b110350a5709101169f319e10ccbb) Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
2026-03-10drm/i915: Fix potential overflow of shmem scatterlist lengthJanusz Krzysztofik1-3/+9
When a scatterlists table of a GEM shmem object of size 4 GB or more is populated with pages allocated from a folio, unsigned int .length attribute of a scatterlist may get overflowed if total byte length of pages allocated to that single scatterlist happens to reach or cross the 4GB limit. As a consequence, users of the object may suffer from hitting unexpected, premature end of the object's backing pages. [278.780187] ------------[ cut here ]------------ [278.780377] WARNING: CPU: 1 PID: 2326 at drivers/gpu/drm/i915/i915_mm.c:55 remap_sg+0x199/0x1d0 [i915] ... [278.780654] CPU: 1 UID: 0 PID: 2326 Comm: gem_mmap_offset Tainted: G S U 6.17.0-rc1-CI_DRM_16981-ged823aaa0607+ #1 PREEMPT(voluntary) [278.780656] Tainted: [S]=CPU_OUT_OF_SPEC, [U]=USER [278.780658] Hardware name: Intel Corporation Meteor Lake Client Platform/MTL-P LP5x T3 RVP, BIOS MTLPFWI1.R00.3471.D91.2401310918 01/31/2024 [278.780659] RIP: 0010:remap_sg+0x199/0x1d0 [i915] ... [278.780786] Call Trace: [278.780787] <TASK> [278.780788] ? __apply_to_page_range+0x3e6/0x910 [278.780795] ? __pfx_remap_sg+0x10/0x10 [i915] [278.780906] apply_to_page_range+0x14/0x30 [278.780908] remap_io_sg+0x14d/0x260 [i915] [278.781013] vm_fault_cpu+0xd2/0x330 [i915] [278.781137] __do_fault+0x3a/0x1b0 [278.781140] do_fault+0x322/0x640 [278.781143] __handle_mm_fault+0x938/0xfd0 [278.781150] handle_mm_fault+0x12c/0x300 [278.781152] ? lock_mm_and_find_vma+0x4b/0x760 [278.781155] do_user_addr_fault+0x2d6/0x8e0 [278.781160] exc_page_fault+0x96/0x2c0 [278.781165] asm_exc_page_fault+0x27/0x30 ... That issue was apprehended by the author of a change that introduced it, and potential risk even annotated with a comment, but then never addressed. When adding folio pages to a scatterlist table, take care of byte length of any single scatterlist not exceeding max_segment. Fixes: 0b62af28f249b ("i915: convert shmem_sg_free_table() to use a folio_batch") Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14809 Cc: Matthew Wilcox (Oracle) <willy@infradead.org> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: stable@vger.kernel.org # v6.5+ Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik@linux.intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://lore.kernel.org/r/20260224094944.2447913-2-janusz.krzysztofik@linux.intel.com (cherry picked from commit 06249b4e691a75694c014a61708c007fb5755f60) Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
2026-03-10drm/i915/vrr: Configure VRR timings after enabling TRANS_DDI_FUNC_CTLVille Syrjälä2-1/+14
Apparently ICL may hang with an MCE if we write TRANS_VRR_VMAX/FLIPLINE before enabling TRANS_DDI_FUNC_CTL. Personally I was only able to reproduce a hang (on an Dell XPS 7390 2-in-1) with an external display connected via a dock using a dodgy type-C cable that made the link training fail. After the failed link training the machine would hang. TGL seemed immune to the problem for whatever reason. BSpec does tell us to configure VRR after enabling TRANS_DDI_FUNC_CTL as well. The DMC firmware also does the VRR restore in two stages: - first stage seems to be unconditional and includes TRANS_VRR_CTL and a few other VRR registers, among other things - second stage is conditional on the DDI being enabled, and includes TRANS_DDI_FUNC_CTL and TRANS_VRR_VMAX/VMIN/FLIPLINE, among other things So let's reorder the steps to match to avoid the hang, and toss in an extra WARN to make sure we don't screw this up later. BSpec: 22243 Cc: stable@vger.kernel.org Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reported-by: Benjamin Tissoires <bentiss@kernel.org> Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15777 Tested-by: Benjamin Tissoires <bentiss@kernel.org> Fixes: dda7dcd9da73 ("drm/i915/vrr: Use fixed timings for platforms that support VRR") Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20260303095414.4331-1-ville.syrjala@linux.intel.com Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> (cherry picked from commit 93f3a267c3dd4d811b224bb9e179a10d81456a74) Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
2026-03-10gpu: nova-core: gsp: add tests for continuation recordsEliot Courtney1-0/+138
Add tests for continuation record splitting. They cover boundary conditions at the split points to make sure the right number of continuation records are made. They also check that the data concatenated is correct. Tested-by: Zhi Wang <zhiw@nvidia.com> Signed-off-by: Eliot Courtney <ecourtney@nvidia.com> Link: https://patch.msgid.link/20260306-cmdq-continuation-v6-9-cc7b629200ee@nvidia.com Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
2026-03-10gpu: nova-core: gsp: support large RPCs via continuation recordEliot Courtney3-2/+207
Splits large RPCs if necessary and sends the remaining parts using continuation records. RPCs that do not need continuation records continue to write directly into the command buffer. Ones that do write into a staging buffer first, so there is one copy. Continuation record for receive is not necessary to support at the moment because those replies do not need to be read and are currently drained by retrying `receive_msg` on `ERANGE`. Signed-off-by: Eliot Courtney <ecourtney@nvidia.com> Link: https://patch.msgid.link/20260306-cmdq-continuation-v6-8-cc7b629200ee@nvidia.com Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
2026-03-10gpu: nova-core: gsp: add `size` helper to `CommandToGsp`Eliot Courtney1-3/+9
Add a default method to `CommandToGsp` which computes the size of a command. Tested-by: Zhi Wang <zhiw@nvidia.com> Signed-off-by: Eliot Courtney <ecourtney@nvidia.com> Link: https://patch.msgid.link/20260306-cmdq-continuation-v6-7-cc7b629200ee@nvidia.com Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
2026-03-10gpu: nova-core: gsp: unconditionally call variable payload handlingEliot Courtney1-8/+6
Unconditionally call the variable length payload code, which is a no-op if there is no such payload but could defensively catch some coding errors by e.g. checking that the allocated size is completely filled. Tested-by: Zhi Wang <zhiw@nvidia.com> Signed-off-by: Eliot Courtney <ecourtney@nvidia.com> Link: https://patch.msgid.link/20260306-cmdq-continuation-v6-6-cc7b629200ee@nvidia.com Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
2026-03-10gpu: nova-core: gsp: clarify invariant on command queueEliot Courtney1-1/+3
Clarify why using only the first returned slice from allocate_command for the message headers is okay. Tested-by: Zhi Wang <zhiw@nvidia.com> Signed-off-by: Eliot Courtney <ecourtney@nvidia.com> Link: https://patch.msgid.link/20260306-cmdq-continuation-v6-5-cc7b629200ee@nvidia.com Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
2026-03-10gpu: nova-core: gsp: add checking oversized commandsEliot Courtney3-1/+11
The limit is 16 pages for a single command sent to the GSP. Return an error if `allocate_command` is called with a too large size. Tested-by: Zhi Wang <zhiw@nvidia.com> Signed-off-by: Eliot Courtney <ecourtney@nvidia.com> Link: https://patch.msgid.link/20260306-cmdq-continuation-v6-4-cc7b629200ee@nvidia.com Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
2026-03-10gpu: nova-core: gsp: add mechanism to wait for space on command queueEliot Courtney1-12/+30
Add a timeout to `allocate_command` which waits for space on the GSP command queue. It uses a similar timeout to nouveau. This lets `send_command` wait for space to free up in the command queue. This is required to support continuation records which can fill up the queue. Tested-by: Zhi Wang <zhiw@nvidia.com> Signed-off-by: Eliot Courtney <ecourtney@nvidia.com> Link: https://patch.msgid.link/20260306-cmdq-continuation-v6-2-cc7b629200ee@nvidia.com Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
2026-03-10gpu: nova-core: gsp: sort `MsgFunction` variants alphabeticallyEliot Courtney1-32/+35
There is no particular order required here and keeping them alphabetical will help preventing future mistakes. Tested-by: Zhi Wang <zhiw@nvidia.com> Signed-off-by: Eliot Courtney <ecourtney@nvidia.com> Link: https://patch.msgid.link/20260306-cmdq-continuation-v6-1-cc7b629200ee@nvidia.com Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
2026-03-10drm: lcdif: Use dev_err_probe()Alexander Stein1-3/+5
Use dev_err_probe() to add a reason for deferred probe. This can especially happen on lcdif3 which uses hdmi_tx_phy for 'pix' clock Reviewed-by: Liu Ying <victor.liu@nxp.com> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Liu Ying <victor.liu@nxp.com> Link: https://lore.kernel.org/r/20260304140426.1499446-1-alexander.stein@ew.tq-group.com
2026-03-09drm/bridge: ti-sn65dsi83: halve horizontal syncs for dual LVDS outputLuca Ceresoli1-3/+4
Dual LVDS output (available on the SN65DSI84) requires HSYNC_PULSE_WIDTH and HORIZONTAL_BACK_PORCH to be divided by two with respect to the values used for single LVDS output. While not clearly stated in the datasheet, this is needed according to the DSI Tuner [0] output. It also makes sense intuitively because in dual LVDS output two pixels at a time are output and so the output clock is half of the pixel clock. Some dual-LVDS panels refuse to show any picture without this fix. Divide by two HORIZONTAL_FRONT_PORCH too, even though this register is used only for test pattern generation which is not currently implemented by this driver. [0] https://www.ti.com/tool/DSI-TUNER Fixes: ceb515ba29ba ("drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 and SN65DSI84 driver") Cc: stable@vger.kernel.org Reviewed-by: Marek Vasut <marek.vasut@mailbox.org> Link: https://patch.msgid.link/20260226-ti-sn65dsi83-dual-lvds-fixes-and-test-pattern-v1-2-2e15f5a9a6a0@bootlin.com Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
2026-03-09drm/bridge: ti-sn65dsi83: fix CHA_DSI_CLK_RANGE roundingLuca Ceresoli1-3/+3
The DSI frequency must be in the range: (CHA_DSI_CLK_RANGE * 5 MHz) <= DSI freq < ((CHA_DSI_CLK_RANGE + 1) * 5 MHz) So the register value should point to the lower range value, but DIV_ROUND_UP() rounds the division to the higher range value, resulting in an excess of 1 (unless the frequency is an exact multiple of 5 MHz). For example for a 437100000 MHz clock CHA_DSI_CLK_RANGE should be 87 (0x57): (87 * 5 = 435) <= 437.1 < (88 * 5 = 440) but current code returns 88 (0x58). Fix the computation by removing the DIV_ROUND_UP(). Fixes: ceb515ba29ba ("drm/bridge: ti-sn65dsi83: Add TI SN65DSI83 and SN65DSI84 driver") Cc: stable@vger.kernel.org Reviewed-by: Marek Vasut <marek.vasut@mailbox.org> Link: https://patch.msgid.link/20260226-ti-sn65dsi83-dual-lvds-fixes-and-test-pattern-v1-1-2e15f5a9a6a0@bootlin.com Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
2026-03-09drm/xe: Utilize for_each_gt_with_type() for type-specific GT loopsMatt Roper2-8/+2
Convert existing loops with Coccinelle via the following semantic patch: @@ identifier GT, XE, ID; iterator name for_each_gt, for_each_gt_with_type; @@ - for_each_gt(GT, XE, ID) { + for_each_gt_with_type(GT, XE, ID, BIT(XE_GT_TYPE_MAIN)) { - if (xe_gt_is_media_type(GT)) - continue; ... } @@ identifier GT, XE, ID; iterator name for_each_gt, for_each_gt_with_type; @@ - for_each_gt(GT, XE, ID) { + for_each_gt_with_type(GT, XE, ID, BIT(XE_GT_TYPE_MEDIA)) { - if (xe_gt_is_main_type(GT)) - continue; ... } @@ identifier GT, XE, ID; iterator name for_each_gt, for_each_gt_with_type; @@ - for_each_gt(GT, XE, ID) { + for_each_gt_with_type(GT, XE, ID, BIT(XE_GT_TYPE_MAIN)) { - if (!xe_gt_is_main_type(GT)) - continue; ... } @@ identifier GT, XE, ID; iterator name for_each_gt, for_each_gt_with_type; @@ - for_each_gt(GT, XE, ID) { + for_each_gt_with_type(GT, XE, ID, BIT(XE_GT_TYPE_MEDIA)) { - if (xe_gt_is_media_type(GT)) - continue; ... } No functional change expected. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patch.msgid.link/20260305-gt-type-loops-v1-2-aa42e9fc3f06@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2026-03-09drm/xe: Add for_each_gt_with_type() iteratorMatt Roper1-0/+4
There are a couple places in the driver today that have GT loops that only need to operate on a specific type of GT. E.g., for_each_gt(...) { if (xe_gt_is_media_type(gt)) continue; ... } Some upcoming development is expected to utilize this pattern a bit more widely, so add a dedicated iterator that allows looping over specific GT type(s). Note that this iterator uses a mask for the "type" parameter rather than a direct value match. That's probably a bit overkill for now given that there are only two possible types of GTs, but if additional types of GTs ever show up in the future, this approach will fit more naturally and allow cases where we might want to loop over a subset of the possible types, or specifically mask off one single type. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patch.msgid.link/20260305-gt-type-loops-v1-1-aa42e9fc3f06@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2026-03-09drm/bridge: cadence: cdns-mhdp8546-core: Reduce log level for DPCD read/writeJayesh Choudhary1-2/+2
Reduce the log level for cdns_mhdp_dpcd_read and cdns_mhdp_dpcd_write errors in cdns_mhdp_transfer function as in case of failure, there is flooding of these prints along with other indicators like EDID failure logs which are fairly intuitive in themselves rendering these error logs useless. Also, the caller functions for the cdns_mhdp_transfer in drm_dp_helper.c (which calls it 32 times), has debug log level in case transfer fails. So having a superseding log level in cdns_mhdp_transfer seems bad. Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Signed-off-by: Harikrishna Shenoy <h-shenoy@ti.com> Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Link: https://patch.msgid.link/20251209120332.3559893-7-h-shenoy@ti.com Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
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