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2026-02-23drm/xe: Consolidate workaround entries for Wa_15016589081Matt Roper1-8/+4
Wa_15016589081 applies to all graphics versions from 20.01 through 20.04 (inclusive). Consolidate the RTP entries into a single range-based entry. Reviewed-by: Shuicheng Lin <shuicheng.lin@intel.com> Link: https://patch.msgid.link/20260220-forupstream-wa_cleanup-v2-20-b12005a05af6@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2026-02-23drm/xe: Consolidate workaround entries for Wa_18033852989Matt Roper1-8/+4
Wa_18033852989 applies to all graphics versions from 20.01 through 20.04 (inclusive). Consolidate the RTP entries into a single range-based entry. Reviewed-by: Shuicheng Lin <shuicheng.lin@intel.com> Link: https://patch.msgid.link/20260220-forupstream-wa_cleanup-v2-19-b12005a05af6@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2026-02-23drm/xe: Consolidate workaround entries for Wa_14019988906Matt Roper1-8/+4
Wa_14019988906 applies to all graphics versions from 20.01 through 20.04 (inclusive). Consolidate the RTP entries into a single range-based entry. Reviewed-by: Shuicheng Lin <shuicheng.lin@intel.com> Link: https://patch.msgid.link/20260220-forupstream-wa_cleanup-v2-18-b12005a05af6@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2026-02-23drm/xe: Consolidate workaround entries for Wa_14019386621Matt Roper1-8/+4
Wa_14019386621 applies to all graphics versions from 20.01 through 20.04 (inclusive). Consolidate the RTP entries into a single range-based entry. Reviewed-by: Shuicheng Lin <shuicheng.lin@intel.com> Link: https://patch.msgid.link/20260220-forupstream-wa_cleanup-v2-17-b12005a05af6@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2026-02-23drm/xe: Consolidate workaround entries for Wa_14019877138Matt Roper1-16/+4
Wa_14019877138 applies to all graphics versions from 12.55 through 20.04 (inclusive) that have a render engine. Consolidate the RTP entries into a single range-based entry. Note that the DG2 entry for this workaround was missing an ENGINE_CLASS(RENDER) rule; that mistake is fixed by this consolidation. Reviewed-by: Shuicheng Lin <shuicheng.lin@intel.com> Link: https://patch.msgid.link/20260220-forupstream-wa_cleanup-v2-16-b12005a05af6@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2026-02-23drm/xe: Consolidate workaround entries for Wa_13012615864Matt Roper1-16/+5
Wa_13012615864 applies to all graphics versions from 20.01 through 30.05 (inclusive). Consolidate the RTP entries into a single range-based entry. Reviewed-by: Shuicheng Lin <shuicheng.lin@intel.com> Link: https://patch.msgid.link/20260220-forupstream-wa_cleanup-v2-14-b12005a05af6@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2026-02-23drm/xe: Consolidate workaround entries for Wa_14021402888Matt Roper1-17/+4
Wa_14021402888 applies to all graphics versions from 20.01 through 30.05 (inclusive). Consolidate the RTP entries into a single range-based entry. Reviewed-by: Shuicheng Lin <shuicheng.lin@intel.com> Link: https://patch.msgid.link/20260220-forupstream-wa_cleanup-v2-13-b12005a05af6@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2026-02-23drm/xe: Consolidate workaround entries for Wa_16021639441Matt Roper1-46/+13
Wa_16021639441 applies to all graphics versions from 20.01 through 20.04 (inclusive) and all media versions from 13.01 to 20.00 (inclusive). Consolidate the RTP entries into a single range-based entry. Also drop the reference to Wa_18032095049 which was only relevant to pre-production platforms that we no longer support. Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Link: https://patch.msgid.link/20260220-forupstream-wa_cleanup-v2-12-b12005a05af6@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2026-02-23drm/xe: Consolidate workaround entries for Wa_14018471104Matt Roper1-9/+5
Wa_14018471104 applies to all graphics versions from 20.01 through 20.04 (inclusive). Consolidate the two RTP entries into a single range-based entry. Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Link: https://patch.msgid.link/20260220-forupstream-wa_cleanup-v2-11-b12005a05af6@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2026-02-23drm/xe: Consolidate workaround entries for Wa_14020338487Matt Roper1-9/+5
Wa_14020338487 applies to all graphics versions from 20.01 through 20.04 (inclusive). Consolidate the two RTP entries into a single range-based entry. Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Link: https://patch.msgid.link/20260220-forupstream-wa_cleanup-v2-10-b12005a05af6@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2026-02-23drm/xe: Consolidate workaround entries for Wa_16018712365Matt Roper1-9/+5
Wa_16018712365 applies to all graphics versions from 20.01 through 20.04 (inclusive). Consolidate the two RTP entries into a single range-based entry. Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Link: https://patch.msgid.link/20260220-forupstream-wa_cleanup-v2-9-b12005a05af6@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2026-02-23drm/xe: Consolidate workaround entries for Wa_18032247524Matt Roper1-10/+7
Wa_18032247524 applies to all graphics versions from 20.01 through 20.04 (inclusive). Consolidate the two RTP entries into a single range-based entry. Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Link: https://patch.msgid.link/20260220-forupstream-wa_cleanup-v2-8-b12005a05af6@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2026-02-23drm/xe: Consolidate workaround entries for Wa_16021865536Matt Roper1-7/+1
Wa_16021865536 applies to both media versions 30.00 and 30.02; since version 30.01 is currently unused we can consolidate the two RTP entries into a single range-based entry. Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Link: https://patch.msgid.link/20260220-forupstream-wa_cleanup-v2-7-b12005a05af6@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2026-02-23drm/xe: Consolidate workaround entries for Wa_16028005424Matt Roper1-26/+5
Wa_16028005424 applies to all media IPs from 13.01 to 35.00 (inclusive) and all graphics IPs from 30.00 and 30.05 (inclusive). Conslidate the multiple RTP entries into a single range-based entry. Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Link: https://patch.msgid.link/20260220-forupstream-wa_cleanup-v2-6-b12005a05af6@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2026-02-23drm/xe: Consolidate workaround entries for Wa_14019449301Matt Roper1-10/+5
Wa_14019449301 applies to both media IP 13.01 and 20.00 and none of the version numbers between those are used. Conslidate the two entries into a single range entry. Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Link: https://patch.msgid.link/20260220-forupstream-wa_cleanup-v2-5-b12005a05af6@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2026-02-23drm/xe: Consolidate workaround entries for Wa_16021867713Matt Roper1-30/+8
Wa_16021867713 applies to every single media IP from 13.00 to 30.02 (inclusive). We can consolidate the multiple per-version entries down to a single range entry. Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Link: https://patch.msgid.link/20260220-forupstream-wa_cleanup-v2-4-b12005a05af6@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2026-02-23drm/xe/wa: Document new policy regarding workaround IP rangesMatt Roper1-0/+11
During early Xe driver development, our policy for applying workarounds to ranges of IP versions was to only use GRAPHICS_VERSION_RANGE and MEDIA_VERSION_RANGE rules when all of the affected IP versions had consecutive version numbers; otherwise separate RTP entries should be used. For example, a workaround that applies to all Xe2-based platforms would be implemented in the driver with two RTP entries: one using GRAPHICS_VERSION_RANGE(2001, 2002) and the other using GRAPHICS_VERSION(2004). This ensured that if a new IP variant showed up in the future with currently unused version 20.03, an old workaround entry wouldn't automatically apply to it by accident (and we could always consolidate those two distinct entries in the future if the workaround database did explicitly indicate that 20.03 also needed the workaround). Now that we're a couple years down the road with this driver, the number of IP versions supported is much larger (several Xe2 20.xx versions, several Xe3 30.xx versions, and a couple Xe3p 35.xx versions). When new workarounds are discovered that need to apply to a wide range of IPs, it's becoming more of a pain to create independent entries for each non-contiguous range of versions, and the general consensus is that we should revisit our previous policy and start allowing use of VERSION_RANGE constructs for non-contiguous version ranges. Note that allowing ranges that cover currently unused versions will require additional care if/when some of those intermediate version numbers start being used in the future. We'll need to re-check every workaround that has a range including the new IP version and check the hardware database to see whether the workaround also applies to the new version (no code change required) or whether we need to split the existing range into two separate ranges that don't cover the new version. The platform enabling engineers are willing to take on this extra review burden at the time we first enable a new IP in the driver (see lore link below for one recent discussion). Update the kerneldoc for the workaround file to make the new policy official. Link: https://lore.kernel.org/all/20260203233600.GT458797@mdroper-desk1.amr.corp.intel.com/ Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Link: https://patch.msgid.link/20260220-forupstream-wa_cleanup-v2-3-b12005a05af6@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2026-02-23drm/xe/pvc: Drop pre-prod workaroundsMatt Roper7-63/+0
Production PVC hardware had a graphics stepping of C0. Xe1 platforms already aren't officially supported by the Xe driver, but pre-production steppings are especially out of scope (and 'has_pre_prod_wa' is not set in the device descriptor). Drop the workarounds that aren't relevant to production hardware. v2: - Drop the stream->override_gucrc which is no longer set anywhere after the removal of Wa_1509372804. (Bala) - Drop xe_guc_rc_set_mode / xe_guc_rc_unset_mode which are no longer used after the removal of Wa_1509372804. Bspec: 44484 Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Link: https://patch.msgid.link/20260220-forupstream-wa_cleanup-v2-2-b12005a05af6@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2026-02-23drm/xe/mtl: Drop pre-prod workarounds Wa_14015795083 & Wa_14014475959Matt Roper2-6/+1
Wa_14015795083 and Wa_14014475959 only apply to early steppings of Xe_LPG that appeared only in pre-production hardware (in fact Wa_14014475959 wasn't supposed to apply to _any_ steppings of version 12.71). Xe1 platforms already aren't officially supported by the Xe driver, but pre-production steppings are especially out of scope (and 'has_pre_prod_wa' is not set in the device descriptor). Drop both workarounds. Bspec: 55420 Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Link: https://patch.msgid.link/20260220-forupstream-wa_cleanup-v2-1-b12005a05af6@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2026-02-24drm/msm/dpu: Don't use %pK through printk (again)Thomas Weißschuh1-1/+1
In the past %pK was preferable to %p as it would not leak raw pointer values into the kernel log. Since commit ad67b74d2469 ("printk: hash addresses printed with %p") the regular %p has been improved to avoid this issue. Furthermore, restricted pointers ("%pK") were never meant to be used through printk(). They can still unintentionally leak raw pointers or acquire sleeping locks in atomic contexts. Switch to the regular pointer formatting which is safer and easier to reason about. This was previously fixed in this driver in commit 1ba9fbe40337 ("drm/msm: Don't use %pK through printk") but an additional usage was reintroduced in commit 39a750ff5fc9 ("drm/msm/dpu: Add DSPP GC driver to provide GAMMA_LUT DRM property") Signed-off-by: Thomas Weißschuh <thomas.weissschuh@linutronix.de> Fixes: 39a750ff5fc9 ("drm/msm/dpu: Add DSPP GC driver to provide GAMMA_LUT DRM property") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/706229/ Link: https://lore.kernel.org/r/20260223-restricted-pointers-msm-v1-1-14c0b451e372@linutronix.de Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-02-24Revert "drm/msm/dpu: try reserving the DSPP-less LM first"Dmitry Baryshkov1-38/+14
This reverts commit 42f62cd79578 ("drm/msm/dpu: try reserving the DSPP-less LM first"). It seems on later DPUs using higher LMs require some additional setup or conflicts with the hardware defaults. Val (and other developers) reported blue screen on Hamoa (X1E80100) laptops. Revert the offending commit until we understand, what is the issue. Fixes: 42f62cd79578 ("drm/msm/dpu: try reserving the DSPP-less LM first") Reported-by: Val Packett <val@packett.cool> Closes: https://lore.kernel.org/r/33424a9d-10a6-4479-bba6-12f8ce60da1a@packett.cool Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Tested-by: Manivannan Sadhasivam <mani@kernel.org> # T14s Patchwork: https://patchwork.freedesktop.org/patch/704814/ Link: https://lore.kernel.org/r/20260214-revert-dspp-less-v1-1-be0d636a2a6e@oss.qualcomm.com
2026-02-24drm/msm/dpu: Fix smatch warnings about variable dereferenced before checksunliming1-1/+3
Fix below smatch warnings: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c:161 dpu_hw_sspp_setup_pe_config_v13() warn: variable dereferenced before check 'ctx' (see line 159) Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <error27@gmail.com> Closes: https://lore.kernel.org/r/202601252214.oEaY3UZM-lkp@intel.com/ Signed-off-by: sunliming <sunliming@kylinos.cn> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/701853/ Link: https://lore.kernel.org/r/20260130053615.24886-1-sunliming@linux.dev Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-02-24drm/msm: Adjust msm_iommu_pagetable_prealloc_allocate() allocation typeKees Cook1-1/+1
In preparation for making the kmalloc family of allocators type aware, we need to make sure that the returned type from the allocation matches the type of the variable being assigned. (Before, the allocator would always return "void *", which can be implicitly cast to any pointer type.) The assigned type is "void **" but the returned type will be "void ***". These are the same allocation size (pointer size), but the types do not match. Adjust the allocation type to match the assignment. Signed-off-by: Kees Cook <kees@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/703588/ Link: https://lore.kernel.org/r/20260206222151.work.016-kees@kernel.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-02-24drm/msm/dpu: Fix LM size on a number of platformsKonrad Dybcio5-30/+30
The register space has grown with what seems to be DPU8. Bump up the .len to match. Fixes: e3b1f369db5a ("drm/msm/dpu: Add X1E80100 support") Fixes: 4a352c2fc15a ("drm/msm/dpu: Introduce SC8280XP") Fixes: efcd0107727c ("drm/msm/dpu: add support for SM8550") Fixes: 100d7ef6995d ("drm/msm/dpu: add support for SM8450") Fixes: 178575173472 ("drm/msm/dpu: add catalog entry for SAR2130P") Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/701063/ Link: https://lore.kernel.org/r/20260127-topic-lm_size_fix-v1-1-25f88d014dfd@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-02-24drm/msm/adreno: Add GPU to MODULE_DEVICE_TABLEAkhil P Oommen1-0/+1
Since it is possible to independently probe Adreno GPU, add GPU match table to MODULE_DEVICE_TABLE to allow auto-loading of msm module. Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/700656/ Link: https://lore.kernel.org/r/20260124-adreno-module-table-v1-1-9c2dbb2638b4@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-02-23drm/xe/sync: Fix user fence leak on alloc failureShuicheng Lin1-2/+4
When dma_fence_chain_alloc() fails, properly release the user fence reference to prevent a memory leak. Fixes: 0995c2fc39b0 ("drm/xe: Enforce correct user fence signaling order using") Cc: Matthew Brost <matthew.brost@intel.com> Signed-off-by: Shuicheng Lin <shuicheng.lin@intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20260219233516.2938172-6-shuicheng.lin@intel.com (cherry picked from commit a5d5634cde48a9fcd68c8504aa07f89f175074a0) Cc: stable@vger.kernel.org Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2026-02-23drm/xe/sync: Cleanup partially initialized sync on parse failureShuicheng Lin1-7/+17
xe_sync_entry_parse() can allocate references (syncobj, fence, chain fence, or user fence) before hitting a later failure path. Several of those paths returned directly, leaving partially initialized state and leaking refs. Route these error paths through a common free_sync label and call xe_sync_entry_cleanup(sync) before returning the error. Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs") Cc: Matthew Brost <matthew.brost@intel.com> Signed-off-by: Shuicheng Lin <shuicheng.lin@intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20260219233516.2938172-5-shuicheng.lin@intel.com (cherry picked from commit f939bdd9207a5d1fc55cced5459858480686ce22) Cc: stable@vger.kernel.org Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2026-02-23drm/xe: Add prefetch fault support for Xe3pVarun Gupta4-11/+25
Xe3p hardware prefetches memory ranges and notifies software via an additional bit (bit 11) in the page fault descriptor that the fault was caused by prefetch. Extract the prefetch bit from the fault descriptor and echo it in the response (bit 6) only when the page fault handling fails. This allows the HW to suppress CAT errors for unsuccessful prefetch faults. For prefetch faults that fail, increment stats counter without verbose logging to avoid spamming the log. The prefetch flag is packed into BIT(7) of the access_type field to avoid growing the consumer struct. Based on original patches by Brian Welty <brian.welty@intel.com> and Priyanka Dandamudi <priyanka.dandamudi@intel.com>. Bspec: 59311 Cc: Matthew Brost <matthew.brost@intel.com> Cc: Priyanka Dandamudi <priyanka.dandamudi@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Varun Gupta <varun.gupta@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20260223061906.1420883-3-varun.gupta@intel.com
2026-02-23drm/xe: Add counter for invalid prefetch pagefaultsVarun Gupta2-0/+2
Add a stats counter for invalid prefetch page faults to avoid excessive logging. Cc: Matthew Brost <matthew.brost@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Varun Gupta <varun.gupta@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20260223061906.1420883-2-varun.gupta@intel.com
2026-02-23drm/amd/display: Fix kdoc formatting in dcn42_hwseq.cSrinivasan Shanmugam1-1/+1
Kernel-doc requires all lines within a documentation comment to start with " *". The previous empty line caused a "bad line" warning during build. Cc: Harry Wentland <harry.wentland@amd.com> Cc: Mario Limonciello <superm1@kernel.org> Cc: Alex Hung <alex.hung@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: ChiaHsuan Chung <chiahsuan.chung@amd.com> Cc: Roman Li <roman.li@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-02-23drm/amdgpu/userq: Use memdup_array_user in amdgpu_userq_signal_ioctlTvrtko Ursulin1-2/+2
Use the existing helper instead of multiplying the size. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Reviewed-by: Sunil Khatri <sunil.khatri@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-02-23drm/amdgpu/userq: Use memdup_array_user in amdgpu_userq_wait_ioctlTvrtko Ursulin1-6/+7
Use the existing helper instead of multiplying the size. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Reviewed-by: Sunil Khatri <sunil.khatri@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-02-23drm/amdgpu/sdma7.1: adjust SDMA limitsAlex Deucher1-2/+2
SDMA 7.1 has increased transfer limits. Cc: Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-02-23drm/amdgpu/sdma7.0: adjust SDMA limitsAlex Deucher1-2/+2
SDMA 7.0 has increased transfer limits. v2: fix harder, use shifts to make it more obvious Cc: Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-02-23drm/amdgpu/sdma6.0: adjust SDMA limitsAlex Deucher1-2/+2
SDMA 6.x has increased transfer limits. v2: fix harder, use shifts to make it more obvious Cc: Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-02-23drm/amdgpu/sdma5.2: adjust SDMA limitsAlex Deucher1-2/+2
SDMA 5.2.x has increased transfer limits. v2: fix harder, use shifts to make it more obvious v3: align const fill with PAL limits v4: re-align with hw limits Cc: Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-02-23drm/amdgpu/sdma4.4: adjust SDMA limitsAlex Deucher1-2/+2
SDMA 4.4.x has increased transfer limits. v2: fix harder, use shifts to make it more obvious Cc: Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-02-23drm/amdgpu/sdma4.0: adjust SDMA limitsAlex Deucher1-3/+16
SDMA 4.4.x has increased transfer limits. v2: fix harder, use shifts to make it more obvious Cc: Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-02-23drm/amd/display: Promote DC to 3.2.371Taimur Hassan1-1/+1
This version brings along the follwing updates: - Add visualconfirm support for refresh rate change testing. - Fix IPS exit with DC helper for all dc_set_power_state cases. - Fix cursor position at overlay plane edges on DCN4. - Introduce DMUB IHC command. - Add missing dprefclk and dtbclk clock types and fix formatting. - Fix DPIA number and driver ID field sizes per spec. - Minor code fixes. Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-02-23drm/amd/display: [FW Promotion] Release 0.1.48.0Taimur Hassan1-0/+54
[Why&How] Introduce DMUB IHC command. Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-02-23drm/amd/display: Add Visual Confirm Support for TestingMuaaz Nisar4-69/+105
[WHY+HOW] Adding visual confirm to visually track changes in refresh rate. Reviewed-by: Aric Cyr <aric.cyr@amd.com> Signed-off-by: Muaaz Nisar <muanisar@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-02-23drm/amd/display: Add missing clock types & fix formattingOvidiu Bunea1-4/+6
[why & how] Add the missing dprefclk and dtbclk clock types to the enum. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-02-23drm/amd/display: Fix dcn401_optimize_bandwidthCharlene Liu1-2/+2
[Why&How] We should check for != zstate disallow and programming extend blank from a different struct. Reviewed-by: Leo Chen <leo.chen@amd.com> Reviewed-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-02-23drm/amd/display: Silence type mismatch warningGaghik Khachatrian1-1/+1
[Why&How] Resolve type mismatch warnings by ensuring loop counters and compared values use matching unsigned types (size_t or int) in array iteration. Reviewed-by: Aric Cyr <aric.cyr@amd.com> Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-02-23drm/amd/display: Fix DPIA number and driver ID field issueCruise Hung2-3/+3
[Why] The DPIA number field is 6 bits in the spec. In dp_type, it only defines 5 bits. The driver ID is only 4 bits in the spec. [How] Set DPIA number field size to 6. And only update 4 bits for driver id. Reviewed-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Signed-off-by: Cruise Hung <Cruise.Hung@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-02-23drm/amd/display: Fix cursor pos at overlay plane edges on DCN4Ivan Lipski1-0/+19
[Why&How] On DCN4, when cursor straddles the left/top edge of an overlay plane, the recout-relative position becomes negative. These negative values wrap to large positive numbers when cast to uint32_t, causing the cursor on the the overlay plane to disappear. Fix by adding hotspot adjustment and position clamping after the recout-relative calculation, matching the existing ODM/MPC slice boundary handling. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-02-23drm/amd/display: Exit IPS w/ DC helper for all dc_set_power_state casesOvidiu Bunea1-2/+5
[why & how] On D3 path during dc_set_power_state, we may be in idle_allowed=true, at which point we will exit idle via dc_wake_and_execute_dmub_cmd_list which doesn't update dc->idle_optimizations_allowed to false. This would cause any future attempts to allow idle optimizations via the DC helper to get skipped because the value is stale and not reflective of the actual HW state. Move dc_exit_ips_for_hw_access() to the top of the function. Additionally ensure that dc_power_down_on_boot thread holds the DC lock and only runs if there are 0 streams. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-02-23drm/amdgpu: Add xgmi link status for VFsSimon Louis2-0/+5
Xgmi link status is unavailable in guest. This patch returns AMDGPU_XGMI_LINK_NA for VFs. Signed-off-by: Simon Louis <simon.louis@amd.com> Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-02-23drm/amd/display: Add atomfirmware cap for DP++ Type2Aurabindo Pillai1-0/+1
Add ATOM_CONNECTOR_CAP_DP_PLUS_PLUS_TYPE2_ONLY in atom connector caps definitions. Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Nevenko Stupar <nevenko.stupar@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-02-23drm/amdgpu: Print full vbios infoLijo Lazar1-2/+26
Add build number, version and date to the existing part number print. Example: [drm] ATOM BIOS: 113-PN000108-103, build: 00159017, ver: 022.040.003.043.000001, 2025/07/27 Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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