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2020-10-22Merge tag 'pci-v5.10-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pciLinus Torvalds40-1426/+1935
Pull PCI updates from Bjorn Helgaas: "Enumeration: - Print IRQ number used by PCIe Link Bandwidth Notification (Dongdong Liu) - Add schedule point in pci_read_config() to reduce max latency (Jiang Biao) - Add Kconfig options for MPS/MRRS strategy (Jim Quinlan) Resource management: - Fix pci_iounmap() memory leak when !CONFIG_GENERIC_IOMAP (Lorenzo Pieralisi) PCIe native device hotplug: - Reduce noisiness on hot removal (Lukas Wunner) Power management: - Revert "PCI/PM: Apply D2 delay as milliseconds, not microseconds" that was done on the basis of spec typo (Bjorn Helgaas) - Rename pci_dev.d3_delay to d3hot_delay to remove D3hot/D3cold ambiguity (Krzysztof Wilczyński) - Remove unused pcibios_pm_ops (Vaibhav Gupta) IOMMU: - Enable Translation Blocking for external devices to harden against DMA attacks (Rajat Jain) Error handling: - Add an ACPI APEI notifier chain for vendor CPER records to enable device-specific error handling (Shiju Jose) ASPM: - Remove struct aspm_register_info to simplify code (Saheed O. Bolarinwa) Amlogic Meson PCIe controller driver: - Build as module by default (Kevin Hilman) Ampere Altra PCIe controller driver: - Add MCFG quirk to work around non-standard ECAM implementation (Tuan Phan) Broadcom iProc PCIe controller driver: - Set affinity mask on MSI interrupts (Mark Tomlinson) Broadcom STB PCIe controller driver: - Make PCIE_BRCMSTB depend on ARCH_BRCMSTB (Jim Quinlan) - Add DT bindings for more Brcmstb chips (Jim Quinlan) - Add bcm7278 register info (Jim Quinlan) - Add bcm7278 PERST# support (Jim Quinlan) - Add suspend and resume pm_ops (Jim Quinlan) - Add control of rescal reset (Jim Quinlan) - Set additional internal memory DMA viewport sizes (Jim Quinlan) - Accommodate MSI for older chips (Jim Quinlan) - Set bus max burst size by chip type (Jim Quinlan) - Add support for bcm7211, bcm7216, bcm7445, bcm7278 (Jim Quinlan) Freescale i.MX6 PCIe controller driver: - Use dev_err_probe() to reduce redundant messages (Anson Huang) Freescale Layerscape PCIe controller driver: - Enforce 4K DMA buffer alignment in endpoint test (Hou Zhiqiang) - Add DT compatible strings for ls1088a, ls2088a (Xiaowei Bao) - Add endpoint support for ls1088a, ls2088a (Xiaowei Bao) - Add endpoint test support for lS1088a (Xiaowei Bao) - Add MSI-X support for ls1088a (Xiaowei Bao) HiSilicon HIP PCIe controller driver: - Handle HIP-specific errors via ACPI APEI (Yicong Yang) HiSilicon Kirin PCIe controller driver: - Return -EPROBE_DEFER if the GPIO isn't ready (Bean Huo) Intel VMD host bridge driver: - Factor out physical offset, bus offset, IRQ domain, IRQ allocation (Jon Derrick) - Use generic PCI PM correctly (Jon Derrick) Marvell Aardvark PCIe controller driver: - Fix compilation on s390 (Pali Rohár) - Implement driver 'remove' function and allow to build it as module (Pali Rohár) - Move PCIe reset card code to advk_pcie_train_link() (Pali Rohár) - Convert mvebu a3700 internal SMCC firmware return codes to errno (Pali Rohár) - Fix initialization with old Marvell's Arm Trusted Firmware (Pali Rohár) Microsoft Hyper-V host bridge driver: - Fix hibernation in case interrupts are not re-created (Dexuan Cui) NVIDIA Tegra PCIe controller driver: - Stop checking return value of debugfs_create() functions (Greg Kroah-Hartman) - Convert to use DEFINE_SEQ_ATTRIBUTE macro (Liu Shixin) Qualcomm PCIe controller driver: - Reset PCIe to work around Qsdk U-Boot issue (Ansuel Smith) Renesas R-Car PCIe controller driver: - Add DT documentation for r8a774a1, r8a774b1, r8a774e1 endpoints (Lad Prabhakar) - Add RZ/G2M, RZ/G2N, RZ/G2H IDs to endpoint test (Lad Prabhakar) - Add DT support for r8a7742 (Lad Prabhakar) Socionext UniPhier Pro5 controller driver: - Add DT descriptions of iATU register (host and endpoint) (Kunihiko Hayashi) Synopsys DesignWare PCIe controller driver: - Add link up check in dw_child_pcie_ops.map_bus() (racy, but seems unavoidable) (Hou Zhiqiang) - Fix endpoint Header Type check so multi-function devices work (Hou Zhiqiang) - Skip PCIE_MSI_INTR0* programming if MSI is disabled (Jisheng Zhang) - Stop leaking MSI page in suspend/resume (Jisheng Zhang) - Add common iATU register support instead of keystone-specific code (Kunihiko Hayashi) - Major config space access and other cleanups in dwc core and drivers that use it (al, exynos, histb, imx6, intel-gw, keystone, kirin, meson, qcom, tegra) (Rob Herring) - Add multiple PFs support for endpoint (Xiaowei Bao) - Add MSI-X doorbell mode in endpoint mode (Xiaowei Bao) Miscellaneous: - Use fallthrough pseudo-keyword (Gustavo A. R. Silva) - Fix "0 used as NULL pointer" warnings (Gustavo Pimentel) - Fix "cast truncates bits from constant value" warnings (Gustavo Pimentel) - Remove redundant zeroing for sg_init_table() (Julia Lawall) - Use scnprintf(), not snprintf(), in sysfs "show" functions (Krzysztof Wilczyński) - Remove unused assignments (Krzysztof Wilczyński) - Fix "0 used as NULL pointer" warning (Krzysztof Wilczyński) - Simplify bool comparisons (Krzysztof Wilczyński) - Use for_each_child_of_node() and for_each_node_by_name() (Qinglang Miao) - Simplify return expressions (Qinglang Miao)" * tag 'pci-v5.10-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (147 commits) PCI: vmd: Update VMD PM to correctly use generic PCI PM PCI: vmd: Create IRQ allocation helper PCI: vmd: Create IRQ Domain configuration helper PCI: vmd: Create bus offset configuration helper PCI: vmd: Create physical offset helper PCI: v3-semi: Remove unneeded break PCI: dwc: Add link up check in dw_child_pcie_ops.map_bus() PCI/ASPM: Remove struct pcie_link_state.l1ss PCI/ASPM: Remove struct aspm_register_info.l1ss_cap PCI/ASPM: Pass L1SS Capabilities value, not struct aspm_register_info PCI/ASPM: Remove struct aspm_register_info.l1ss_ctl1 PCI/ASPM: Remove struct aspm_register_info.l1ss_ctl2 (unused) PCI/ASPM: Remove struct aspm_register_info.l1ss_cap_ptr PCI/ASPM: Remove struct aspm_register_info.latency_encoding PCI/ASPM: Remove struct aspm_register_info.enabled PCI/ASPM: Remove struct aspm_register_info.support PCI/ASPM: Use 'parent' and 'child' for readability PCI/ASPM: Move LTR path check to where it's used PCI/ASPM: Move pci_clear_and_set_dword() earlier PCI: dwc: Fix MSI page leakage in suspend/resume ...
2020-10-21Merge branch 'remotes/lorenzo/pci/xilinx'Bjorn Helgaas1-4/+0
- Remove leftover bridge initialization (Lorenzo Pieralisi) * remotes/lorenzo/pci/xilinx: PCI: xilinx-cpm: Remove leftover bridge initialization
2020-10-21Merge branch 'remotes/lorenzo/pci/xgene'Bjorn Helgaas1-2/+2
- Remove unused assignment (Krzysztof Wilczyński) * remotes/lorenzo/pci/xgene: PCI: xgene: Remove unused assignment to variable msi_val
2020-10-21Merge branch 'pci/vmd'Bjorn Helgaas1-124/+182
- Add physical offset helper (Jon Derrick) - Add bus offset configuration helper (Jon Derrick) - Add IRQ domain configuration helper (Jon Derrick) - Add IRQ allocation helper (Jon Derrick) - Drop pci_save_state()/pci_restore_state() in favor of the PCI core PM (Jon Derrick) * pci/vmd: PCI: vmd: Update VMD PM to correctly use generic PCI PM PCI: vmd: Create IRQ allocation helper PCI: vmd: Create IRQ Domain configuration helper PCI: vmd: Create bus offset configuration helper PCI: vmd: Create physical offset helper
2020-10-21Merge branch 'remotes/lorenzo/pci/tegra'Bjorn Helgaas2-59/+12
- Drop return value checking for debugfs_create() calls (Greg Kroah-Hartman) - Convert debugfs "ports" file to use DEFINE_SEQ_ATTRIBUTE() (Liu Shixin) * remotes/lorenzo/pci/tegra: PCI: tegra: Convert to use DEFINE_SEQ_ATTRIBUTE macro PCI: tegra: No need to check return value of debugfs_create() functions
2020-10-21Merge branch 'remotes/lorenzo/pci/rcar'Bjorn Helgaas1-1/+1
- Document R8A774A1, R8A774B1, R8A774E1 endpoint support in DT (Lad Prabhakar) - Add R8A774A1, R8A774B1, R8A774E1 (RZ/G2M, RZ/G2N, RZ/G2H) IDs to endpoint test (Lad Prabhakar) - Add device tree support for R8A7742 (Lad Prabhakar) - Use "fallthrough" pseudo-keyword (Gustavo A. R. Silva) * remotes/lorenzo/pci/rcar: dt-bindings: PCI: rcar: Add device tree support for r8a7742 PCI: rcar-gen2: Use fallthrough pseudo-keyword misc: pci_endpoint_test: Add Device ID for RZ/G2H PCIe controller dt-bindings: pci: rcar-pci-ep: Document r8a774e1 misc: pci_endpoint_test: Add Device ID for RZ/G2M and RZ/G2N PCIe controllers dt-bindings: pci: rcar-pci-ep: Document r8a774a1 and r8a774b1
2020-10-21Merge branch 'remotes/lorenzo/pci/qcom'Bjorn Helgaas1-0/+13
- Make sure PCIe is reset before init to work around QSDK U-Boot issue (Ansuel Smith) - Set iproc affinity mask on MSI interrupts (Mark Tomlinson) * remotes/lorenzo/pci/qcom: PCI: qcom: Make sure PCIe is reset before init for rev 2.1.0
2020-10-21Merge branch 'remotes/lorenzo/pci/mvebu'Bjorn Helgaas1-3/+0
- Remove useless msi_controller pointer allocation (Lorenzo Pieralisi) * remotes/lorenzo/pci/mvebu: PCI: mvebu: Remove useless msi_controller pointer allocation
2020-10-21Merge branch 'remotes/lorenzo/pci/mobiveil'Bjorn Helgaas1-6/+1
- Simplify mobiveil_pcie_init_irq_domain() (Liu Shixin) * remotes/lorenzo/pci/mobiveil: PCI: mobiveil: Simplify mobiveil_pcie_init_irq_domain() return expression
2020-10-21Merge branch 'remotes/lorenzo/pci/meson'Bjorn Helgaas2-2/+9
- Add pci-meson module support and enable by default on ARCH_MESON (Kevin Hilman) * remotes/lorenzo/pci/meson: PCI: meson: Build as module by default
2020-10-21Merge branch 'remotes/lorenzo/pci/loongson'Bjorn Helgaas1-6/+1
* remotes/lorenzo/pci/loongson: PCI: loongson: Simplify loongson_pci_probe() return expression
2020-10-21Merge branch 'remotes/lorenzo/pci/kirin'Bjorn Helgaas1-1/+5
- Return -EPROBE_DEFER in case the gpio isn't ready (Bean Huo) * remotes/lorenzo/pci/kirin: PCI: kirin: Return -EPROBE_DEFER in case the gpio isn't ready
2020-10-21Merge branch 'remotes/lorenzo/pci/iproc'Bjorn Helgaas3-17/+11
- Set affinity mask on MSI interrupts (Mark Tomlinson) - Simplify by using module_bcma_driver (Liu Shixin) - Fix 'using integer as NULL pointer' warning (Krzysztof Wilczyński) * remotes/lorenzo/pci/iproc: PCI: iproc: Fix using plain integer as NULL pointer in iproc_pcie_pltfm_probe PCI: iproc: Use module_bcma_driver to simplify the code PCI: iproc: Set affinity mask on MSI interrupts
2020-10-21Merge branch 'remotes/lorenzo/pci/imx6'Bjorn Helgaas1-23/+18
- Use "fallthrough" pseudo-keyword (Gustavo A. R. Silva) - Drop redundant error messages after devm_clk_get() (Anson Huang) * remotes/lorenzo/pci/imx6: PCI: imx6: Do not output error message when devm_clk_get() failed with -EPROBE_DEFER PCI: imx6: Use fallthrough pseudo-keyword
2020-10-21Merge branch 'remotes/lorenzo/pci/hv'Bjorn Helgaas1-3/+47
- Fix hibernation in case interrupts are not re-created (Dexuan Cui) * remotes/lorenzo/pci/hv: PCI: hv: Fix hibernation in case interrupts are not re-created
2020-10-21Merge branch 'remotes/lorenzo/pci/dwc'Bjorn Helgaas20-1066/+848
- Fix designware-ep Header Type check (Hou Zhiqiang) - Use DBI accessors instead of own config accessors (Rob Herring) - Allow overriding bridge pci_ops (Rob Herring) - Allow root and child buses to have different pci_ops (Rob Herring) - Add default dwc pci_ops.map_bus (Rob Herring) - Use pci_ops for root config space accessors in al, exynos, histb, keystone, kirin, meson, tegra (Rob Herring) - Remove dwc own/other config accessor ops (Rob Herring) - Use generic config accessors in dwc (Rob Herring) - Also call .add_bus() callback for root bus (Rob Herring) - Convert keystone .scan_bus() callback to use pci_ops.add_bus (Rob Herring) - Convert dwc to use pci_host_probe() (Rob Herring) - Remove dwc root_bus pointer (Rob Herring) - Remove storing of PCI resources in dwc-specific structs (Rob Herring) - Simplify config space handling (Rob Herring) - Drop keystone duplicated DT num-viewport handling (Rob Herring) - Check CONFIG_PCI_MSI in dw_pcie_msi_init() instead of duplicating it in all the drivers (Rob Herring) - Remove imx6 duplicate PCIE_LINK_WIDTH_SPEED_CONTROL definition (Rob Herring) - Add dwc num_lanes for use when it's lacking from DT (Rob Herring) - Ensure "Fast Link Mode" simulation environment setting is cleared (Rob Herring) - Drop meson duplicate number of lanes setup (Rob Herring) - Drop meson unnecessary RC config space init (Rob Herring) - Rework meson config and dwc port logic register accesses (Rob Herring) - Use common PCI register definitions in imx6 and qcom (Rob Herring) - Search for DesignWare PCIe Capability instead of hard-coding its location (Rob Herring) - Use common DesignWare register definitions in tegra (Rob Herring) - Drop keystone unused DBI2 code (Rob Herring) - Make dwc ATU accessors private (Rob Herring) - Centralize link gen setting in dwc (Rob Herring) - Set PORT_LINK_DLL_LINK_EN in common dwc setup code (Rob Herring) - Drop intel-gw unnecessary DT 'device_type' checking (Rob Herring) - Move intel-gw PCI_CAP_ID_EXP discovery to the single place it's used (Rob Herring) - Drop intel-gw unused max_width (Rob Herring) - Move N_FTS (fast training sequence) setup to common dwc setup (Rob Herring) - Convert spear13xx, tegra194 to use DBI accessors (Rob Herring) - Add multiple PFs support for DWC (Xiaowei Bao) - Add MSI-X doorbell mode for endpoint mode (Xiaowei Bao) - Update MSI/MSI-X capability management for endpoints (Xiaowei Bao) - Add layerscape ls1088a and ls2088a compatible strings (Xiaowei Bao) - Update layerscape MSI/MSI-X management (Xiaowei Bao) - Use doorbell to support MSI-X on layerscape (Xiaowei Bao) - Add layerscape endpoint mode support for ls1088a and ls2088a (Xiaowei Bao) - Add layerscape ls1088a node to DT (Xiaowei Bao) - Add Freescale/Layerscape ls1088a to endpoint test (Xiaowei Bao) - Add endpoint test driver data for Layerscape PCIe controllers (Hou Zhiqiang) - Fix 'cast truncates bits from constant value' warning (Gustavo Pimentel) - Add uniphier iATU register description (Kunihiko Hayashi) - Add common iATU register support (Kunihiko Hayashi) - Remove keystone iATU register mapping in favor of generic dwc support (Kunihiko Hayashi) - Skip PCIE_MSI_INTR0* programming if MSI is disabled (Jisheng Zhang) - Fix MSI page leakage in suspend/resume (Jisheng Zhang) - Check whether link is up before attempting config access (best-effort fix even though it's racy) (Hou Zhiqiang) * remotes/lorenzo/pci/dwc: PCI: dwc: Add link up check in dw_child_pcie_ops.map_bus() PCI: dwc: Fix MSI page leakage in suspend/resume PCI: dwc: Skip PCIE_MSI_INTR0* programming if MSI is disabled PCI: keystone: Remove iATU register mapping PCI: dwc: Add common iATU register support dt-bindings: PCI: uniphier-ep: Add iATU register description dt-bindings: PCI: uniphier: Add iATU register description PCI: dwc: Fix 'cast truncates bits from constant value' misc: pci_endpoint_test: Add driver data for Layerscape PCIe controllers misc: pci_endpoint_test: Add LS1088a in pci_device_id table PCI: layerscape: Add EP mode support for ls1088a and ls2088a PCI: layerscape: Modify the MSIX to the doorbell mode PCI: layerscape: Modify the way of getting capability with different PEX PCI: layerscape: Fix some format issue of the code dt-bindings: pci: layerscape-pci: Add compatible strings for ls1088a and ls2088a PCI: designware-ep: Modify MSI and MSIX CAP way of finding PCI: designware-ep: Move the function of getting MSI capability forward PCI: designware-ep: Add the doorbell mode of MSI-X in EP mode PCI: designware-ep: Add multiple PFs support for DWC PCI: dwc: Use DBI accessors PCI: dwc: Move N_FTS setup to common setup PCI: dwc/intel-gw: Drop unused max_width PCI: dwc/intel-gw: Move getting PCI_CAP_ID_EXP offset to intel_pcie_link_setup() PCI: dwc/intel-gw: Drop unnecessary checking of DT 'device_type' property PCI: dwc: Set PORT_LINK_DLL_LINK_EN in common setup code PCI: dwc: Centralize link gen setting PCI: dwc: Make ATU accessors private PCI: dwc: Remove read_dbi2 code PCI: dwc/tegra: Use common Designware port logic register definitions PCI: dwc: Remove hardcoded PCI_CAP_ID_EXP offset PCI: dwc/qcom: Use common PCI register definitions PCI: dwc/imx6: Use common PCI register definitions PCI: dwc/meson: Rework PCI config and DW port logic register accesses PCI: dwc/meson: Drop unnecessary RC config space initialization PCI: dwc/meson: Drop the duplicate number of lanes setup PCI: dwc: Ensure FAST_LINK_MODE is cleared PCI: dwc: Add a 'num_lanes' field to struct dw_pcie PCI: dwc/imx6: Remove duplicate define PCIE_LINK_WIDTH_SPEED_CONTROL PCI: dwc: Check CONFIG_PCI_MSI inside dw_pcie_msi_init() PCI: dwc/keystone: Drop duplicated 'num-viewport' PCI: dwc: Simplify config space handling PCI: dwc: Remove storing of PCI resources PCI: dwc: Remove root_bus pointer PCI: dwc: Convert to use pci_host_probe() PCI: dwc: keystone: Convert .scan_bus() callback to use add_bus PCI: Also call .add_bus() callback for root bus PCI: dwc: Use generic config accessors PCI: dwc: Remove dwc specific config accessor ops PCI: dwc: histb: Use pci_ops for root config space accessors PCI: dwc: exynos: Use pci_ops for root config space accessors PCI: dwc: kirin: Use pci_ops for root config space accessors PCI: dwc: meson: Use pci_ops for root config space accessors PCI: dwc: tegra: Use pci_ops for root config space accessors PCI: dwc: keystone: Use pci_ops for config space accessors PCI: dwc: al: Use pci_ops for child config space accessors PCI: dwc: Add a default pci_ops.map_bus for root port PCI: dwc: Allow overriding bridge pci_ops PCI: dwc: Use DBI accessors instead of own config accessors PCI: Allow root and child buses to have different pci_ops PCI: designware-ep: Fix the Header Type check
2020-10-21Merge branch 'remotes/lorenzo/pci/cadence'Bjorn Helgaas2-7/+2
- Remove obsolete path from comment (Flavio Suligoi) - Simplify cdns_pcie_host_init_address_translation() (Qinglang Miao) * remotes/lorenzo/pci/cadence: PCI: cadence: Simplify cdns_pcie_host_init_address_translation() return expression PCI: cadence-ep: Remove obsolete path from comment
2020-10-21Merge branch 'remotes/lorenzo/pci/brcmstb'Bjorn Helgaas2-64/+383
- Make PCIE_BRCMSTB depend on and default to ARCH_BRCMSTB (Jim Quinlan) - Add DT bindings for 7278, 7216, 7211, and new properties (Jim Quinlan) - Add bcm7278 register info (Jim Quinlan) - Add suspend and resume pm_ops (Jim Quinlan) - Add bcm7278 PERST# support (Jim Quinlan) - Add control of RESCAL reset (Jim Quinlan) - Set additional internal memory DMA viewport sizes (Jim Quinlan) - Accommodate MSI for older chips (Jim Quinlan) - Set bus max burst size by chip type (Jim Quinlan) - Add bcm7211, bcm7216, bcm7445, bcm7278 to match list (Jim Quinlan) * remotes/lorenzo/pci/brcmstb: PCI: brcmstb: Add bcm7211, bcm7216, bcm7445, bcm7278 to match list PCI: brcmstb: Set bus max burst size by chip type PCI: brcmstb: Accommodate MSI for older chips PCI: brcmstb: Set additional internal memory DMA viewport sizes PCI: brcmstb: Add control of rescal reset PCI: brcmstb: Add bcm7278 PERST# support PCI: brcmstb: Add suspend and resume pm_ops PCI: brcmstb: Add bcm7278 register info dt-bindings: PCI: Add bindings for more Brcmstb chips PCI: brcmstb: PCIE_BRCMSTB depends on ARCH_BRCMSTB
2020-10-21Merge branch 'remotes/lorenzo/pci/aardvark'Bjorn Helgaas2-40/+70
- Fix s390 build error (Pali Rohár) - Check for errors from pci_bridge_emul_init() (Pali Rohár) - Export pci-bridge-emul functions for use by modules (Pali Rohár) - Make aardvark driver modular (Pali Rohár) - Move PCIe reset code to advk_pcie_train_link() (Pali Rohár) - Convert internal SMCC firmware return codes to errno (Pali Rohár) - Fix initialization with old Marvell's Arm Trusted Firmware (Pali Rohár) * remotes/lorenzo/pci/aardvark: PCI: aardvark: Fix initialization with old Marvell's Arm Trusted Firmware phy: marvell: comphy: Convert internal SMCC firmware return codes to errno PCI: aardvark: Move PCIe reset card code to advk_pcie_train_link() PCI: aardvark: Implement driver 'remove' function and allow to build it as module PCI: pci-bridge-emul: Export API functions PCI: aardvark: Check for errors from pci_bridge_emul_init() call PCI: aardvark: Fix compilation on s390
2020-10-21Merge branch 'remotes/lorenzo/pci/apei'Bjorn Helgaas3-0/+335
- Add ACPI APEI notifier chain for unknown (vendor) CPER records (Shiju Jose) - Add handling of HiSilicon HIP PCIe controller errors (Yicong Yang) * remotes/lorenzo/pci/apei: PCI: hip: Add handling of HiSilicon HIP PCIe controller errors ACPI / APEI: Add a notifier chain for unknown (vendor) CPER records
2020-10-21PCI: vmd: Update VMD PM to correctly use generic PCI PMJon Derrick1-2/+0
The pci_save_state() call in vmd_suspend() can be performed by pci_pm_suspend_irq(). This also allows VMD to benefit from the call into pci_prepare_to_sleep(). The pci_restore_state() call in vmd_resume() was restoring state after pci_pm_resume()::pci_restore_standard_config() had already restored state. It's also been suspected that the config state should have been restored before re-requesting IRQs instead of afterwards. Remove the pci_save_state()/pci_restore_state() calls in vmd_suspend()/vmd_resume() to allow proper flow through generic PCI core Power Management code. Link: https://lore.kernel.org/r/20200806210017.5654-1-jonathan.derrick@intel.com Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Kai-Heng Feng <kai.heng.feng@canonical.com> Cc: You-Sheng Yang <vicamo.yang@canonical.com>
2020-10-20PCI: vmd: Create IRQ allocation helperJon Derrick1-41/+53
Move the IRQ allocation and SRCU initialization code to a new helper. No functional changes. Link: https://lore.kernel.org/r/20200728194945.14126-5-jonathan.derrick@intel.com Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
2020-10-20PCI: vmd: Create IRQ Domain configuration helperJon Derrick1-17/+35
Move the IRQ and MSI Domain configuration code to new helpers. No functional changes. Link: https://lore.kernel.org/r/20200728194945.14126-4-jonathan.derrick@intel.com Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
2020-10-20PCI: vmd: Create bus offset configuration helperJon Derrick1-21/+32
Move the bus offset configuration discovery code to a new helper. Modify the bus offset 2-bit decode switch to have a 0 case and a default error case, just in case the field is expanded in future hardware. Link: https://lore.kernel.org/r/20200728194945.14126-3-jonathan.derrick@intel.com Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
2020-10-20PCI: vmd: Create physical offset helperJon Derrick1-43/+62
Move the guest-passthrough physical offset discovery code to a new helper. No functional changes. Link: https://lore.kernel.org/r/20200728194945.14126-2-jonathan.derrick@intel.com Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
2020-10-20PCI: v3-semi: Remove unneeded breakTom Rix1-1/+0
A break is not needed if it is preceded by a return Link: https://lore.kernel.org/r/20201019190249.7825-1-trix@redhat.com Signed-off-by: Tom Rix <trix@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2020-10-20PCI: dwc: Add link up check in dw_child_pcie_ops.map_bus()Hou Zhiqiang1-0/+11
NXP Layerscape (ls1028a, ls2088a), dra7xxx and imx6 platforms are either programmed or statically configured to forward the error triggered by a link-down state (eg no connected endpoint device) on the system bus for PCI configuration transactions; these errors are reported as an SError at system level, which is fatal. Enumerating a PCI tree when the PCIe link is down is not sensible either, so even if the link-up check is racy (link can go down after map_bus() is called) add a link-up check in map_bus() to prevent issuing configuration transactions when the link is down. SError report: SError Interrupt on CPU2, code 0xbf000002 -- SError CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.9.0-rc5-next-20200914-00001-gf965d3ec86fa #67 Hardware name: LS1046A RDB Board (DT) pstate: 20000085 (nzCv daIf -PAN -UAO BTYPE=--) pc : pci_generic_config_read+0x3c/0xe0 lr : pci_generic_config_read+0x24/0xe0 sp : ffff80001003b7b0 x29: ffff80001003b7b0 x28: ffff80001003ba74 x27: ffff000971d96800 x26: ffff00096e77e0a8 x25: ffff80001003b874 x24: ffff80001003b924 x23: 0000000000000004 x22: 0000000000000000 x21: 0000000000000000 x20: ffff80001003b874 x19: 0000000000000004 x18: ffffffffffffffff x17: 00000000000000c0 x16: fffffe0025981840 x15: ffffb94c75b69948 x14: 62203a383634203a x13: 666e6f635f726568 x12: 202c31203d207265 x11: 626d756e3e2d7375 x10: 656877202c307830 x9 : 203d206e66766564 x8 : 0000000000000908 x7 : 0000000000000908 x6 : ffff800010900000 x5 : ffff00096e77e080 x4 : 0000000000000000 x3 : 0000000000000003 x2 : 84fa3440ff7e7000 x1 : 0000000000000000 x0 : ffff800010034000 Kernel panic - not syncing: Asynchronous SError Interrupt CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.9.0-rc5-next-20200914-00001-gf965d3ec86fa #67 Hardware name: LS1046A RDB Board (DT) Call trace: dump_backtrace+0x0/0x1c0 show_stack+0x18/0x28 dump_stack+0xd8/0x134 panic+0x180/0x398 add_taint+0x0/0xb0 arm64_serror_panic+0x78/0x88 do_serror+0x68/0x180 el1_error+0x84/0x100 pci_generic_config_read+0x3c/0xe0 dw_pcie_rd_other_conf+0x78/0x110 pci_bus_read_config_dword+0x88/0xe8 pci_bus_generic_read_dev_vendor_id+0x30/0x1b0 pci_bus_read_dev_vendor_id+0x4c/0x78 pci_scan_single_device+0x80/0x100 Link: https://lore.kernel.org/r/20200916054130.8685-1-Zhiqiang.Hou@nxp.com Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [lorenzo.pieralisi@arm.com: rewrote the commit log, remove Fixes tag] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2020-10-15Merge tag 'usb-5.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usbLinus Torvalds1-17/+0
Pull USB/PHY/Thunderbolt driver updates from Greg KH: "Here is the big set of USB, PHY, and Thunderbolt driver updates for 5.10-rc1. Lots of tiny different things for these subsystems are in here, including: - phy driver updates - thunderbolt / USB 4 updates and additions - USB gadget driver updates - xhci fixes and updates - typec driver additions and updates - api conversions to various drivers for core kernel api changes - new USB control message functions to make it harder to get wrong, as found by syzbot (took 2 tries to get it right) - lots of tiny USB driver fixes and updates all over the place All of these have been in linux-next for a while, with the exception of the last "obviously correct" patch that updated a FALLTHROUGH comment that got merged last weekend" * tag 'usb-5.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (374 commits) usb: musb: gadget: Use fallthrough pseudo-keyword usb: typec: Add QCOM PMIC typec detection driver USB: serial: option: add Cellient MPL200 card usb: typec: tcpci_maxim: Add support for Sink FRS usb: typec: tcpci: Implement callbacks for FRS usb: typec: tcpm: Add support for Sink Fast Role SWAP(FRS) usb: typec: tcpci_maxim: Chip level TCPC driver usb: typec: tcpci: Add set_vbus tcpci callback usb: typec: tcpci: Add a getter method to retrieve tcpm_port reference usbip: vhci_hcd: fix calling usb_hcd_giveback_urb() with irqs enabled usb: cdc-acm: add quirk to blacklist ETAS ES58X devices USB: serial: ftdi_sio: use cur_altsetting for consistency USB: serial: option: Add Telit FT980-KS composition USB: core: remove polling for /sys/kernel/debug/usb/devices usb: typec: add support for STUSB160x Type-C controller family usb: typec: add typec_find_pwr_opmode usb: typec: hd3ss3220: Use OF graph API to get the connector fwnode dt-bindings: usb: renesas,usb3-peri: Document HS and SS data bus dt-bindings: usb: convert ti,hd3ss3220 bindings to json-schema usb: dwc2: Fix INTR OUT transfers in DDMA mode. ...
2020-10-14Merge tag 'hyperv-next-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linuxLinus Torvalds1-1/+4
Pull Hyper-V updates from Wei Liu: - a series from Boqun Feng to support page size larger than 4K - a few miscellaneous clean-ups * tag 'hyperv-next-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux: hv: clocksource: Add notrace attribute to read_hv_sched_clock_*() functions x86/hyperv: Remove aliases with X64 in their name PCI: hv: Document missing hv_pci_protocol_negotiation() parameter scsi: storvsc: Support PAGE_SIZE larger than 4K Driver: hv: util: Use VMBUS_RING_SIZE() for ringbuffer sizes HID: hyperv: Use VMBUS_RING_SIZE() for ringbuffer sizes Input: hyperv-keyboard: Use VMBUS_RING_SIZE() for ringbuffer sizes hv_netvsc: Use HV_HYP_PAGE_SIZE for Hyper-V communication hv: hyperv.h: Introduce some hvpfn helper functions Drivers: hv: vmbus: Move virt_to_hvpfn() to hyperv header Drivers: hv: Use HV_HYP_PAGE in hv_synic_enable_regs() Drivers: hv: vmbus: Introduce types of GPADL Drivers: hv: vmbus: Move __vmbus_open() Drivers: hv: vmbus: Always use HV_HYP_PAGE_SIZE for gpadl drivers: hv: remove cast from hyperv_die_event
2020-10-13PCI: dwc: Fix MSI page leakage in suspend/resumeJisheng Zhang3-17/+36
Currently, dw_pcie_msi_init() allocates and maps page for msi, then program the PCIE_MSI_ADDR_LO and PCIE_MSI_ADDR_HI. The Root Complex may lose power during suspend-to-RAM, so when we resume, we want to redo the latter but not the former. If designware based driver (for example, pcie-tegra194.c) calls dw_pcie_msi_init() in resume path, the msi page will be leaked. As pointed out by Rob and Ard, there's no need to allocate a page for the MSI address, we could use an address in the driver data. To avoid map the MSI msg again during resume, we move the map MSI msg from dw_pcie_msi_init() to dw_pcie_host_init(). Suggested-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201009155505.5a580ef5@xhacker.debian Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
2020-10-13PCI: dwc: Skip PCIE_MSI_INTR0* programming if MSI is disabledJisheng Zhang1-1/+1
If MSI is disabled, there's no need to program PCIE_MSI_INTR0_MASK and PCIE_MSI_INTR0_ENABLE registers. Link: https://lore.kernel.org/r/20201009155436.27e67238@xhacker.debian Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
2020-10-13PCI: keystone: Remove iATU register mappingKunihiko Hayashi1-16/+4
After applying "PCI: dwc: Add common iATU register support", there is no need to set own iATU in the Keystone driver itself. Suggested-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1601444167-11316-5-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
2020-10-13PCI: dwc: Add common iATU register supportKunihiko Hayashi1-0/+5
This gets iATU register area from reg property that has reg-names "atu". In Synopsys DWC version 4.80 or later, since iATU register area is separated from core register area, this area is necessary to get from DT independently. Suggested-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1601444167-11316-4-git-send-email-hayashi.kunihiko@socionext.com Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
2020-10-12Merge tag 'x86-irq-2020-10-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds3-9/+11
Pull x86 irq updates from Thomas Gleixner: "Surgery of the MSI interrupt handling to prepare the support of upcoming devices which require non-PCI based MSI handling: - Cleanup historical leftovers all over the place - Rework the code to utilize more core functionality - Wrap XEN PCI/MSI interrupts into an irqdomain to make irqdomain assignment to PCI devices possible. - Assign irqdomains to PCI devices at initialization time which allows to utilize the full functionality of hierarchical irqdomains. - Remove arch_.*_msi_irq() functions from X86 and utilize the irqdomain which is assigned to the device for interrupt management. - Make the arch_.*_msi_irq() support conditional on a config switch and let the last few users select it" * tag 'x86-irq-2020-10-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (40 commits) PCI: MSI: Fix Kconfig dependencies for PCI_MSI_ARCH_FALLBACKS x86/apic/msi: Unbreak DMAR and HPET MSI iommu/amd: Remove domain search for PCI/MSI iommu/vt-d: Remove domain search for PCI/MSI[X] x86/irq: Make most MSI ops XEN private x86/irq: Cleanup the arch_*_msi_irqs() leftovers PCI/MSI: Make arch_.*_msi_irq[s] fallbacks selectable x86/pci: Set default irq domain in pcibios_add_device() iommm/amd: Store irq domain in struct device iommm/vt-d: Store irq domain in struct device x86/xen: Wrap XEN MSI management into irqdomain irqdomain/msi: Allow to override msi_domain_alloc/free_irqs() x86/xen: Consolidate XEN-MSI init x86/xen: Rework MSI teardown x86/xen: Make xen_msi_init() static and rename it to xen_hvm_msi_init() PCI/MSI: Provide pci_dev_has_special_msi_domain() helper PCI_vmd_Mark_VMD_irqdomain_with_DOMAIN_BUS_VMD_MSI irqdomain/msi: Provide DOMAIN_BUS_VMD_MSI x86/irq: Initialize PCI/MSI domain at PCI init time x86/pci: Reducde #ifdeffery in PCI init code ...
2020-10-09PCI: iproc: Fix using plain integer as NULL pointer in iproc_pcie_pltfm_probeKrzysztof Wilczyński1-1/+1
Fix sparse build warning: drivers/pci/controller/pcie-iproc-platform.c:102:33: warning: Using plain integer as NULL pointer The map_irq member of the struct iproc_pcie takes a function pointer serving as a callback to map interrupts, therefore we should pass a NULL pointer to it rather than a integer in the iproc_pcie_pltfm_probe() function. Related: commit b64aa11eb2dd ("PCI: Set bridge map_irq and swizzle_irq to default functions") Link: https://lore.kernel.org/r/20200922194932.465925-1-kw@linux.com Signed-off-by: Krzysztof Wilczyński <kw@linux.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
2020-10-05PCI: meson: Build as module by defaultKevin Hilman2-2/+9
Enable pci-meson to build as a module whenever ARCH_MESON is enabled. Link: https://lore.kernel.org/r/20200918181251.32423-1-khilman@baylibre.com Signed-off-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Cc: Yue Wang <yue.wang@amlogic.com>
2020-10-05Merge 5.9-rc8 into usb-nextGreg Kroah-Hartman1-7/+4
We need the USB fixes in here as well for testing. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-10-02Merge tag 'pci-v5.9-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pciLinus Torvalds1-7/+4
Pull PCI fixes from Bjorn Helgaas: - Fix rockchip regression in rockchip_pcie_valid_device() (Lorenzo Pieralisi) - Add Pali Rohár as aardvark PCI maintainer (Pali Rohár) * tag 'pci-v5.9-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: MAINTAINERS: Add Pali Rohár as aardvark PCI maintainer PCI: rockchip: Fix bus checks in rockchip_pcie_valid_device()
2020-10-02PCI: aardvark: Fix initialization with old Marvell's Arm Trusted FirmwarePali Rohár1-1/+3
Old ATF automatically power on pcie phy and does not provide SMC call for phy power on functionality which leads to aardvark initialization failure: [ 0.330134] mvebu-a3700-comphy d0018300.phy: unsupported SMC call, try updating your firmware [ 0.338846] phy phy-d0018300.phy.1: phy poweron failed --> -95 [ 0.344753] advk-pcie d0070000.pcie: Failed to initialize PHY (-95) [ 0.351160] advk-pcie: probe of d0070000.pcie failed with error -95 This patch fixes above failure by ignoring 'not supported' error in aardvark driver. In this case it is expected that phy is already power on. Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com> Link: https://lore.kernel.org/r/20200902144344.16684-3-pali@kernel.org Fixes: 366697018c9a ("PCI: aardvark: Add PHY support") Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Cc: <stable@vger.kernel.org> # 5.8+: ea17a0f153af: phy: marvell: comphy: Convert internal SMCC firmware return codes to errno
2020-10-02PCI: xgene: Remove unused assignment to variable msi_valKrzysztof Wilczyński1-2/+2
The value assigned to msi_val after the inner loop finishes its run is never used for anything, and it is also immediately overridden in the line that follows with the return value from the xgene_msi_int_read() function. Since the value of msi_val following the inner loop completion is never used in any meaningful way the assignment can be removed. Addresses-Coverity-ID: 1437183 ("Unused value") Link: https://lore.kernel.org/r/20200922030257.459898-1-kw@linux.com Signed-off-by: Krzysztof Wilczyński <kw@linux.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
2020-10-02PCI: loongson: Simplify loongson_pci_probe() return expressionQinglang Miao1-6/+1
Simplify the return expression. Link: https://lore.kernel.org/r/20200921131054.92797-1-miaoqinglang@huawei.com Signed-off-by: Qinglang Miao <miaoqinglang@huawei.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
2020-10-02PCI: cadence: Simplify cdns_pcie_host_init_address_translation() return expressionQinglang Miao1-6/+2
Simplify the return expression. Link: https://lore.kernel.org/r/20200921131053.92752-1-miaoqinglang@huawei.com Signed-off-by: Qinglang Miao <miaoqinglang@huawei.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
2020-10-02PCI: mobiveil: Simplify mobiveil_pcie_init_irq_domain() return expressionLiu Shixin1-6/+1
Simplify the return expression by removing useless code. Link: https://lore.kernel.org/r/20200921082447.2591877-1-liushixin2@huawei.com Signed-off-by: Liu Shixin <liushixin2@huawei.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
2020-10-02PCI: iproc: Use module_bcma_driver to simplify the codeLiu Shixin1-12/+1
module_bcma_driver() makes the code simpler by eliminating boilerplate code. Link: https://lore.kernel.org/r/20200918030829.3946025-1-liushixin2@huawei.com Signed-off-by: Liu Shixin <liushixin2@huawei.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Ray Jui <ray.jui@broadcom.com>
2020-10-02PCI: brcmstb: Add bcm7211, bcm7216, bcm7445, bcm7278 to match listJim Quinlan1-0/+4
Now that the support is in place with previous commits, we add several chips that use the BrcmSTB driver. Link: https://lore.kernel.org/r/20200911175232.19016-11-james.quinlan@broadcom.com Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Rob Herring <robh@kernel.org>
2020-10-02PCI: brcmstb: Set bus max burst size by chip typeJim Quinlan1-4/+15
The proper value of the parameter SCB_MAX_BURST_SIZE varies per chip. The 2711 family requires 128B whereas other devices can employ 512. The assignment is complicated by the fact that the values for this two-bit field have different meanings; Value Type_Generic Type_7278 00 Reserved 128B 01 128B 256B 10 256B 512B 11 512B Reserved Link: https://lore.kernel.org/r/20200911175232.19016-10-james.quinlan@broadcom.com Signed-off-by: Jim Quinlan <jquinlan@broadcom.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Florian Fainelli <f.fainelli@gmail.com>
2020-10-02PCI: brcmstb: Accommodate MSI for older chipsJim Quinlan1-21/+49
Older BrcmSTB chips do not have a separate register for MSI interrupts; the MSIs are in a register that also contains unrelated interrupts. In addition, the interrupts lie in bits [31..24] for these legacy chips. This commit provides common code for both legacy and non-legacy MSI interrupt registers. Link: https://lore.kernel.org/r/20200911175232.19016-9-james.quinlan@broadcom.com Signed-off-by: Jim Quinlan <jquinlan@broadcom.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Florian Fainelli <f.fainelli@gmail.com>
2020-10-02PCI: brcmstb: Set additional internal memory DMA viewport sizesJim Quinlan1-18/+49
The Raspberry Pi (RPI) is currently the only chip using this driver (pcie-brcmstb.c). There, only one memory controller is used, without an extension region, and the SCB0 viewport size is set to the size of the first and only dma-range region. Other BrcmSTB SOCs have more complicated memory configurations that require setting additional viewport sizes. BrcmSTB PCIe controllers are intimately connected to the memory controller(s) on the SOC. The SOC may have one to three memory controllers; they are indicated by the term SCBi. Each controller has a base region and an optional extension region. In physical memory, the base and extension regions of a controller are not adjacent, but in PCIe-space they are. There is a "viewport" for each memory controller that allows DMA from endpoint devices. Each viewport's size must be set to a power of two, and that size must be equal to or larger than the amount of memory each controller supports which is the sum of base region and its optional extension. Further, the 1-3 viewports are also adjacent in PCIe-space. Unfortunately the viewport sizes cannot be ascertained from the "dma-ranges" property so they have their own property, "brcm,scb-sizes". This is because dma-range information does not indicate what memory controller it is associated. For example, consider the following case where the size of one dma-range is 2GB and the second dma-range is 1GB: /* Case 1: SCB0 size set to 4GB */ dma-range0: 2GB (from memc0-base) dma-range1: 1GB (from memc0-extension) /* Case 2: SCB0 size set to 2GB, SCB1 size set to 1GB */ dma-range0: 2GB (from memc0-base) dma-range1: 1GB (from memc0-extension) By just looking at the dma-ranges information, one cannot tell which situation applies. That is why an additional property is needed. Its length indicates the number of memory controllers being used and each value indicates the viewport size. Note that the RPI DT does not have a "brcm,scb-sizes" property value, as it is assumed that it only requires one memory controller and no extension. So the optional use of "brcm,scb-sizes" will be backwards compatible. One last layer of complexity exists: all of the viewports sizes must be added and rounded up to a power of two to determine what the "BAR" size is. Further, an offset must be given that indicates the base PCIe address of this "BAR". The use of the term BAR is typically associated with endpoint devices, and the term is used here because the PCIe HW may be used as an RC or an EP. In the former case, all of the system memory appears in a single "BAR" region in PCIe memory. As it turns out, BrcmSTB PCIe HW is rarely used in the EP role and its system of mapping memory is an artifact that requires multiple dma-ranges regions. Link: https://lore.kernel.org/r/20200911175232.19016-8-james.quinlan@broadcom.com Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Florian Fainelli <f.fainelli@gmail.com>
2020-10-02PCI: brcmstb: Add control of rescal resetJim Quinlan1-2/+77
Some STB chips have a special purpose reset controller named RESCAL (reset calibration). The PCIe HW can now control RESCAL to start and stop its operation. On probe(), the RESCAL is deasserted and the driver goes through the sequence of setting registers and reading status in order to start the internal PHY that is required for the PCIe. Link: https://lore.kernel.org/r/20200911175232.19016-7-james.quinlan@broadcom.com Signed-off-by: Jim Quinlan <jquinlan@broadcom.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Florian Fainelli <f.fainelli@gmail.com>
2020-10-02PCI: hv: Fix hibernation in case interrupts are not re-createdDexuan Cui1-3/+47
pci_restore_msi_state() directly writes the MSI/MSI-X related registers via MMIO. On a physical machine, this works perfectly; for a Linux VM running on a hypervisor, which typically enables IOMMU interrupt remapping, the hypervisor usually should trap and emulate the MMIO accesses in order to re-create the necessary interrupt remapping table entries in the IOMMU, otherwise the interrupts can not work in the VM after hibernation. Hyper-V is different from other hypervisors in that it does not trap and emulate the MMIO accesses, and instead it uses a para-virtualized method, which requires the VM to call hv_compose_msi_msg() to notify the hypervisor of the info that would be passed to the hypervisor in the case of the trap-and-emulate method. This is not an issue to a lot of PCI device drivers, which destroy and re-create the interrupts across hibernation, so hv_compose_msi_msg() is called automatically. However, some PCI device drivers (e.g. the in-tree GPU driver nouveau and the out-of-tree Nvidia proprietary GPU driver) do not destroy and re-create MSI/MSI-X interrupts across hibernation, so hv_pci_resume() has to call hv_compose_msi_msg(), otherwise the PCI device drivers can no longer receive interrupts after the VM resumes from hibernation. Hyper-V is also different in that chip->irq_unmask() may fail in a Linux VM running on Hyper-V (on a physical machine, chip->irq_unmask() can not fail because unmasking an MSI/MSI-X register just means an MMIO write): during hibernation, when a CPU is offlined, the kernel tries to move the interrupt to the remaining CPUs that haven't been offlined yet. In this case, hv_irq_unmask() -> hv_do_hypercall() always fails because the vmbus channel has been closed: here the early "return" in hv_irq_unmask() means the pci_msi_unmask_irq() is not called, i.e. the desc->masked remains "true", so later after hibernation, the MSI interrupt always remains masked, which is incorrect. Refer to cpu_disable_common() -> fixup_irqs() -> irq_migrate_all_off_this_cpu() -> migrate_one_irq(): static bool migrate_one_irq(struct irq_desc *desc) { ... if (maskchip && chip->irq_mask) chip->irq_mask(d); ... err = irq_do_set_affinity(d, affinity, false); ... if (maskchip && chip->irq_unmask) chip->irq_unmask(d); Fix the issue by calling pci_msi_unmask_irq() unconditionally in hv_irq_unmask(). Also suppress the error message for hibernation because the hypercall failure during hibernation does not matter (at this time all the devices have been frozen). Note: the correct affinity info is still updated into the irqdata data structure in migrate_one_irq() -> irq_do_set_affinity() -> hv_set_affinity(), so later when the VM resumes, hv_pci_restore_msi_state() is able to correctly restore the interrupt with the correct affinity. Link: https://lore.kernel.org/r/20201002085158.9168-1-decui@microsoft.com Fixes: ac82fc832708 ("PCI: hv: Add hibernation support") Signed-off-by: Dexuan Cui <decui@microsoft.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Jake Oshins <jakeo@microsoft.com>