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Suspending Goodix touchscreens requires changing the interrupt pin to
output before sending them a power-down command. Followed by wiggling
the interrupt pin to wake the device up, after which it is put back
in input mode.
On Cherry Trail device the interrupt pin is listed as a GpioInt ACPI
resource so we can do this without problems as long as we release the
IRQ before changing the pin to output mode.
On Bay Trail devices with a Goodix touchscreen direct-irq mode is used
in combination with listing the pin as a normal GpioIo resource. This
works fine, but this triggers the WARN in byt_gpio_set_direction-s output
path because direct-irq support is enabled on the pin.
This commit replaces the WARN call with a dev_info_once call, fixing a
bunch of WARN splats in dmesg on each suspend/resume cycle.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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Suspending Goodix touchscreens requires changing the interrupt pin to
output before sending them a power-down command. Followed by wiggling
the interrupt pin to wake the device up, after which it is put back
in input mode.
On Bay Trail devices with a Goodix touchscreen direct-irq mode is used
in combination with listing the pin as a normal GpioIo resource.
This works fine, until the goodix driver gets rmmod-ed and then insmod-ed
again. In this case byt_gpio_disable_free() calls
byt_gpio_clear_triggering() which clears the IRQ flags and after that the
(direct) IRQ no longer triggers.
This commit fixes this by adding a check for the BYT_DIRECT_IRQ_EN flag
to byt_gpio_clear_triggering().
Note that byt_gpio_clear_triggering() only gets called from
byt_gpio_disable_free() for direct-irq enabled pins, as these are excluded
from the irq_valid mask by byt_init_irq_valid_mask().
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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pinctrl: sh-pfc: Updates for v5.5
- Split R-Car H3 support in two independent drivers,
- Miscellaneous fixes and cleanups.
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Commit 179e5a6114cc ("pinctrl: intel: Remove default Interrupt Status
offset") removes default interrupt status offset of GPIO controllers,
with previous commits explicitly providing the previously default
offsets. However, the is_offset value in SPTH_COMMUNITY is missing,
preventing related irq from being properly detected and handled.
Fixes: f702e0b93cdb ("pinctrl: sunrisepoint: Provide Interrupt Status register offset")
Link: https://bugzilla.kernel.org/show_bug.cgi?id=205745
Cc: stable@vger.kernel.org
Signed-off-by: Boyan Ding <boyan.j.ding@gmail.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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Despite using the same compatible values ("r8a7795"-based) because of
historical reasons, R-Car H3 ES1.x (R8A77950) and R-Car H3 ES2.0+
(R8A77951) are really different SoCs, with different part numbers, and
with different Pin Function Controller blocks.
Reflect this in the pinctrl configuration, by replacing the existing
CONFIG_PINCTRL_PFC_R8A7795 symbol by two new config symbols:
CONFIG_PINCTRL_PFC_R8A77950 and CONFIG_PINCTRL_PFC_R8A77951. The latter
are selected automatically, depending on the soon-to-be-introduced
corresponding SoC-specific config options, and on the current common
config option, to relax dependencies.
Rename the individual pin control driver source files from
pfc-r8a7795-es1.c to pfc-r8a77950.c, and from pfc-r8a7795.c to
pfc-r8a77951.c, and make them truly independent.
As both SoCs share the same compatible value, special care must be taken
to match them to the correct pin control driver, if support for it is
included in the running kernel.
This will allow making support for early R-Car H3 revisions optional,
the largest share of which is taken by the pin control driver.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20191230083156.19191-1-geert+renesas@glider.be
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The artpec6_pconf_set should have marked reg as __iomem,
which ends up making sparse complain about address
space conversions. Add the __iomem to silence the
following warnings:
drivers/pinctrl/pinctrl-artpec6.c:814:13: warning: incorrect type in assignment (different address spaces)
drivers/pinctrl/pinctrl-artpec6.c:814:13: expected unsigned int *reg
drivers/pinctrl/pinctrl-artpec6.c:814:13: got void [noderef] <asn:2> *
drivers/pinctrl/pinctrl-artpec6.c:825:34: warning: incorrect type in argument 1 (different address spaces)
drivers/pinctrl/pinctrl-artpec6.c:825:34: expected void const volatile [noderef] <asn:2> *addr
drivers/pinctrl/pinctrl-artpec6.c:825:34: got unsigned int *reg
drivers/pinctrl/pinctrl-artpec6.c:827:25: warning: incorrect type in argument 2 (different address spaces)
drivers/pinctrl/pinctrl-artpec6.c:827:25: expected void volatile [noderef] <asn:2> *addr
drivers/pinctrl/pinctrl-artpec6.c:827:25: got unsigned int *reg
drivers/pinctrl/pinctrl-artpec6.c:837:34: warning: incorrect type in argument 1 (different address spaces)
drivers/pinctrl/pinctrl-artpec6.c:837:34: expected void const volatile [noderef] <asn:2> *addr
drivers/pinctrl/pinctrl-artpec6.c:837:34: got unsigned int *reg
drivers/pinctrl/pinctrl-artpec6.c:840:25: warning: incorrect type in argument 2 (different address spaces)
drivers/pinctrl/pinctrl-artpec6.c:840:25: expected void volatile [noderef] <asn:2> *addr
drivers/pinctrl/pinctrl-artpec6.c:840:25: got unsigned int *reg
drivers/pinctrl/pinctrl-artpec6.c:850:34: warning: incorrect type in argument 1 (different address spaces)
drivers/pinctrl/pinctrl-artpec6.c:850:34: expected void const volatile [noderef] <asn:2> *addr
drivers/pinctrl/pinctrl-artpec6.c:850:34: got unsigned int *reg
drivers/pinctrl/pinctrl-artpec6.c:853:25: warning: incorrect type in argument 2 (different address spaces)
drivers/pinctrl/pinctrl-artpec6.c:853:25: expected void volatile [noderef] <asn:2> *addr
drivers/pinctrl/pinctrl-artpec6.c:853:25: got unsigned int *reg
drivers/pinctrl/pinctrl-artpec6.c:864:34: warning: incorrect type in argument 1 (different address spaces)
drivers/pinctrl/pinctrl-artpec6.c:864:34: expected void const volatile [noderef] <asn:2> *addr
drivers/pinctrl/pinctrl-artpec6.c:864:34: got unsigned int *reg
drivers/pinctrl/pinctrl-artpec6.c:867:25: warning: incorrect type in argument 2 (different address spaces)
drivers/pinctrl/pinctrl-artpec6.c:867:25: expected void volatile [noderef] <asn:2> *addr
drivers/pinctrl/pinctrl-artpec6.c:867:25: got unsigned int *reg
Signed-off-by: Ben Dooks (Codethink) <ben.dooks@codethink.co.uk>
Link: https://lore.kernel.org/r/20191218101602.2442868-1-ben.dooks@codethink.co.uk
[Changed unsigned int -> void for the reg pointer]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Use devm_platform_ioremap_resource() instead of platform_get_resource +
devm_ioremap_resource.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20200106232711.559727-6-paul@crapouillou.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Simplify the code of the driver's irq_set_type() function by doing some
factorization. The behaviour is unchanged.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20200106232711.559727-5-paul@crapouillou.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Until there is the need to handle the JZ4760B and X1000E differently
there is no reason to use a separate ingenic_chip_info since the data
it contains is the same than for the JZ4760 and X1000 respectively.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20200106232711.559727-4-paul@crapouillou.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Instead of passing a numeric ID as match data, and retrieve a pointer to
the ingenic_chip_info structure in an ugly succession of if/else in the
probe function, get the pointer to the ingenic_chip_info structure
directly from the match data, and store the numeric ID inside the
ingenic_chip_info structure.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20200106232711.559727-3-paul@crapouillou.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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We enforce devicetree support in the Kconfig and all Ingenic boards
without exception probe their drivers from devicetree. The code path to
probe the driver from arch code can then be considered as dead code and
removed.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20200106232711.559727-2-paul@crapouillou.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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GPIOH_5 and GPIOH_6 can have two Ethernet related functions:
- GPIOH_5 can be ETH_TXD1 or ETH_RXD3
- GPIOH_6 can be ETH_TXD0 or ETH_RXD2
Add the bits for eth_rxd3_h and eth_rxd2_h so the ETH_RXD function can
be disabled when using the ETH_TXD function of GPIOH_{5,6}. No problem
was observed so far, but in theory this could lead to two different
signals being routed to the same pad (which could break Ethernet).
These settings were found in the public "Amlogic Ethernet controller
user guide":
http://openlinux.amlogic.com/@api/deki/files/75/=Amlogic_Ethenet_controller_user_Guide.pdf
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20191226191425.3797490-1-martin.blumenstingl@googlemail.com
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The npcmgpio_irqchip structure is only copied into another
structure, so make it const.
The opportunity for this change was found using Coccinelle.
Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
Link: https://lore.kernel.org/r/1577864614-5543-17-git-send-email-Julia.Lawall@inria.fr
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The pm8xxx_pinctrl_desc structure is only copied into another
structure, so make it const.
The opportunity for this change was found using Coccinelle.
Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
Link: https://lore.kernel.org/r/1577864614-5543-15-git-send-email-Julia.Lawall@inria.fr
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The pm8xxx_pinctrl_desc structure is only copied into another structure,
so make it const.
The opportunity for this change was found using Coccinelle.
Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
Link: https://lore.kernel.org/r/1577864614-5543-9-git-send-email-Julia.Lawall@inria.fr
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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In meson_pinconf_get_drive_strength, variable bit is calculated by
meson_calc_reg_and_bit, this value is the offset from the first pin of a
certain bank to current pin, while Meson SoCs use two bits for each pin
to depict drive-strength. So a left shift by 1 should be done or node
pinconf-pins shows wrong message.
Fixes: 6ea3e3bbef37 ("pinctrl: meson: add support of drive-strength-microamp")
Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
Link: https://lore.kernel.org/r/20191226023734.9631-1-qianggui.song@amlogic.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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In a rare randconfig build I came across one configuration that does
not enable CONFIG_GPIOLIB, which is needed by lochnagar:
ERROR: "devm_gpiochip_add_data" [drivers/pinctrl/cirrus/pinctrl-lochnagar.ko] undefined!
ERROR: "gpiochip_generic_free" [drivers/pinctrl/cirrus/pinctrl-lochnagar.ko] undefined!
ERROR: "gpiochip_generic_request" [drivers/pinctrl/cirrus/pinctrl-lochnagar.ko] undefined!
ERROR: "gpiochip_get_data" [drivers/pinctrl/cirrus/pinctrl-lochnagar.ko] undefined!
Add another 'select' like all other pinctrl drivers have.
Fixes: 0548448b719a ("pinctrl: lochnagar: Add support for the Cirrus Logic Lochnagar")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20191218163701.171914-1-arnd@arndb.de
Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Fixes coccicheck warning:
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c:736:2-3: Unneeded semicolon
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c:803:2-3: Unneeded semicolon
Fixes: commit 5715092a458c ("pinctrl: armada-37xx: Add gpio support")
commit 2f227605394b ("pinctrl: armada-37xx: Add irqchip support")
Signed-off-by: Ma Feng <mafeng.ma@huawei.com>
Link: https://lore.kernel.org/r/1576723865-111331-1-git-send-email-mafeng.ma@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The m_voc_groups is not declared outside of the
driver, so make it static to avoid the following
sparse wanrning:
drivers/pinctrl/qcom/pinctrl-msm8976.c:592:12: warning: symbol 'm_voc_groups' was not declared. Should it be static?
Signed-off-by: Ben Dooks (Codethink) <ben.dooks@codethink.co.uk>
Link: https://lore.kernel.org/r/20191218102804.2487374-1-ben.dooks@codethink.co.uk
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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platform_irq_count() is the more generic way (independent of
device trees) to determine the count of available interrupts. So
use this instead.
As platform_irq_count() might return an error code (which
of_irq_count doesn't) some additional handling is necessary.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/1576672860-14420-2-git-send-email-peng.fan@nxp.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The dsi entry is defined identically twice, so remove
the second one to remove the sparse warning:
drivers/pinctrl/actions/pinctrl-s700.c:1581:10: warning: Initializer entry defined twice
drivers/pinctrl/actions/pinctrl-s700.c:1586:10: also defined here
Signed-off-by: Ben Dooks (Codethink) <ben.dooks@codethink.co.uk>
Link: https://lore.kernel.org/r/20191218102013.2465038-1-ben.dooks@codethink.co.uk
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The functions should have __iomem on the register pointer
so add that to silence the following sparse warnings:
drivers/pinctrl/tegra/pinctrl-tegra.c:657:22: warning: incorrect type in assignment (different address spaces)
drivers/pinctrl/tegra/pinctrl-tegra.c:657:22: expected unsigned int [usertype] *regs
drivers/pinctrl/tegra/pinctrl-tegra.c:657:22: got void [noderef] <asn:2> *
drivers/pinctrl/tegra/pinctrl-tegra.c:659:42: warning: incorrect type in argument 1 (different address spaces)
drivers/pinctrl/tegra/pinctrl-tegra.c:659:42: expected void const volatile [noderef] <asn:2> *addr
drivers/pinctrl/tegra/pinctrl-tegra.c:659:42: got unsigned int [usertype] *
drivers/pinctrl/tegra/pinctrl-tegra.c:675:22: warning: incorrect type in assignment (different address spaces)
drivers/pinctrl/tegra/pinctrl-tegra.c:675:22: expected unsigned int [usertype] *regs
drivers/pinctrl/tegra/pinctrl-tegra.c:675:22: got void [noderef] <asn:2> *
drivers/pinctrl/tegra/pinctrl-tegra.c:677:25: warning: incorrect type in argument 2 (different address spaces)
drivers/pinctrl/tegra/pinctrl-tegra.c:677:25: expected void volatile [noderef] <asn:2> *addr
drivers/pinctrl/tegra/pinctrl-tegra.c:677:25: got unsigned int [usertype] *
Signed-off-by: Ben Dooks (Codethink) <ben.dooks@codethink.co.uk>
Link: https://lore.kernel.org/r/20191218110456.2533088-1-ben.dooks@codethink.co.uk
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Add support for probing the pinctrl-ingenic driver on the
X1830 Soc from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Link: https://lore.kernel.org/r/1576426864-35348-7-git-send-email-zhouyanjie@wanyeetech.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Introduce "reg_offset", use it instead hard code "0x100",
it will also be used for subsequent X1830 pinctrl driver.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Link: https://lore.kernel.org/r/1576426864-35348-5-git-send-email-zhouyanjie@wanyeetech.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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1.Add pinctrl drivers for the SPI flash controller (SFC) of
X1000 and X1500.
2.Add pinctrl driver for the synchronous serial interface (SSI)
of X1000.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Link: https://lore.kernel.org/r/1576426864-35348-4-git-send-email-zhouyanjie@wanyeetech.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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1.Fix the pullup parameter of X1000.
2.X1000 and X1500 have only one set of uart1 hwflow pin mapping,
so modify "uart1_hwflow_d" to "uart1_hwflow".
3.X1000 has only one set of mmc1 pin mapping, so modify
"mmc1-1bit-e/mmc1-4bit-e" to "mmc1-1bit/mmc1-4bit".
4.X1000 has only one regular externel memory controller that
does not support nand flash, so change "nemc_" to "emc_".
5.X1500 has only one set of mmc, so modify "mmc0_" to "mmc_".
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Link: https://lore.kernel.org/r/1576426864-35348-3-git-send-email-zhouyanjie@wanyeetech.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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ioremap has provided non-cached semantics by default since the Linux 2.6
days, so remove the additional ioremap_nocache interface.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
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pinmux_func_gpios[] contains a hole due to the missing function GPIO
definition for the "CTX0&CTX1" signal, which is the logical "AND" of the
first two CAN outputs.
A closer look reveals other issues:
- Some functionality is available on alternative pins, but the
PINMUX_DATA() entries is using the wrong marks,
- Several configurations are missing.
Fix this by:
- Renaming CTX0CTX1CTX2_MARK, CRX0CRX1_PJ22_MARK, and
CRX0CRX1CRX2_PJ20_MARK to CTX0_CTX1_CTX2_MARK, CRX0_CRX1_PJ22_MARK,
resp. CRX0_CRX1_CRX2_PJ20_MARK for consistency with the
corresponding enum IDs,
- Adding all missing enum IDs and marks,
- Use the right (*_PJ2x) variants for alternative pins,
- Adding all missing configurations to pinmux_data[],
- Adding all missing function GPIO definitions to pinmux_func_gpios[].
See SH7268 Group, SH7269 Group User’s Manual: Hardware, Rev. 2.00:
[1] Table 1.4 List of Pins
[2] Figure 23.29 Connection Example when Using Channels 0 and 1 as One
Channel (64 Mailboxes × 1 Channel) and Channel 2 as One Channel
(32 Mailboxes × 1 Channel),
[3] Figure 23.30 Connection Example when Using Channels 0, 1, and 2 as
One Channel (96 Mailboxes × 1 Channel),
[4] Table 48.3 Multiplexed Pins (Port B),
[5] Table 48.4 Multiplexed Pins (Port C),
[6] Table 48.10 Multiplexed Pins (Port J),
[7] Section 48.2.4 Port B Control Registers 0 to 5 (PBCR0 to PBCR5).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20191218194812.12741-5-geert+renesas@glider.be
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pinmux_func_gpios[] contains a hole due to the missing function GPIO
definition for the "CTX0&CTX1" signal, which is the logical "AND" of the
two CAN outputs.
Fix this by:
- Renaming CRX0_CRX1_MARK to CTX0_CTX1_MARK, as PJ2MD[2:0]=010
configures the combined "CTX0&CTX1" output signal,
- Renaming CRX0X1_MARK to CRX0_CRX1_MARK, as PJ3MD[1:0]=10 configures
the shared "CRX0/CRX1" input signal, which is fed to both CAN
inputs,
- Adding the missing function GPIO definition for "CTX0&CTX1" to
pinmux_func_gpios[],
- Moving all CAN enums next to each other.
See SH7262 Group, SH7264 Group User's Manual: Hardware, Rev. 4.00:
[1] Figure 1.2 (3) (Pin Assignment for the SH7264 Group (1-Mbyte
Version),
[2] Figure 1.2 (4) Pin Assignment for the SH7264 Group (640-Kbyte
Version,
[3] Table 1.4 List of Pins,
[4] Figure 20.29 Connection Example when Using This Module as 1-Channel
Module (64 Mailboxes x 1 Channel),
[5] Table 32.10 Multiplexed Pins (Port J),
[6] Section 32.2.30 (3) Port J Control Register 0 (PJCR0).
Note that the last 2 disagree about PJ2MD[2:0], which is probably the
root cause of this bug. But considering [4], "CTx0&CTx1" in [5] must
be correct, and "CRx0&CRx1" in [6] must be wrong.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20191218194812.12741-4-geert+renesas@glider.be
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The register definition block for the Port K I/O Register is
accidentally using the defines for Port J. Replace them by the proper
Port K defines.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20191218194812.12741-3-geert+renesas@glider.be
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The FN_SDSELF_B and FN_SD1_CLK_B enum IDs are used twice, which means
one set of users must be wrong. Replace them by the correct enum IDs.
Fixes: 87f8c988636db0d4 ("sh-pfc: Add r8a7778 pinmux support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20191218194812.12741-2-geert+renesas@glider.be
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Currently only the drivers/pinctrl/devicetree.c code allows registering
pinctrl-mappings which may later be unregistered, all other mappings
are assumed to be permanent.
Non-dt platforms may also want to register pinctrl mappings from code which
is build as a module, which requires being able to unregister the mapping
when the module is unloaded to avoid dangling pointers.
To allow unregistering the mappings the devicetree code uses 2 internal
functions: pinctrl_register_map and pinctrl_unregister_map.
pinctrl_register_map allows the devicetree code to tell the core to
not memdup the mappings as it retains ownership of them and
pinctrl_unregister_map does the unregistering, note this only works
when the mappings where not memdupped.
The only code relying on the memdup/shallow-copy done by
pinctrl_register_mappings is arch/arm/mach-u300/core.c this commit
replaces the __initdata with const, so that the shallow-copy is no
longer necessary.
After that we can get rid of the internal pinctrl_unregister_map function
and just use pinctrl_register_mappings directly everywhere.
This commit also renames pinctrl_unregister_map to
pinctrl_unregister_mappings so that its naming matches its
pinctrl_register_mappings counter-part and exports it.
Together these 2 changes will allow non-dt platform code to
register pinctrl-mappings from modules without breaking things on
module unload (as they can now unregister the mapping on unload).
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Link: https://lore.kernel.org/r/20191216205122.1850923-2-hdegoede@redhat.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Linux 5.5-rc3
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Since this message is printed for each port, it creates a lot of output
during boot and would serve better only during debugging.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Acked-by: Jacopo Mondi <jacopo@jmondi.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20191212135301.17915-1-chris.brandt@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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R-Car Gen3 Hardware Manual Errata for Rev. 2.00 of October 24, 2019
changed the configuration bits for drive and bias control for the
DU_DOTCLKIN3 pin on R-Car M3-N, to match the same pin on R-Car H3.
Update the driver to reflect this.
After this, the handling of drive and bias control for the various
DU_DOTCLKINx pins is consistent across all of the R-Car H3, M3-W,
M3-W+, and M3-N SoCs.
Fixes: 86c045c2e4201e94 ("pinctrl: sh-pfc: r8a77965: Replace DU_DOTCLKIN2 by DU_DOTCLKIN3")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20191113101653.28428-1-geert+renesas@glider.be
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JZ4760 support was added in parallel of the previous patch so this one
slipped through. The first SoC to use the new register is the JZ4760 and
not the JZ4770, fix it here.
Fixes: 7009d046a601 ("pinctrl: ingenic: Handle PIN_CONFIG_OUTPUT config")
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20191210164446.53912-1-paul@crapouillou.net
[Folded into OF dependency]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Rather than always using handle_simple_irq() as the gpio_irq_chip
handler, set a more appropriate handler based on the IRQ trigger type
requested.
This is important for level triggered interrupts which need to be
masked during handling.
Signed-off-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz>
Link: https://lore.kernel.org/r/20191215210503.15488-2-hamish.martin@alliedtelesis.co.nz
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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on sc7180 we have cases where multiple functions from the same
qup instance share the same pin. This is true for qup02/04/11 and qup13.
Add new function names to distinguish which qup function to use.
The device tree files for this platform haven't landed in mainline yet,
so there aren't any users upstream who should break with this change
in function names, however, anyone using the devicetree files that were
posted on the lists and using these specific function names will need
to update their changes.
Reported-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Link: https://lore.kernel.org/r/0101016ef36a9118-f2919277-effa-4cd5-adf8-bbc8016f31df-000000@us-west-2.amazonses.com
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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GPIOs that can be configured as wakeup sources, have their
interrupt lines routed to PDC interrupt controller.
Provide the interrupt map of the GPIO to its wakeup capable
interrupt parent.
Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
Link: https://lore.kernel.org/r/1572419178-5750-2-git-send-email-mkshah@codeaurora.org
Reviewed-by: Lina Iyer <ilina@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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All Samsung pinctrl drivers select common part - PINCTRL_SAMSUNG which uses
both OF and GPIOLIB inside. However only Exynos drivers depend on these,
therefore after enabling COMPILE_TEST, on x86_64 build of S3C64xx driver
failed:
drivers/pinctrl/samsung/pinctrl-samsung.c: In function ‘samsung_gpiolib_register’:
drivers/pinctrl/samsung/pinctrl-samsung.c:969:5: error: ‘struct gpio_chip’ has no member named ‘of_node’
gc->of_node = bank->of_node;
^
Rework the dependencies so all Samsung drivers and common
PINCTRL_SAMSUNG part depend on OF_GPIO (which is default yes if GPIOLIB
and OF are enabled).
Reported-by: Chen Zhou <chenzhou10@huawei.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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Reflect in the driver that it is now a pin control one.
While here, update copyright years and authors.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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When all preparations are done, we may switch to pin control API.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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When IRQ chip is instantiated via GPIO library flow, the few functions,
in particular the ACPI event registration mechanism, on some of ACPI based
platforms expect that the pin ranges are initialized to that point.
Add GPIO <-> pin mapping ranges via callback in the GPIO library flow.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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The introduced callback ->pin_dbg_show() is useful for debugging.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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Add implementation for:
- pin control, group information retrieval: count, name and pins
- pin muxing:
- function information (count, name and groups)
- mux setting
- GPIO control (enable, disable, set direction)
- pin configuration:
- pull disable, up and down
- any other option is treated as not supported.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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We may use now available struct intel_pinctrl in the driver.
No functional change implied.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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In order to implement pin control for Intel Lynxpoint, we need
data structures in which to store and pass along pin, community
and SoC data information.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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Allows querying GPIO direction from the pad config register.
If the pad is not in GPIO mode, return an error.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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Hans de Goede
Linus Walleij
Boyan Ding
Geert Uytterhoeven
Ben Dooks (Codethink)
Paul Cercueil
Martin Blumenstingl
Julia Lawall
Qianggui Song
Arnd Bergmann
Ma Feng
Peng Fan
周琰杰 (Zhou Yanjie)
Christoph Hellwig
Chris Brandt
Hamish Martin
Rajendra Nayak
Maulik Shah
Krzysztof Kozlowski
Andy Shevchenko