Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2016-05-11 | irqchip/gic-v3: Configure all interrupts as non-secure Group-1 | 1 | -0/+12 | |
2016-05-11 | irqchip/gic-v2m: Add workaround for Broadcom NS2 GICv2m erratum | 1 | -2/+17 | |
2016-05-11 | irqchip/irq-alpine-msi: Don't use <asm-generic/msi.h> | 1 | -1/+1 | |
2016-05-11 | irqchip/mbigen: Checking for IS_ERR() instead of NULL | 1 | -2/+2 | |
2016-05-11 | irqchip/gic-v3: Remove inexistant register definition | 1 | -2/+0 | |
2016-05-11 | irqchip/gicv3-its: Don't allow devices whose ID is outside range | 1 | -4/+38 | |
2016-05-11 | irqchip: Add LPC32xx interrupt controller driver | 4 | -1/+241 | |
2016-05-11 | irqchip/gic: Ensure ordering between read of INTACK and shared data | 2 | -0/+15 | |
2016-05-04 | irqchip: Add Layerscape SCFG MSI controller support | 3 | -0/+246 |