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2017-08-18drm/amdgpu: fix vega10 graphic hang issue in S3 testKen Wang2-2/+9
mmVGT_INDEX_TYPE has no default value, need to make sure it's initialized when gfx is initialized. Signed-off-by: Ken Wang <Ken.Wang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-18drm: udl: constify usb_device_idArvind Yadav1-1/+1
usb_device_id are not supposed to change at runtime. All functions working with usb_device_id provided by <linux/usb.h> work with const usb_device_id. So mark the non-const structs as const. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/22fa8ca67a6d4a59997f463bf241ed56596fbcfa.1502526524.git.arvind.yadav.cs@gmail.com
2017-08-18drm/gma500: fix potential NULL pointer dereference dereferenceGustavo A. R. Silva1-1/+3
NULL check at line 528: if (!sender || !data_out || !len_out) {, implies that pointer _sender_ might be NULL. Move pointer _sender_ dereference after NULL check in order to avoid a potential NULL pointer dereference. This issue was detected with the help of Coccinelle. Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20170812015515.GA8360@embeddedgus
2017-08-17drm/amdgpu: bump version for support of UVD MJPEG decodeLeo Liu1-1/+2
Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-17drm/amdgpu: add MJPEG check for UVD physical mode msg bufferLeo Liu1-0/+4
Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-17drm/ttm: Fix accounting error when fail to get pages for poolXiangliang.Yu1-1/+1
When fail to get needed page for pool, need to put allocated pages into pool. But current code has a miscalculation of allocated pages, correct it. Signed-off-by: Xiangliang.Yu <Xiangliang.Yu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2017-08-17drm/amd/amdgpu: expose fragment size as module parameter (v2)Roger He9-16/+44
Allow overrides on the command line. v2: agd: sqaush in spelling fix and bogus default value warning Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Roger He <Hongbo.He@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-17drm/amd/amdgpu: store fragment_size in vm_managerRoger He9-26/+33
adds fragment_size in the vm_manager structure and implements hardware setup for it. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Roger He <Hongbo.He@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-17drm/amdgpu: rename VM invalidated to movedChristian König3-12/+12
That better describes what happens here with the BO. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-17drm/amdgpu: separate bo_va structureChristian König7-55/+66
Split that into vm_bo_base and bo_va to allow other uses as well. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-17drm/amdgpu: drop the extra VM huge page flag v2Christian König2-10/+9
Just add the flags to the addr field as well. v2: add some more comments that the flag is for huge pages. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-17drm/amdgpu: remove superflous amdgpu_bo_kmap in the VMChristian König1-19/+9
We now properly kmap all BOs after validation. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-17drm/amdgpu: cleanup static CSA handlingChristian König6-20/+20
Move the CSA bo_va from the VM to the fpriv structure. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-17drm/amdgpu: SHADOW and VRAM_CONTIGUOUS flags shouldn't be used by userspaceChristian König1-3/+1
The shadow handling isn't implemented completely for userspace BOs and the kernel sets the VRAM_CONTIGUOUS as necessary. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-17drm/amdgpu: save list length when fence is signaledChunming Zhou1-7/+6
update the list first to avoid redundant checks. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2017-08-17drm/amdgpu: move vram usage tracking into the vram manager v2Christian König6-62/+79
Looks like a better place for this. v2: use atomic64_t members instead Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-17drm/amdgpu: move gtt usage tracking into the gtt manager v2Christian König5-16/+26
It doesn't make much sense to count those numbers twice. v2: use and atomic64_t instead Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-17drm/amdgpu: move debug print into the MM managersChristian König3-22/+11
Instead of the separate switch/case in the calling function. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-17drm/amdgpu: fix incorrect use of the lru_lockChristian König1-5/+2
The BO manager has its own lock and doesn't use the lru_lock. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-17drm/radeon: fix incorrect use of the lru_lockChristian König1-6/+4
The BO manager has its own lock and doesn't use the lru_lock. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-17drm/ttm: make ttm_mem_type_manager_func debug more usefulChristian König8-19/+20
Provide the drm printer directly instead of just the callback. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-17drm/amd/amdgpu: Add tracepoint for DMA page mapping (v4)Tom St Denis2-6/+106
This helps map DMA addresses back to physical addresses. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (v2): Added tracepoints for USERPTR, SG mappings, and SWIOTBL mappings. Reformatted trace call perform PCI decoding internal to the trace. (v3): Add unmap tracepoints as well (v4): Move traces into separate functions
2017-08-17drm/amdgpu: fix Vega10 HW config for 2MB pagesChristian König2-4/+4
Those values weren't correct. This should result in quite some speedup. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-17drm/amdgpu: only bind VM shadows after validation v2Christian König1-14/+8
No need to do this on every CS. v2: remove all other bind, reorder code Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-17drm/amdgpu: only move VM BOs in the LRU during validation v2Christian König3-59/+16
This should save us a bunch of command submission overhead. v2: move the LRU move to the right place to avoid the move for the root BO and handle the shadow BOs as well. This turned out to be a bug fix because the move needs to happen before the kmap. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-17drm/ttm: individualize BO reservation obj when they are freedChristian König1-7/+47
Use the BOs reservation object when it is put on the ddelete list. This way we avoid delaying freeing up the BO because of new fences on the reservation object. This is used by dma-buf and amdgpu's VM page tables. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-17drm/ttm: remove nonsense wait in ttm_bo_cleanup_refs_and_unlockChristian König1-7/+0
With shared reservation objects the assumption that no fence could have been added isn't true any more. Additional to that the BO is about to be destroyed, so removing the fences now has no advantage whatsoever. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-17drm/tegra: Prevent BOs from being freed during job submissionDmitry Osipenko1-9/+31
Since DRM IOCTL's are lockless, there is a chance that BOs could be released while a job submission is in progress. To avoid that, keep the GEM reference until the job has been pinned, part of which will be to take another reference. v2: remove redundant check and avoid memory leak Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-08-17drm/tegra: gem: Implement mmap() for PRIME buffersThierry Reding1-15/+34
The mapping of PRIME buffers can reuse much of the GEM mapping code, so extract the common bits into a new tegra_gem_mmap() helper. Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-08-17drm/tegra: Support render nodeThierry Reding1-15/+29
None of the driver-specific IOCTLs are privileged, so mark them as such and advertise that the driver supports render nodes. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-08-17drm/tegra: sor: Trace register accessesThierry Reding2-1/+14
Add tracepoint events for SOR controller register accesses. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-08-17drm/tegra: dpaux: Trace register accessesThierry Reding2-1/+14
Add tracepoint events for DPAUX controller register accesses. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-08-17drm/tegra: dsi: Trace register accessesThierry Reding2-1/+14
Add tracepoint events for DSI controller register accesses. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-08-17drm/tegra: hdmi: Trace register accessesThierry Reding2-1/+14
Add tracepoint events for HDMI controller register accesses. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-08-17drm/tegra: dc: Trace register accessesThierry Reding4-1/+51
Add tracepoint events for display controller register accesses. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-08-17drm/tegra: sor: Use unsigned int for register offsetsThierry Reding1-2/+2
Register offsets are usually fairly small numbers, so an unsigned int is more than enough to represent them. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-08-17drm/tegra: hdmi: Use unsigned int for register offsetsThierry Reding1-2/+2
Register offsets are usually fairly small numbers, so an unsigned int is more than enough to represent them. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-08-17drm/tegra: dsi: Use unsigned int for register offsetsThierry Reding1-4/+4
Register offsets are usually fairly small numbers, so an unsigned int is more than enough to represent them. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-08-17drm/tegra: dpaux: Use unsigned int for register offsetsThierry Reding1-2/+2
Register offsets are usually fairly small numbers, so an unsigned int is more than enough to represent them. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-08-17drm/tegra: dc: Use unsigned int for register offsetsThierry Reding1-2/+2
Register offsets are usually fairly small numbers, so an unsigned int is more than enough to represent them. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-08-17drm/tegra: Fix NULL deref in debugfs/iovaMichał Mirosław1-3/+5
When IOMMU is off, ->mm_lock is not initialized and ->mm is NULL. Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-08-17drm/tegra: switch to drm_*_get(), drm_*_put() helpersCihangir Akturk3-15/+15
Use drm_*_get() and drm_*_put() helpers instead of drm_*_reference() and drm_*_unreference() helpers. drm_*_reference() and drm_*_unreference() functions are just compatibility alias for drm_*_get() and drm_*_put() and should not be used by new code. So convert all users of compatibility functions to use the new APIs. Generated by: scripts/coccinelle/api/drm-get-put.cocci Signed-off-by: Cihangir Akturk <cakturk@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-08-17drm/tegra: Set MODULE_FIRMWARE for the VICNicolas Chauvet1-2/+13
The defines are set anyway to prevent an empty string. The test for the SoC is the same as for Nouveau for the Tegra GPU firmware (see drivers/gpu/drm/nouveau/nouveau_platform.c) v2: - Place the defines above each chip's vic_config struct - MODULE_FIRMWARE() at the end of the file Fixes: 0ae797a8ba05 ("drm/tegra: Add VIC support") Signed-off-by: Nicolas Chauvet <kwizart@gmail.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-08-17drm/tegra: Add CONFIG_OF dependencyArnd Bergmann1-0/+1
Without CONFIG_OF, we can run into a build error: drivers/gpu/drm/tegra/dpaux.c:378:20: error: 'pinconf_generic_dt_node_to_map_group' undeclared here (not in a function); did you mean 'pinconf_generic_params'? .dt_node_to_map = pinconf_generic_dt_node_to_map_group, ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ pinconf_generic_params drivers/gpu/drm/tegra/dpaux.c:379:17: error: 'pinconf_generic_dt_free_map' undeclared here (not in a function); did you mean 'pinconf_generic_params'? This adds an explicit dependency. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-08-17gpu: host1x: Support sub-devices recursivelyThierry Reding1-1/+17
The display architecture in Tegra186 changes slightly compared to earlier Tegra generations, which requires that we recursively scan host1x sub-devices from device tree. Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-08-17gpu: host1x: fix error return code in host1x_probe()Gustavo A. R. Silva1-2/+2
platform_get_irq() returns an error code, but the host1x driver ignores it and always returns -ENXIO. This is not correct and, prevents -EPROBE_DEFER from being propagated properly. Notice that platform_get_irq() no longer returns 0 on error: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e330b9a6bb35dc7097a4f02cb1ae7b6f96df92af Print and propagate the return value of platform_get_irq on failure. This issue was detected with the help of Coccinelle. Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-08-17gpu: host1x: Fix bitshift/mask multipliersMikko Perttunen2-13/+13
Some parts of Host1x uses BIT_WORD/BIT_MASK/BITS_PER_LONG to calculate register or field offsets. This worked fine on ARMv7, but now that BITS_PER_LONG is 64 but our registers are still 32-bit things are broken. Fix by replacing.. - BIT_WORD with (x / 32) - BIT_MASK with BIT(x % 32) - BITS_PER_LONG with 32 Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Tested-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-08-17gpu: host1x: Don't fail on NULL bo physical addressMikko Perttunen1-8/+0
Pinning a Host1x BO currently cannot fail and zero is a valid address for a BO when IOMMU is enabled. To avoid false errors remove checks for NULL BO physical addresses. Fixes: 404bfb78daf3 ("gpu: host1x: Add IOMMU support") Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-08-16drm/tinydrm: make function st7586_pipe_enable staticColin Ian King1-2/+2
The function st7586_pipe_enable is local to the source and does not need to be in global scope, so make it static. Cleans up sparse warning: symbol 'st7586_pipe_enable' was not declared. Should it be static? Signed-off-by: Colin Ian King <colin.king@canonical.com> Acked-By: David Lechner <david@lechnology.com> [noralf: fixed: Alignment should match open parenthesis] Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Link: https://patchwork.freedesktop.org/patch/msgid/20170816092306.10969-1-colin.king@canonical.com
2017-08-16MAINTAINERS: Add drm/tinydrm maintainer entryNoralf Trønnes1-0/+8
Add myself as drivers/gpu/drm/tinydrm maintainer. Signed-off-by: Noralf Trønnes <noralf@tronnes.org> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/1502645790-14944-1-git-send-email-noralf@tronnes.org
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