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AgeCommit message (Expand)AuthorFilesLines
2015-03-26drm/i915: always preserve bios swizzlingDaniel Vetter1-25/+22
2015-03-26drm/i915: Add initial_ prefix to bios fb takeover codeDaniel Vetter1-7/+7
2015-03-26drm/i915: Remove duplicated psr.active unsetRodrigo Vivi1-2/+0
2015-03-26drm/i915: Fixup legacy plane->crtc link for initial fb configDaniel Vetter1-0/+2
2015-03-26drm/i915: kill i915.powersaveRodrigo Vivi5-16/+3
2015-03-25drm/i915: Add fault address to error state for gen8 and gen9Mika Kuoppala3-0/+15
2015-03-25drm/i915/skl: Fix up positive error codeTvrtko Ursulin1-1/+1
2015-03-25drm/i915: make unsupported fb modifier message DRM_DEBUGJesse Barnes1-2/+2
2015-03-24drm/i915: Removing the drrs capability enum initializationRamalingam C1-2/+0
2015-03-24drm/i915: move clearing of RPS interrupt bits from disable to reset timeImre Deak1-9/+1
2015-03-24drm/i915: fix race when clearing RPS IIR bitsImre Deak1-0/+7
2015-03-23drm/i915/skl: Take 90/270 rotation into account in watermark calculationsTvrtko Ursulin4-9/+45
2015-03-23drm/i915/skl: Query display address through a wrapperTvrtko Ursulin3-7/+30
2015-03-23drm/i915/skl: Support secondary (rotated) frame buffer mappingTvrtko Ursulin5-6/+158
2015-03-23drm/i915: Helper function to determine GGTT view from plane stateTvrtko Ursulin1-3/+22
2015-03-23drm/i915: Pass in plane state when (un)pinning frame buffersTvrtko Ursulin3-7/+14
2015-03-23drm/i915: Use GGTT view when (un)pinning objects to planesTvrtko Ursulin4-16/+30
2015-03-23drm/i915/skl: Extract tile height code into a helper functionTvrtko Ursulin2-21/+29
2015-03-23drm/i915: Use usleep_range() in wait_for()Ville Syrjälä1-2/+2
2015-03-20drm/i915: Do not leak objects after capturing error stateMichel Thierry1-0/+7
2015-03-20drm/i915: Fix SKL sprite disable double buffer register updateVille Syrjälä1-2/+2
2015-03-20drm/i915: Eliminate plane control register RMW from sprite codeVille Syrjälä1-52/+10
2015-03-20drm/i915: Eliminate the RMW sprite colorkey managementVille Syrjälä2-235/+69
2015-03-20drm/i915: Move vblank wait determination to 'check' phaseMatt Roper1-14/+10
2015-03-20drm/i915/chv: use vlv_PLL_is_optimal in chv_find_best_dpllImre Deak1-6/+20
2015-03-20drm/i915: check for div-by-zero in vlv_PLL_is_optimalImre Deak1-0/+3
2015-03-20drm/i915: factor out vlv_PLL_is_optimalImre Deak1-14/+36
2015-03-20drm/i915: Kill intel_plane->objVille Syrjälä3-17/+10
2015-03-20drm/i915: Initialize all contextsBen Widawsky1-9/+19
2015-03-20drm/i915: Track page table reload needBen Widawsky5-6/+43
2015-03-20drm/i915: Track GEN6 page table usageBen Widawsky3-62/+219
2015-03-20drm/i915: Extract context switch skip and add pd load logicBen Widawsky1-2/+73
2015-03-20drm/i915: page table generalizationsMichel Thierry2-92/+96
2015-03-20drm/i915: Send out the full AUX addressVille Syrjälä1-2/+3
2015-03-20drm/i915: kerneldoc for i915_gem_shrinker.cDaniel Vetter4-2/+61
2015-03-20drm/i915: Extract i915_gem_shrinker.cDaniel Vetter4-277/+306
2015-03-20drm/i915: Use down ei for manual Baytrail RPS calculationsChris Wilson4-19/+4
2015-03-20drm/i915: Improved w/a for rps on BaytrailChris Wilson5-104/+81
2015-03-20drm/i915: Relax RPS contraints to allows setting minfreq on idleChris Wilson3-16/+35
2015-03-20drm/i915: Fallback to using CPU relocations for large batch buffersChris Wilson1-11/+75
2015-03-20drm/i915: Turn on PIN_GLOBAL in i915_gem_object_ggtt_pinTvrtko Ursulin1-1/+1
2015-03-20drm/i915: memory leak in __i915_gem_vma_create()Dan Carpenter1-3/+4
2015-03-20drm/i915/dp: return number of bytes written for short aux/i2c writesJani Nikula1-3/+8
2015-03-20drm/i915: Unconfuse DP link rate array namesVille Syrjälä3-38/+39
2015-03-20drm/i915: Include the sink/source/supported rates in debug outputVille Syrjälä1-0/+43
2015-03-20drm/i915: Add eDP intermediate frequencies for CHVVille Syrjälä1-0/+6
2015-03-20drm/i915: Avoid overflowing the DP link rate arraysVille Syrjälä1-0/+2
2015-03-20drm/i915: Fix MST link rate handlingVille Syrjälä3-8/+22
2015-03-20drm/i915: Use DP_LINK_RATE_SET whenever possibleVille Syrjälä1-6/+7
2015-03-20drm/i915: Fix max link rate in intel_dp_mode_valid()Ville Syrjälä2-1/+15
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