| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2021-12-08 | clk: renesas: r9a07g044: Add mux and divider for G clock |   Biju Das | 2 | -0/+10 |
| 2021-12-08 | clk: renesas: r9a07g044: Rename CLK_PLL3_DIV4 macro | Biju Das | 1 | -2/+2 |
| 2021-12-08 | clk: renesas: cpg-mssr: Add support for R-Car S4-8 |   Yoshihiro Shimoda | 5 | -0/+196 |
| 2021-12-08 | clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driver | Yoshihiro Shimoda | 7 | -341/+437 |
 |
index : wireguard-linux | |
| WireGuard for the Linux kernel | Jason A. Donenfeld |
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