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2024-06-17pinctrl: pinctrl-tps6594: make tps65224_muxval_remap and tps6594_muxval_remap as static to fix sparse warningNirmala Devi Mal Nadar1-2/+2
pinctrl: tps6594: Fix sparse warning. warning: symbol 'tps65224_muxval_remap' was not declared. Should it be static? warning: symbol 'tps6594_muxval_remap' was not declared. Should it be static? Signed-off-by: Nirmala Devi Mal Nadar <m.nirmaladevi@ltts.com> Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202405111523.9yt759uX-lkp@intel.com/ Link: https://lore.kernel.org/r/0109018f85002ae1-6fb831b2-74c2-4559-98f1-a3ef25e72558-000000@ap-south-1.amazonses.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: qcom: spmi: Add PMC8380Konrad Dybcio1-0/+1
PMC8380 is a new chip, featuring 10 GPIOs. Describe it. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240525-topic-pmc8380_gpio-v2-2-2de50cb28ac1@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17dt-bindings: pinctrl: qcom,pmic-gpio: Document PMC8380Konrad Dybcio1-0/+2
PMC8380 is a new PMIC used with X1 SoCs. Document it Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240525-topic-pmc8380_gpio-v2-1-2de50cb28ac1@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: core: reset gpio_device in loop in pinctrl_pins_show()Léo DUBOIN1-0/+1
We were not resetting the pointer to the associated gpio_device once we are done displaying a pin's information. This meant that once we reached the end of a gpio-range, if there were pins right after it that did not belong to any known range, they would be associated with the previous range's gpio device. This resulted in those pins appearing as <4294966783:old_gdev> instead of the expected <0:?> (due to gpio_num being -1). Signed-off-by: Léo DUBOIN <lduboin@freebox.fr> Link: https://lore.kernel.org/r/c40d0634abefa19e689ffd450e0f48a8d63c4fc4.1714049455.git.lduboin@freebox.fr Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: core: take into account the pins array in pinctrl_pins_show()Léo DUBOIN1-4/+13
We previously only looked at the 'pin_base' of the pinctrl_gpio_ranges struct for determining if a pin matched a GPIO number. This value is present only if the 'pins' array is not NULL, and is 0 otherwise. This means that GPIO ranges declared using gpiochip_add_pingroup_range(), thus making use of pins, were always matched by the pins in the range [0-npins] even if they contained pins in a completely separate range. Signed-off-by: Léo DUBOIN <lduboin@freebox.fr> Link: https://lore.kernel.org/r/6df39bd47942156be5713f8f4e317d2ad3e0ddeb.1714049455.git.lduboin@freebox.fr Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-06-17pinctrl: nuvoton: Add ma35d1 pinctrl and GPIO driverJacky Huang5-0/+3059
Add common pinctrl and GPIO driver for Nuvoton MA35 series SoC, and add support for ma35d1 pinctrl. Signed-off-by: Jacky Huang <ychuang3@nuvoton.com> Link: https://lore.kernel.org/r/20240521012447.42211-4-ychuang570808@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>