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2024-11-05clk: qcom: rpmh: add support for SAR2130PDmitry Baryshkov1-0/+13
Define clocks as supported by the RPMh on the SAR2130P platform. The msm-5.10 kernel declares just the CXO clock, the RF_CLK1 clock was added following recommendation from Taniya Das. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20241027-sar2130p-clocks-v5-7-ecad2a1432ba@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-05clk: qcom: rcg2: add clk_rcg2_shared_floor_opsDmitry Baryshkov2-5/+44
Generally SDCC clocks use clk_rcg2_floor_ops, however on SAR2130P platform it's recommended to use rcg2_shared_ops for all Root Clock Generators to park them instead of disabling. Implement a mix of those, clk_rcg2_shared_floor_ops. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241027-sar2130p-clocks-v5-6-ecad2a1432ba@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-05dt-bindings: clk: qcom,sm8450-gpucc: add SAR2130P compatiblesKonrad Dybcio3-0/+49
Expand qcom,sm8450-gpucc bindings to include SAR2130P. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241027-sar2130p-clocks-v5-5-ecad2a1432ba@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-05dt-bindings: clock: qcom,sm8550-dispcc: Add SAR2130P compatibleDmitry Baryshkov1-0/+1
Document compatible for the Display Clock Controller on SAR2130P platform. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241027-sar2130p-clocks-v5-4-ecad2a1432ba@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-05dt-bindings: clock: qcom,sm8550-tcsr: Add SAR2130P compatibleDmitry Baryshkov1-0/+1
Document compatible for the TCSR Clock Controller on SAR2130P platform. It is mostly compatible with the SM8550, except that it doesn't provide UFS clocks. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241027-sar2130p-clocks-v5-3-ecad2a1432ba@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-05dt-bindings: clock: qcom: document SAR2130P Global Clock ControllerDmitry Baryshkov2-0/+250
Add bindings for the Global Clock Controller (GCC) present on the Qualcomm SAR2130P platform. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241027-sar2130p-clocks-v5-2-ecad2a1432ba@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-05dt-bindings: clock: qcom,rpmhcc: Add SAR2130P compatibleDmitry Baryshkov1-0/+1
Document compatible for RPMh clock controller on SAR2130P platform. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241027-sar2130p-clocks-v5-1-ecad2a1432ba@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-03clk: qcom: Make GCC_6125 depend on QCOM_GDSCKonrad Dybcio1-0/+1
Like all other non-ancient Qualcomm clock drivers, QCOM_GDSC is required, as the GCC driver defines and instantiates a bunch of GDSCs. Add the missing dependency. Reported-by: Kamil Gołda <kamil.golda@protonmail.com> Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Link: https://lore.kernel.org/r/20241003-topic-6125kconfig-v1-1-f5e1efbff07c@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-23dt-bindings: clock: qcom: gcc-ipq9574: remove q6 bring up clock macrosManikanta Mylavarapu1-18/+0
Q6 firmware takes care of bringup clocks, so remove them. Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240820055618.267554-5-quic_gokulsri@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-23dt-bindings: clock: qcom: gcc-ipq5332: remove q6 bring up clock macrosManikanta Mylavarapu1-20/+0
Q6 firmware takes care of bringup clocks, so remove them. Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com> Link: https://lore.kernel.org/r/20240820055618.267554-4-quic_gokulsri@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-23clk: qcom: ipq9574: remove q6 bring up clocksManikanta Mylavarapu1-326/+0
Q6 firmware takes care of bringup clocks, so remove them from gcc driver. Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com> Link: https://lore.kernel.org/r/20240820055618.267554-3-quic_gokulsri@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-23clk: qcom: ipq5332: remove q6 bring up clocksManikanta Mylavarapu1-380/+0
Q6 firmware takes care of bringup clocks, so remove them from gcc driver. Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com> Link: https://lore.kernel.org/r/20240820055618.267554-2-quic_gokulsri@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-22clk: qcom: clk-alpha-pll: fix lucid 5lpe pll enabled checkJohan Hovold1-3/+2
The lucid 5lpe PLL enable check only checks for an impossible negative return value and does not actually return as intended in case the PLL is already enabled (e.g. has been left enabled by boot firmware). Fixes: f4c7e27aa4b6 ("clk: qcom: clk-alpha-pll: Add support for Lucid 5LPE PLL") Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20241022080521.359-3-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-22clk: qcom: clk-alpha-pll: drop lucid-evo pll enabled warningJohan Hovold1-6/+1
The boot firmware may have left the display enabled and its PLL running, which currently generates a warning on boot (e.g. on x1e80100): disp_cc_pll0 PLL is already enabled Drop the bogus warning and fix up the PLL enabled error handling (trion_pll_is_enabled() only returns 0 or 1). Fixes: d1b121d62b7e ("clk: qcom: Add LUCID_EVO PLL type for SDX65") Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20241022080521.359-2-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-22clk: qcom: gcc-qcs404: fix initial rate of GPLL3Gabor Juhos1-0/+1
The comment before the config of the GPLL3 PLL says that the PLL should run at 930 MHz. In contrary to this, calculating the frequency from the current configuration values by using 19.2 MHz as input frequency defined in 'qcs404.dtsi', it gives 921.6 MHz: $ xo=19200000; l=48; alpha=0x0; alpha_hi=0x0 $ echo "$xo * ($((l)) + $(((alpha_hi << 32 | alpha) >> 8)) / 2^32)" | bc -l 921600000.00000000000000000000 Set 'alpha_hi' in the configuration to a value used in downstream kernels [1][2] in order to get the correct output rate: $ xo=19200000; l=48; alpha=0x0; alpha_hi=0x70 $ echo "$xo * ($((l)) + $(((alpha_hi << 32 | alpha) >> 8)) / 2^32)" | bc -l 930000000.00000000000000000000 The change is based on static code analysis, compile tested only. [1] https://git.codelinaro.org/clo/la/kernel/msm-5.4/-/blob/kernel.lnx.5.4.r56-rel/drivers/clk/qcom/gcc-qcs404.c?ref_type=heads#L335 [2} https://git.codelinaro.org/clo/la/kernel/msm-5.15/-/blob/kernel.lnx.5.15.r49-rel/drivers/clk/qcom/gcc-qcs404.c?ref_type=heads#L127 Cc: stable@vger.kernel.org Fixes: 652f1813c113 ("clk: qcom: gcc: Add global clock controller driver for QCS404") Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Link: https://lore.kernel.org/r/20241022-fix-gcc-qcs404-gpll3-v1-1-c4d30d634d19@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-22clk: qcom: Add support for Display clock Controllers on SA8775PTaniya Das4-0/+2973
Add support for display0 and display1 clock controllers on SA8775P platform. Reviewed-by: Jagadeesh Kona <quic_jkona@quicinc.com> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20241011-sa8775p-mm-v4-resend-patches-v5-6-4a9f17dc683a@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-22clk: qcom: Add support for Camera Clock Controller on SA8775PTaniya Das3-0/+1879
Add support for Camera Clock Controller on SA8755P platform. Reviewed-by: Jagadeesh Kona <quic_jkona@quicinc.com> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20241011-sa8775p-mm-v4-resend-patches-v5-4-4a9f17dc683a@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-22clk: qcom: Add support for Video clock controller on SA8775PTaniya Das3-0/+588
Add support for Video Clock Controller for SA8775P platform. Reviewed-by: Jagadeesh Kona <quic_jkona@quicinc.com> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20241011-sa8775p-mm-v4-resend-patches-v5-2-4a9f17dc683a@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-22dt-bindings: clock: qcom: Add SA8775P display clock controllersTaniya Das2-0/+166
Add device tree bindings for the display clock controllers on Qualcomm SA8775P platform. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20241011-sa8775p-mm-v4-resend-patches-v5-5-4a9f17dc683a@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-22dt-bindings: clock: qcom: Add SA8775P camera clock controllerTaniya Das2-0/+170
Add device tree bindings for the camera clock controller on Qualcomm SA8775P platform. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20241011-sa8775p-mm-v4-resend-patches-v5-3-4a9f17dc683a@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-22dt-bindings: clock: qcom: Add SA8775P video clock controllerTaniya Das2-0/+109
Add device tree bindings for the video clock controller on Qualcomm SA8775P platform. Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20241011-sa8775p-mm-v4-resend-patches-v5-1-4a9f17dc683a@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-14clk: qcom: videocc-sm8550: depend on either gcc-sm8550 or gcc-sm8650Jonathan Marek1-2/+2
This driver is compatible with both sm8550 and sm8650, fix the Kconfig entry to reflect that. Fixes: da1f361c887c ("clk: qcom: videocc-sm8550: Add SM8650 video clock controller") Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241005144047.2226-1-jonathan@marek.ca Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05clk: qcom: constify static 'struct qcom_icc_hws_data'Krzysztof Kozlowski3-3/+3
Drivers and core code does not modify the file-scope static 'struct qcom_icc_hws_data', so it can be made const for code safety and readability. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240905150235.276345-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05clk: qcom: camcc-sm8450: Add SM8475 supportDanila Tikhonov2-11/+285
Add support to the SM8475 camera clock controller by extending the SM8450 camera clock controller, which is almost identical but has some minor differences. Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Link: https://lore.kernel.org/r/20240818204348.197788-11-danila@jiaxyga.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05clk: qcom: videocc-sm8450: Add SM8475 supportDanila Tikhonov2-4/+46
Add support to the SM8475 video clock controller by extending the SM8450 video clock controller, which is almost identical but has some minor differences. Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Link: https://lore.kernel.org/r/20240818204348.197788-9-danila@jiaxyga.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05clk: qcom: gpucc-sm8450: Add SM8475 supportDanila Tikhonov2-6/+47
Add support to the SM8475 graphics clock controller by extending the SM8450 graphics clock controller, which is almost identical but has some minor differences. Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Link: https://lore.kernel.org/r/20240818204348.197788-7-danila@jiaxyga.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05clk: qcom: dispcc-sm8450: Add SM8475 supportDanila Tikhonov2-4/+64
Add support to the SM8475 display clock controller by extending the SM8450 display clock controller, which is almost identical but has some minor differences. Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Link: https://lore.kernel.org/r/20240818204348.197788-5-danila@jiaxyga.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05clk: qcom: gcc-sm8450: Add SM8475 supportDanila Tikhonov2-2/+182
Add support to the SM8475 global clock controller by extending the SM8450 global clock controller, which is almost identical but has some minor differences. Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Link: https://lore.kernel.org/r/20240818204348.197788-3-danila@jiaxyga.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05dt-bindings: clock: qcom,sm8450-camcc: Add SM8475 CAMCC bindingsDanila Tikhonov1-0/+1
Add new entry to the SM8450 dt-bindings for the SM8475 clocks. Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Link: https://lore.kernel.org/r/20240818204348.197788-10-danila@jiaxyga.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05dt-bindings: clock: qcom,sm8450-videocc: Add SM8475 VIDEOCC bindingsDanila Tikhonov1-0/+1
Add new entry to the SM8450 dt-bindings for the SM8475 clocks. Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240818204348.197788-8-danila@jiaxyga.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05dt-bindings: clock: qcom,sm8450-gpucc: Add SM8475 GPUCC bindingsDanila Tikhonov1-0/+1
Add new entry to the SM8450 dt-bindings for the SM8475 clocks. Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240818204348.197788-6-danila@jiaxyga.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05dt-bindings: clock: qcom,sm8450-dispcc: Add SM8475 DISPCC bindingsDanila Tikhonov1-0/+1
Add new entry to the SM8450 dt-bindings for the SM8475 clocks. Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240818204348.197788-4-danila@jiaxyga.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05dt-bindings: clock: qcom,gcc-sm8450: Add SM8475 GCC bindingsDanila Tikhonov2-1/+6
Add new entry to the SM8450 dt-bindings and add SM8475-specific clocks to SM8450 GCC header file. Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240818204348.197788-2-danila@jiaxyga.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-09-29Linux 6.12-rc1Linus Torvalds1-2/+2
2024-09-29x86: kvm: fix build errorLinus Torvalds1-0/+2
The cpu_emergency_register_virt_callback() function is used unconditionally by the x86 kvm code, but it is declared (and defined) conditionally: #if IS_ENABLED(CONFIG_KVM_INTEL) || IS_ENABLED(CONFIG_KVM_AMD) void cpu_emergency_register_virt_callback(cpu_emergency_virt_cb *callback); ... leading to a build error when neither KVM_INTEL nor KVM_AMD support is enabled: arch/x86/kvm/x86.c: In function ‘kvm_arch_enable_virtualization’: arch/x86/kvm/x86.c:12517:9: error: implicit declaration of function ‘cpu_emergency_register_virt_callback’ [-Wimplicit-function-declaration] 12517 | cpu_emergency_register_virt_callback(kvm_x86_ops.emergency_disable_virtualization_cpu); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ arch/x86/kvm/x86.c: In function ‘kvm_arch_disable_virtualization’: arch/x86/kvm/x86.c:12522:9: error: implicit declaration of function ‘cpu_emergency_unregister_virt_callback’ [-Wimplicit-function-declaration] 12522 | cpu_emergency_unregister_virt_callback(kvm_x86_ops.emergency_disable_virtualization_cpu); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Fix the build by defining empty helper functions the same way the old cpu_emergency_disable_virtualization() function was dealt with for the same situation. Maybe we could instead have made the call sites conditional, since the callers (kvm_arch_{en,dis}able_virtualization()) have an empty weak fallback. I'll leave that to the kvm people to argue about, this at least gets the build going for that particular config. Fixes: 590b09b1d88e ("KVM: x86: Register "emergency disable" callbacks when virt is enabled") Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Sean Christopherson <seanjc@google.com> Cc: Kai Huang <kai.huang@intel.com> Cc: Chao Gao <chao.gao@intel.com> Cc: Farrah Chen <farrah.chen@intel.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2024-09-28Reduce Coccinelle choices in string_choices.cocciJulia Lawall1-50/+41
The isomorphism neg_if_exp negates the test of a ?: conditional, making it unnecessary to have an explicit case for a negated test with the branches inverted. At the same time, we can disable neg_if_exp in cases where a different API function may be more suitable for a negated test. Finally, in the non-patch cases, E matches an expression with parentheses around it, so there is no need to mention () explicitly in the pattern. The () are still needed in the patch cases, because we want to drop them, if they are present. Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
2024-09-28coccinelle: Remove unnecessary parentheses for only one possible change.Hongbo Li1-8/+0
The parentheses are only needed if there is a disjunction, ie a set of possible changes. If there is only one pattern, we can remove these parentheses. Just like the format: - x + y not: ( - x + y ) Signed-off-by: Hongbo Li <lihongbo22@huawei.com> Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
2024-09-28coccinelle: Add rules to find str_yes_no() replacementsHongbo Li1-0/+19
As other rules done, we add rules for str_yes_no() to check the relative opportunities. Signed-off-by: Hongbo Li <lihongbo22@huawei.com> Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
2024-09-28coccinelle: Add rules to find str_on_off() replacementsHongbo Li1-0/+19
As other rules done, we add rules for str_on_off() to check the relative opportunities. Signed-off-by: Hongbo Li <lihongbo22@huawei.com> Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
2024-09-28coccinelle: Add rules to find str_write_read() replacementsHongbo Li1-0/+19
As other rules done, we add rules for str_write_read() to check the relative opportunities. Signed-off-by: Hongbo Li <lihongbo22@huawei.com> Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
2024-09-28coccinelle: Add rules to find str_read_write() replacementsHongbo Li1-0/+19
As other rules done, we add rules for str_read_write() to check the relative opportunities. Signed-off-by: Hongbo Li <lihongbo22@huawei.com> Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
2024-09-28coccinelle: Add rules to find str_enable{d}_disable{d}() replacementsHongbo Li1-0/+38
As other rules done, we add rules for str_enable{d}_ disable{d}() to check the relative opportunities. Signed-off-by: Hongbo Li <lihongbo22@huawei.com> Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
2024-09-28coccinelle: Add rules to find str_lo{w}_hi{gh}() replacementsHongbo Li1-0/+38
As other rules done, we add rules for str_lo{w}_hi{gh}() to check the relative opportunities. Signed-off-by: Hongbo Li <lihongbo22@huawei.com> Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
2024-09-28coccinelle: Add rules to find str_hi{gh}_lo{w}() replacementsHongbo Li1-0/+42
As other rules done, we add rules for str_hi{gh}_lo{w}() to check the relative opportunities. Signed-off-by: Hongbo Li <lihongbo22@huawei.com> Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
2024-09-28coccinelle: Add rules to find str_false_true() replacementsHongbo Li1-0/+19
As done with str_true_false(), add checks for str_false_true() opportunities. A simple test can find over 9 cases currently exist in the tree. Signed-off-by: Hongbo Li <lihongbo22@huawei.com> Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
2024-09-28coccinelle: Add rules to find str_true_false() replacementsHongbo Li1-0/+19
After str_true_false() has been introduced in the tree, we can add rules for finding places where str_true_false() can be used. A simple test can find over 10 locations. Signed-off-by: Hongbo Li <lihongbo22@huawei.com> Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
2024-09-27bcachefs: check_subvol_path() now prints subvol root inodeKent Overstreet2-20/+14
Signed-off-by: Kent Overstreet <kent.overstreet@linux.dev>
2024-09-27bcachefs: remove_backpointer() now checks if dirent points to inodeKent Overstreet1-6/+9
Signed-off-by: Kent Overstreet <kent.overstreet@linux.dev>
2024-09-27bcachefs: dirent_points_to_inode() now warns on mismatchKent Overstreet1-28/+56
if an inode backpointer points to a dirent that doesn't point back, that's an error we should warn about. Signed-off-by: Kent Overstreet <kent.overstreet@linux.dev>
2024-09-27bcachefs: Fix lost wake upAlan Huang1-3/+9
If the reader acquires the read lock and then the writer enters the slow path, while the reader proceeds to the unlock path, the following scenario can occur without the change: writer: pcpu_read_count(lock) return 1 (so __do_six_trylock will return 0) reader: this_cpu_dec(*lock->readers) reader: smp_mb() reader: state = atomic_read(&lock->state) (there is no waiting flag set) writer: six_set_bitmask() then the writer will sleep forever. Signed-off-by: Alan Huang <mmpgouride@gmail.com> Signed-off-by: Kent Overstreet <kent.overstreet@linux.dev>