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The board uses lane 3 of SERDES for USB. Set the mux
accordingly.
The USB controller and EVM supports super-speed for USB0
on the Type-C port. However, the SERDES has a limitation
that upto 2 protocols can be used at a time. The SERDES is
wired for PCIe, QSGMII and USB super-speed. It has been
chosen to use PCI2 and QSGMII as default. So restrict
USB0 to high-speed mode.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20200930122032.23481-7-rogerq@ti.com
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First two lanes of SERDES is connected to PCIe, third lane is
connected to QSGMII and the last lane is connected to USB. However,
Cadence torrent SERDES doesn't support more than 2 protocols
at the same time. Configure it only for PCIe and QSGMII.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20200930122032.23481-6-rogerq@ti.com
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j7200 has on USB controller instance. Add that.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20200930122032.23481-5-rogerq@ti.com
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The USB controller can be connected to one of the 2 lanes
of SERDES0 using a MUX. Add a MUX controller node for that.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20200930122032.23481-4-rogerq@ti.com
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The SERDES lane control mux registers are present in the
CTRLMMR space.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20200930122032.23481-3-rogerq@ti.com
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There are 4 lanes in each J7200 SERDES. Each SERDES lane mux can
select upto 4 different IPs. Define all the possible functions.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Peter Rosin <peda@axentia.se>
Cc: Peter Rosin <peda@axentia.se>
Link: https://lore.kernel.org/r/20200930122032.23481-2-rogerq@ti.com
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Fix the leds subnode names to match (^led-[0-9a-f]$|led).
Similar change has been also done by commit 08dc0e5dd9aa ("arm64: dts:
meson: fix leds subnodes name").
The patch is fixing this warning:
avnet-ultra96-rev1.dt.yaml: leds: 'ds2', 'ds3', 'ds4', 'ds5' do not match
any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+'
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/1a69c3fa0291f991ffcf113ea222c713ba4d4ff0.1598264917.git.michal.simek@xilinx.com
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u-boot, DT properties are not documented anywhere in Linux DT binding
that's why remove them.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/8ba339425b9c9f319bdedce7741367055a30713c.1598257720.git.michal.simek@xilinx.com
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
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DT binding permits only one compatible string which was decribed in past by
commit 63cab195bf49 ("i2c: removed work arounds in i2c driver for Zynq
Ultrascale+ MPSoC").
The commit aea37006e183 ("dt-bindings: i2c: cadence: Migrate i2c-cadence
documentation to YAML") has converted binding to yaml and the following
issues is reported:
...: i2c@ff030000: compatible: Additional items are not allowed
('cdns,i2c-r1p10' was unexpected)
From schema:
.../Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml fds
...: i2c@ff030000: compatible: ['cdns,i2c-r1p14', 'cdns,i2c-r1p10'] is too
long
The commit c415f9e8304a ("ARM64: zynqmp: Fix i2c node's compatible string")
has added the second compatible string but without removing origin one.
The patch is only keeping one compatible string "cdns,i2c-r1p14".
Fixes: c415f9e8304a ("ARM64: zynqmp: Fix i2c node's compatible string")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/cc294ae1a79ef845af6809ddb4049f0c0f5bb87a.1598259551.git.michal.simek@xilinx.com
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
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Rename amba-apu and amba to AXI. Based on Xilinx ZynqMP TRM (Chapter 15)
chip is "using the advanced eXtensible interface (AXI) point-to-point
channels for communicating addresses, data, and response transactions
between master and slave clients."
Issues are reported as:
...: amba: $nodename:0: 'amba' does not match
'^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$'
From schema: .../dt-schema/dtschema/schemas/simple-bus.yaml
...: amba-apu@0: $nodename:0: 'amba-apu@0' does not match
'^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$'
From schema: .../dt-schema/dtschema/schemas/simple-bus.yaml
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/68f20a2b2bb0feee80bc3348619c2ee98aa69963.1598263539.git.michal.simek@xilinx.com
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
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The convention for node names is to use hyphens, not underscores.
dtschema for pca95xx expects GPIO hogs to end with 'hog' prefix.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20200916155715.21009-8-krzk@kernel.org
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Add support for "allwinner,simple-framebuffer"
with "mixer0-lcd0" pipeline from boot loader (u-boot).
It depends on boot loader implementation of DE2/TCON0
setup with LCD.
Signed-off-by: Martin Cerveny <m.cerveny@computer.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20200916175941.8448-1-m.cerveny@computer.org
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The Pine64 PineCube IP camera is an IP camera with SoChip S3 SoC.
It comes with a main board, an expansion board and a camera.
The main board features a Micro-USB power-only jack, a USB Type-A port,
an Ethernet port connected to the internal PHY of the SoC and a Realtek
RTL8189ES SDIO Wi-Fi module. A RGB LCD connector is reserved on the
board.
The expansion board features a TF slot, a microphone, a speaker
connector with on-board amplifier and a few IR LEDs.
Add support for the kit, with features on the main board and the
expansion board now.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20200923010215.148819-2-icenowy@aosc.io
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Document board compatible names for Pine64 PineCube IP camera.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20200923010215.148819-1-icenowy@aosc.io
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I2C1 controller is available at PE bank, usually used for
connecting an I2C-controlled camera sensor.
Add pinctrl node for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20200923010014.148482-2-icenowy@aosc.io
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The CSI1 controller of V3/V3s/S3/S3L SoCs is used for parallel CSI.
As we're going to add support for Pine64 SCC board, which uses 8-bit
parallel CSI (and the MCLK output), add the pinctrl node of 8-bit
CSI and MCLK to the DTSI file.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20200923010122.148661-1-icenowy@aosc.io
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The CSI1 controller of V3/V3s/S3/S3L chips is used for parallel CSI.
Add the device tree node of it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20200923005858.148261-2-icenowy@aosc.io
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The UART2 RX/TX pins on Allwinner V3 series is at PB0/1, which is used
as debugging UART on some boards.
Add pinctrl node for them.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20200923005858.148261-1-icenowy@aosc.io
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The Allwinner V3/V3s/S3L/SoChip S3 Ethernet MAC and internal PHY is quite
similar to the ones on Allwinner H3, except for V3s the external MII is
not wired out.
Add ethernet support to V3/V3s/S3/S3L.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20200923005709.147966-2-icenowy@aosc.io
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The Synopsys DesignWare APB GPIO controller port must have gpio-cells
property, as pointed by dtschema:
arch/arm64/boot/dts/apm/apm-mustang.dt.yaml: gpio@1c024000: gpio-controller@0: '#gpio-cells' is a required property
Link: https://lore.kernel.org/r/20200917165040.22908-2-krzk@kernel.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
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The Synopsys DesignWare APB GPIO controller driver does not parse
reg-io-width and dtschema does not allow it so drop it to fix dtschema
warnings like:
arch/arm64/boot/dts/apm/apm-mustang.dt.yaml: gpio@1c024000:
'reg-io-width' does not match any of the regexes: '^gpio-(port|controller)@[0-9a-f]+$', 'pinctrl-[0-9]+'
Link: https://lore.kernel.org/r/20200917165040.22908-1-krzk@kernel.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
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The Synopsys DesignWare APB GPIO controller driver does not parse
reg-io-width and dtschema does not allow it so drop it to fix dtschema
warnings like:
arch/arm/boot/dts/picoxcell-pc7302-pc3x2.dt.yaml: gpio@20000:
'reg-io-width' does not match any of the regexes: '^gpio-(port|controller)@[0-9a-f]+$', 'pinctrl-[0-9]+'
Link: https://lore.kernel.org/r/20200917164909.22490-1-krzk@kernel.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Jamie Iles <jamie@jamieiles.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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Add ARCH_PICOXCELL entries to Makefil so the DTBs get built with
`make dtbs`.
Link: https://lore.kernel.org/r/20200917163957.21895-1-krzk@kernel.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
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The convention for node names is to use hyphens, not underscores.
dtschema for pca95xx expects GPIO hogs to end with 'hog' prefix.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20200916155715.21009-7-krzk@kernel.org
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Correct the property for reset GPIOs of the GPIO expander.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The convention for node names is to use hyphens, not underscores.
dtschema for pca95xx expects GPIO hogs to end with 'hog' prefix.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The PCA9539 GPIO expander requires GPIO controller properties to operate
properly.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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All am437x boards have been converted to use new driver, so drop legacy
cpsw dt node.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The dual_mac mode has been preserved the same way between legacy and new
driver, and one port devices works the same as 1 dual_mac port - it's safe
to switch drivers.
So, Switch all am437x boards to use new cpsw switch driver. Those boards
have or 2 Ext. port wired and configured in dual_mac mode by default, or
only 1 Ext. port.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Add DT node for the new cpsw switchdev based driver.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Add support for the eMMC and SD card connected on the common
processor board
sdhci0 is connected to an eMMC while sdhci1 is connected to the
micro SD slot.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Sekhar Nori <nsekhar@ti.com>
Link: https://lore.kernel.org/r/20200924112644.11076-3-faiz_abbas@ti.com
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Add support for MMC/SD controller nodes present on TI's j7200 SoCs.
There are two nodes:
1. sdhci0 (8 bit bus width, 200 MHz, HS200, 200 MBps)
2. sdhci1 (4 bit bus width, 50 MHz, HS, 25 MBps)
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Sekhar Nori <nsekhar@ti.com>
Link: https://lore.kernel.org/r/20200924112644.11076-2-faiz_abbas@ti.com
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J7200 SoM has a HyperFlash connected to HyperBus memory controller. But
HyperBus is muxed with OSPI, therefore keep HyperBus node disabled.
Bootloader will detect the mux and enable the node as required.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Sekhar Nori <nsekhar@ti.com>
Link: https://lore.kernel.org/r/20200923163150.16973-3-vigneshr@ti.com
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J7200 has a Flash SubSystem that has one OSPI and one HyperBus.. Add
DT nodes for HyperBus controller for now.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Sekhar Nori <nsekhar@ti.com>
Link: https://lore.kernel.org/r/20200923163150.16973-2-vigneshr@ti.com
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Add DT nodes for I2C GPIO expanders on main_i2c0 and main_i2c1 and
also add the pinmux corresponding to these I2C instances.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: Faiz Abbas <faiz_abbas@ti.com>
Link: https://lore.kernel.org/r/20200923155400.13757-3-vigneshr@ti.com
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J7200 has 7 I2Cs in main domain, 2 I2Cs in MCU and 1 in wakeup domain.
Add DT nodes for the same.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: Faiz Abbas <faiz_abbas@ti.com>
Link: https://lore.kernel.org/r/20200923155400.13757-2-vigneshr@ti.com
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The TI J7200 EVM base board has TI DP83867 PHY connected to external CPSW
NUSS Port 1 in rgmii-rxid mode.
Hence, add pinmux and Ethernet PHY configuration for TI J7200 SoC MCU
Gigabit Ethernet two ports Switch subsystem (CPSW NUSS).
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Link: https://lore.kernel.org/r/20200923220938.30788-5-grygorii.strashko@ti.com
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Add DT node for The TI J7200 MCU SoC Gigabit Ethernet two ports Switch
subsystem (MCU CPSW NUSS).
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Link: https://lore.kernel.org/r/20200923220938.30788-4-grygorii.strashko@ti.com
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Add DT node for Main NAVSS CPTS module.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Link: https://lore.kernel.org/r/20200923220938.30788-3-grygorii.strashko@ti.com
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Add the ringacc and udmap nodes for Main and MCU NAVSS.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Link: https://lore.kernel.org/r/20200923220938.30788-2-grygorii.strashko@ti.com
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sm8250 has 24 thermal sensors split across two tsens controllers. Add
the thermal zones to expose them and wireup the cpus to throttle on
crossing passive temperature thresholds.
Signed-off-by: Amit Kucheria <amitk@kernel.org>
Link: https://lore.kernel.org/r/89b83b3caa4e32db08fe402cfa510feb25232aa0.1599732068.git.amitk@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Add arm-pmu node on stm32mp15.
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: Marek Vasut <marex@denx.de> # update to linux-next
Tested-by: Marek Vasut <marex@denx.de> # on DH PDK2 and Avenger96
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
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This patch adds FMC2 External Bus Interface support on stm32mp157c.
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
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The "eMMC high-speed DDR mode (3.3V I/O)" at 50MHz is supported on
the eMMC-interface of the lxa-mc1. Set it in the device tree to
benefit from the speed improvement.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Holger Assmann <h.assmann@pengutronix.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
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The display PWM channel is number 3 (PWM2 CH4), make it so.
Fixes: 34e0c7847dcf ("ARM: dts: stm32: Add DH Electronics DHCOM STM32MP1 SoM and PDK2 board")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
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The DH AV96 has RTS/CTS lines available on UART7, describe them in DT.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
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On the production revision of the SoM, 587-200, the PHY reset GPIO and
touchscreen IRQs are swapped to prevent collision between EXTi IRQs,
reflect that in DT.
Fixes: 34e0c7847dcf ("ARM: dts: stm32: Add DH Electronics DHCOM STM32MP1 SoM and PDK2 board")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: linux-stm32@st-md-mailman.stormreply.com
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
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Previously the FIFO on the stm32h743 usart was not utilized, because
the stm32f7 compatible configures it without FIFO support.
Signed-off-by: Tobias Schramm <t.schramm@manjaro.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
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The stm32 spi driver tries to determine the fifo size of spi devices
dynamically. However, if the spi was already configured by the bootloader
the fifo size check can become an endless loop, because the driver
expects the spi to be in its initial "after device reset" state. The
driver does already support resetting the spi device at probe, thus this
patch adds only the required device tree properties
Signed-off-by: Tobias Schramm <t.schramm@manjaro.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
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Declare LTDC (display controller) on stm32h743.
Signed-off-by: Tobias Schramm <t.schramm@manjaro.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
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Roger Quadros
Kishon Vijay Abraham I
Michal Simek
Krzysztof Kozlowski
Martin Cerveny
Icenowy Zheng
Grygorii Strashko
Faiz Abbas
Vignesh Raghavendra
Peter Ujfalusi
Amit Kucheria
Alexandre Torgue
Christophe Kerello
Ahmad Fatoum
Marek Vasut
Tobias Schramm