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2023-08-04ARM: dts: at91: remove duplicated entriesClaudiu Beznea1-14/+1
Remove duplicated DTC_FLAGS_<board> := -@ entries which intends to enable the building of device tree overlays. Commit 724ba6751532 ("ARM: dts: Move .dts files to vendor sub-directories") added those entries at the beginning of file w/o removing the already available entries spread though file. Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20230721053918.33944-1-claudiu.beznea@tuxon.dev Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2023-08-03arm64: dts: hi3798cv200: Fix clocks order of sd0David Yang1-2/+2
"ciu" and "biu" were incorrectly swapped. Fix their order. Signed-off-by: David Yang <mmyangfl@gmail.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2023-08-02ARM: dts: microchip: split interrupts per cellsKrzysztof Kozlowski4-35/+35
Each interrupt should be in its own cell. This is much more readable. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230730111542.98238-1-krzysztof.kozlowski@linaro.org Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2023-07-31ARM: dts: at91: ksz9477_evb: Add tx-internal-delay-ps property for port5Lukasz Majewski1-0/+1
Without this change the KSZ9477 Evaluation board's Linux (v6.5-rc1) shows following device warning: 'ksz-switch spi1.0: Port 5 interpreting RGMII delay settings based on "phy-mode" property, please update device tree to specify "rx-internal-delay-ps" and "tx-internal-delay-ps"' This is not critical, as KSZ driver by itself assigns default value of tx delay to 2000 ps (as 'rgmii-txid' is set as PHY mode). However, to avoid extra warnings in logs - the missing 'tx-internal-delay-ps' has been specified with the default value of 2000 ps. Signed-off-by: Lukasz Majewski <lukma@denx.de> Link: https://lore.kernel.org/r/20230727080656.3828397-1-lukma@denx.de Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2023-07-31ARM: dts: at91: ksz9477_evb: Add missing timer nodesLukasz Majewski1-0/+12
Without this change the KSZ9477-EVB board hangs just after passing execution flow from u-boot to Linux kernel. This code has been copied from at91-sama5d3_xplained.dts. Test setup: Linux 6.5-rc1 Config: arch/arm/configs/sama5_defconfig Toolchain: gcc-linaro-7.3.1-2018.05-x86_64_arm-linux-gnueabi Signed-off-by: Lukasz Majewski <lukma@denx.de> Link: https://lore.kernel.org/r/20230712152111.3756211-1-lukma@denx.de Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2023-07-31ARM: dts: at91-vinco: Fix "status" valuesRob Herring1-2/+2
The defined value for "status" is "disabled", not "disable". Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20230626221010.3946263-1-robh@kernel.org Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2023-07-29arm64: dts: microchip: minor whitespace cleanup around '='Krzysztof Kozlowski1-6/+6
The DTS code coding style expects exactly one space before and after '=' sign. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230702185108.43959-1-krzysztof.kozlowski@linaro.org [claudiu.beznea: added link] Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2023-07-29ARM: dts: microchip: add missing space before {Krzysztof Kozlowski9-9/+9
Add missing whitespace between node name/label and opening {. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230705150058.293942-1-krzysztof.kozlowski@linaro.org [claudiu.beznea: added link] Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2023-07-29ARM: dts: microchip: minor whitespace cleanup around '='Krzysztof Kozlowski1-1/+1
The DTS code coding style expects exactly one space before and after '=' sign. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230702185108.43959-1-krzysztof.kozlowski@linaro.org [claudiu.beznea: added link] Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2023-07-27ARM: tegra: Provide specific compatible string for Nexus 7 panelThierry Reding1-8/+4
panel-lvds alone is not a valid compatible string and we always need a specific compatible string as well. Nexus 7 can come with one of (at least) two panels, so pick one of them as the specific compatible string. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-27ARM: tegra: Use Hannstar HSD101PWW2 on Pegatron ChagallThierry Reding1-1/+1
The LVDS bindings require a specific compatible string in addition to the generic "panel-lvds". Add the HannStar HSD101PWW2 which is used on a similar device (ASUS TF201) and seems to work fine with slightly modified timings in DT. Suggested-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-27ARM: tegra: Reuse I2C3 for NVECThierry Reding1-10/+9
Instead of duplicating the I2C3 node and adding NVEC specific properties, reuse the I2C3 node, extend it with NVEC specific properties and drop properties that are not needed by NVEC. This results in a DTB that is a bit cleaner and avoids accidentally using I2C3 and NVEC which would have them fight over the same hardware resources. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-27arm64: tegra: Add blank lines for better readabilityThierry Reding1-0/+8
Add a few blank lines to visually separate blocks in the Jetson AGX Orin device tree. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-27arm64: tegra: Remove {clock,reset}-names from VIC powergateThierry Reding1-2/+0
According to the device tree bindings, the powergate definition nodes don't contain clock-names and reset-names properties, so remove them. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-27arm64: tegra: Drop incorrect maxim,disable-etr on SmaugKrzysztof Kozlowski1-1/+0
There is no "maxim,disable-etr" property (but there is maxim,enable-etr), neither in the bindings nor in the Linux driver: tegra210-smaug.dtb: regulator@1c: Unevaluated properties are not allowed ('maxim,disable-etr' was unexpected) Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-27arm64: tegra: Add SPI device tree nodes for Tegra234Gautham Srinivasan1-0/+57
Create the device tree nodes for the SPI1, SPI2 and SPI3 controllers found on Tegra234. Signed-off-by: Gautham Srinivasan <gauthams@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-27arm64: tegra: Enable UARTA and UARTE for Orin NanoGautham Srinivasan1-0/+14
Activate UARTA and UARTE functionalities for Orin Nano. - UARTA is accessible via the 40-pin header with pin 8 and 10 (TX/RX) - UARTE utilizes the M2.E connector Signed-off-by: Gautham Srinivasan <gauthams@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-27arm64: tegra: Add UARTE device tree node on Tegra234Gautham Srinivasan1-0/+9
This commit adds the device tree node for UARTE on Tegra234. Signed-off-by: Gautham Srinivasan <gauthams@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-27arm64: dts: renesas: spider-cpu: Add GP LEDsGeert Uytterhoeven1-0/+20
Describe the two General Purpose LEDs LED7 and LED8 on the Spider CPU board, so they can be used as indicator LEDs. Note that General Purpose LEDs LED9 to LED11 are not added, as they are connected to GPIO block 4, which can only be accessed from the Control Domain. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/fdaf6c700b624851039a60733c7f73a413c6d2c5.1690447094.git.geert+renesas@glider.be
2023-07-27arm64: dts: renesas: r8a779f0: Add INTC-EX nodeGeert Uytterhoeven1-0/+15
Add the device node for the Interrupt Controller for External Devices (INTC-EX) on the Renesas R-Car S4-8 (R8A779F0) SoC, which serves external IRQ pins IRQ[0-5]. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/8f5612c0353b8c90f98366978563340d93c7ae58.1690447013.git.geert+renesas@glider.be
2023-07-27arm64: dts: renesas: rzg2ul-smarc: Add support for enabling MTU3Biju Das3-0/+30
Add support for PMOD_MTU3 macro to enable MTU3 node on RZ/G2UL SMARC EVK. The MTU3a PWM pins on PMOD0 are muxed with SPI1. Disable SPI1, when PMOD_MTU3 macro is enabled. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230727081848.100834-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-27arm64: dts: renesas: r9a07g043: Add MTU3a nodeBiju Das1-0/+70
Add MTU3a node to R9A07G043 (RZ/{G2UL,Five}) SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230727081848.100834-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-27ARM dts: renesas: armadillo800eva: Switch to enable-gpiosKrzysztof Kozlowski1-1/+1
The recommended name for enable GPIOs property in regulator-gpio is "enable-gpios". This is also required by bindings: r8a7740-armadillo800eva.dtb: regulator-vccq-sdhi0: Unevaluated properties are not allowed ('enable-gpio' was unexpected) Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230726070241.103545-1-krzysztof.kozlowski@linaro.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-27arm64: zynqmp: Describe interrupts by using macrosMichal Simek1-75/+110
Use arm-gic.h and irq.h for interrupt description. It helps to improve readability of device tree file. Suggested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/9d5bd17f37772be186cab17b06cc21351d36ff62.1688986332.git.michal.simek@amd.com
2023-07-26arm64: tegra: Adapt to LP855X bindings changesArtur Weber1-4/+2
Change underscores in ROM node names to dashes, and remove deprecated pwm-period property. Signed-off-by: Artur Weber <aweber.kernel@gmail.com> Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26arm64: tegra: Add PCIe and DP 3.3V suppliesShubhi Garg2-0/+29
Add the 3.3V supplies for PCIe C1 controller and Display Port controller for the NVIDIA IGX Orin platform. Signed-off-by: Shubhi Garg <shgarg@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26arm64: tegra: Add missing reset-names for Tegra HS UARTThierry Reding1-0/+1
The device tree bindings for the Tegra high-speed UART require the reset-names property, so add it whenever the compatible string for the serial port is overwritten. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26arm64: tegra: Remove current-speed for SBSA UARTThierry Reding3-3/+0
The SBSA UART device tree bindings don't define a current-speed property, so remove it. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26arm64: tegra: smaug: Remove reg-shift for high-speed UARTThierry Reding1-0/+1
The device tree bindings for the high-speed UART don't define a reg-shift property, so delete it. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26arm64: tegra: Remove dmas and dma-names for debug UARTThierry Reding7-0/+14
The debug UART doesn't support DMA and the DT bindings prohibit the use of the dmas and dma-names properties for it, so remove them. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26arm64: tegra: Add 35°C trip point for Jetson Orin NX/NanoThierry Reding3-3/+19
It turns out that these devices can get quite hot to the touch with the standard cooling configuration, so add another trip point at 35°C along with a cooling map to help keep the system reasonably cool at very low system load. Reviewed-by: Yi-Wei Wang <yiweiw@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26arm64: tegra: Remove duplicate PCI nodesThierry Reding1-44/+0
The PCI nodes for Jetson Orin NX are already defined at the carrier board level, so the duplicates can be dropped at the platform level. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26arm64: tegra: Sort PCI nodes correctly on OrinThierry Reding3-108/+108
Recent changes to several Orin boards didn't order some device tree nodes correctly. Resort them. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26arm64: tegra: Add audio support for IGX OrinMohan Kumar7-2014/+2170
Add audio support for the NVIDIA IGX Orin development kit having P3701 module with P3740 carrier board. Move the common device-tree nodes to a new file tegra234-p3701.dtsi and use this for Jetson AGX Orin and NVIDIA IGX Orin platforms Signed-off-by: Mohan Kumar <mkumard@nvidia.com> [treding@nvidia.com: properly sort nodes] Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-07-26dt-bindings: firmware: Add support for tegra186-bpmp DRAM MRQ GSCsPeter De Schrijver1-5/+34
Add memory-region property to the tegra186-bpmp binding to support DRAM MRQ GSCs. Co-developed-by: Stefan Kristiansson <stefank@nvidia.com> Signed-off-by: Stefan Kristiansson <stefank@nvidia.com> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Thierry Reding <treding@nvidia.com>