aboutsummaryrefslogtreecommitdiffstatshomepage
path: root/tools/perf/scripts/python/export-to-postgresql.py (unfollow)
AgeCommit message (Collapse)AuthorFilesLines
2020-07-15drm/amdgpu: enable JPEG3.0 PG and CG for navy_flounderBoyuan Zhang1-2/+4
Enable JPEG3.0 PG and CG for navy_flounder by setting up the flags to the ASIC Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: enable VCN3.0 DPG for navy_flounderBoyuan Zhang1-1/+2
Enable VCN3.0 DPG for navy_flounder by setting up the flag to the ASIC Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: enable VCN3.0 PG and CG for navy_flounderBoyuan Zhang1-2/+2
Enable VCN3.0 PG and CG for navy_flounder by setting up the flags to the ASIC Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: enable cp_fw_write_wait for navy_flounderJiansong Chen1-0/+1
It's the same with sienna_cichlid, cp fw for navy_flounder can support WAIT_REG_MEM packet. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: add vcn ip block for navy_flounderBoyuan Zhang1-0/+2
Add vcn3.0 and jpeg3.0 ip blocks for navy_flounder Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: add navy_flounder vcn firmware supportBoyuan Zhang1-0/+8
Add navy_flounder to vcn family Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu/gfx10: add gc golden setting for navy_flounderJiansong Chen1-0/+48
Add gc golden setting for navy_flounder Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdkfd: Add kfd2kgd_funcs for navy_flounder kfd supportChengming Gui1-0/+1
Add callbacks to KGD for navy flounder. Signed-off-by: Chengming Gui <Jack.Gui@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdkfd: Support navy_flounder KFDChengming Gui6-0/+24
Add KFD support for Navy Flounder. Signed-off-by: Chengming Gui <Jack.Gui@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: use front door firmware loading for navy_flounderJiansong Chen1-2/+1
Same as other navi asics. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: add psp block for navy_flounderJiansong Chen1-0/+5
Add psp and smu block for navy_flounder with psp firmware load type. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: add psp support for navy_flounderJiansong Chen2-4/+16
Currently skip ASD FW loading and ih reroute per sienna_cichlid. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: add smu block for navy_flounderJiansong Chen1-0/+3
Add SMU block for navy_flounder with direct firmware load type. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu/powerplay: add smu support for navy_flounderJiansong Chen3-1/+16
Now navy_flounder will reuse the smu11 driver_if header and ppt functions for sienna_cichlid. Later navy_flounder can maintain its own version if the compatibility is broken. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: add gmc cg support for navy_flounderJiansong Chen2-2/+5
The athub version used for navy_flounder is v2.1. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: force pa_sc_tile_steering_override to 0 for navy_flounderJiansong Chen1-1/+2
pa_sc_tile_steering_override is only programmable for gfx10.0/10.1/10.2, and navy_flounder has the same gfx10.3 IP with sienna_cichlid. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: configure navy_flounder gfx according to gfx 10.3Tao Zhou1-0/+9
The gfx version of navy_flounder is 10.3, identical to sienna_cichlid, follow the way of sienna_cichlid. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: add virtual display support for navy_flounder.Jiansong Chen1-0/+2
Virtual display support for bring up and virtualization. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: add sdma ip block for navy_flounderJiansong Chen2-2/+19
Navy_Flounder has the same sdma IP version with sienna_cichlid, and it has 2 sdma controllers. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: add gfx ip block for navy_flounderJiansong Chen2-0/+5
since navy_flounder has similar gc IP version with sienna_cichlid, follow its setting for the moment. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: add ih ip block for navy_flounderJiansong Chen2-0/+2
navy_flounder has the same osssys IP verison with sienna_cichlid, follow its setting. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: add gmc ip block for navy_flounderJiansong Chen2-6/+13
navy_flounder has similar gc IP version with sienna_cichlid, follow its setting for the moment. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: add common ip block for navy_flounderJiansong Chen1-0/+3
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: add support on mmhub for navy_flounderJiansong Chen1-0/+5
navy_flounder has the same mmhub IP version with sienna_cichlid, follow its setting. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: initialize IP offset for navy_flounderJiansong Chen1-0/+1
since navy_flounder has the same ip offset with sienna_cichlid, follow sienna_cichlid setting for the moment. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu/soc15: add support for navy_flounderJiansong Chen1-0/+7
Add soc support. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu/gfx10: add clockgating support for navy_flounderJiansong Chen1-0/+1
Same as navi10. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu/gmc10: add navy_flounder supportJiansong Chen1-0/+3
Same as navi10. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu/gfx10: add support for navy_flounder firmwareJiansong Chen1-0/+10
Declare the gfx/compute firmwares. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: set asic family and ip blocks for navy_flounderJiansong Chen1-0/+1
Add the asic family and IP blocks for navy flounder. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: set fw load type for navy_flounderJiansong Chen1-1/+2
Currently navy_flounder only supports backdoor loading type. Will switch to psp load type when psp is ready. Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: add navy_flounder gpu info firmwareJiansong Chen1-0/+4
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: add navy_flounder asic typeJiansong Chen2-0/+2
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: expand to add multiple trap event irq idHuang Rui1-26/+41
Sienna_cichlid has four sdma instances, but other chips don't. So we need expand to add multiple trap event irq id in sdma v5.2. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amd/sriov skip vcn powergating and dec_ring_testJack Zhang2-5/+20
1.Skip decode_ring test in VF, because VCN in SRIOV does not support direct register read/write. 2.Skip powergating configuration in hw fini because VCN3.0 SRIOV doesn't support powergating. V2: delete unneccessary white lines and refine implementation. Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amdgpu: correct ta header v2 ucode init start addressJohn Clements1-1/+3
resolve bug calculating fw start address within binary Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-15drm/amd/sriov porting sriov cap to vcn3.0Jack Zhang1-32/+318
1.In early_init and for sriov, hardcode harvest_config=0, enc_num=1 2.sw_init/fini alloc & free mm_table for sriov doorbell setting for sriov 3.hw_init/fini Under sriov, add start_sriov to config mmsch Skip ring_test to avoid mmio in VF, but need to initialize wptr for vcn rings. 4.Implementation for vcn_v3_0_start_sriov V2:Clean-up some uneccessary funciton declaration. Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>