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2015-05-07ARM: DT: STi: STiH418: Enable USB3 port on stih418-b2199.Peter Griffin1-0/+4
The USB3 controller is present on the b2199 board, so enable it in the board specific DT file. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-05-07ARM: DT: STi: STiH418: Add miphy28lp optional oscillator clock propertiesPeter Griffin1-0/+11
STiH418 miphy28lp port0/1 need the oscillator clock configured in the same way as on STiH407/STiH410 platforms. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-05-07ARM: DT: STi: stihxxx-b2120: Enable USB3 port on stih407-b2120 and stih410-b2120Peter Griffin1-0/+5
The USB3 controller is present on both variants of the b2120 board so enable the controller in the generic stihxxx-b2120.dtsi file. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-05-07ARM: DT: STi: STiH407: Add dwc3 usb3 DT node.Peter Griffin1-0/+27
Now that both usb2 and usb3 phy drivers, and also the ST dwc3 glue code are all present upstream, we can add the dwc3 DT node and have a working usb3 controller on stih407-b2120 and stih410-b2020. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-05-07ARM: DT: STi: STiH407: Update picophyreset for the usb3 controllers usb2 phyPeter Griffin1-1/+1
Ths picophyreset is incorrectly defined, which stops the usb2 phy being taken out of reset. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-04-30ARM: DT: STi: STiH407: Add sata DT nodes.Peter Griffin1-0/+45
Now that the miphy28lp is upstream, we can add the sata dt nodes for stih407 family silicon. This has been tested on b2120 board J4 (sata0 channel). These nodes are disabled by default as a special mini pci-e to sata daughter board is required which isn't shipped with the board. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-04-30ARM: STi: DT: STiH407: Fix retime pin mask for PIO5 and PIO35Karim BEN BELGACEM1-0/+2
This will avoid programming the retime registers when not implemented - PIO5 : no retime registers assigned to pins 6 and 7 - PIO35 : pin 7 is reserved so no retime register assigned to it Signed-off-by: Karim BEN BELGACEM <karim.ben-belgacem@st.com> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
2015-04-30ARM: STi: DT: STiH407: Add Device Tree node for the LPCLee Jones1-0/+20
On current ST platforms the LPC controls a number of functions. This patch enables support for the LPC Watchdog and LPC RTC devices on LPC1 and LPC2 respectively. Signed-off-by: David Paris <david.paris@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>