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2017-06-17bus: SIMPLE_PM_BUS does not depend on ARCH_RENESASRob Clark1-1/+0
In fact, it is needed for PCI to work on msm8996 (and probably other things). No idea why it was depending on renesas but that doesn't make any sense. So drop the dependency. Signed-off-by: Rob Clark <robdclark@gmail.com> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Arnd Bergmann <arnd@arndb.de>
2017-06-17drm/msm: Separate locking of buffer resources from struct_mutexSushmita Susheelendra17-144/+238
Buffer object specific resources like pages, domains, sg list need not be protected with struct_mutex. They can be protected with a buffer object level lock. This simplifies locking and makes it easier to avoid potential recursive locking scenarios for SVM involving mmap_sem and struct_mutex. This also removes unnecessary serialization when creating buffer objects, and also between buffer object creation and GPU command submission. Signed-off-by: Sushmita Susheelendra <ssusheel@codeaurora.org> [robclark: squash in handling new locking for shrinker] Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-06-16drm/msm/hdmi: Fix HDMI pink strip issue seen on 8x96Archit Taneja1-3/+67
A 2 pixel wide pink strip was observed on the left end of some HDMI monitors configured in a HDMI mode. It turned out that we were missing out on configuring AVI infoframes, and unlike APQ8064, the 8x96 HDMI H/W seems to be sensitive to that. Add configuration of AVI infoframes. While at it, make sure that hdmi_audio_update is only called when we've detected that the monitor supports HDMI. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-06-16drm/msm/hdmi: 8996 PLL: Populate unprepareArchit Taneja1-0/+5
Without doing anything in unprepare, the HDMI driver isn't able to switch modes successfully. Calling set_rate with a new rate results in an un-locked PLL. If we reset the PLL in unprepare, the PLL is able to lock with the new rate. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-06-16drm/msm/hdmi: Use bitwise operators when building register valuesLiviu Dudau1-3/+3
Commit c0c0d9eeeb8d ("drm/msm: hdmi audio support") uses logical OR operators to build up a value to be written in the REG_HDMI_AUDIO_INFO0 and REG_HDMI_AUDIO_INFO1 registers when it should have used bitwise operators. Signed-off-by: Liviu Dudau <liviu.dudau@arm.com> Fixes: c0c0d9eeeb8d ("drm/msm: hdmi audio support") Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-06-16drm/msm: update generated headersRob Clark15-337/+2059
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-06-16drm/msm: remove address-space idRob Clark8-46/+0
Now that the msm_gem supports an arbitrary number of vma's, we no longer need to assign an id (index) to each address space. So rip out the associated code. Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-06-16drm/msm: support for an arbitrary number of address spacesRob Clark2-43/+99
It means we have to do a list traversal where we once had an index into a table. But the list will normally have one or two entries. Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-06-16drm/msm: refactor how we handle vram carveout buffersRob Clark1-21/+27
Pull some of the logic out into msm_gem_new() (since we don't need to care about the imported-bo case), and don't defer allocating pages. The latter is generally a good idea, since if we are using VRAM carveout to allocate contiguous buffers (ie. no IOMMU), the allocation is more likely to fail. So failing at allocation time is a more sane option. Plus this simplifies things in the next patch. Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-06-16drm/msm: pass address-space to _get_iova() and friendsRob Clark17-58/+78
No functional change, that will come later. But this will make it easier to deal with dynamically created address spaces (ie. per- process pagetables for gpu). Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-06-16drm/msm/mdp4+5: move aspace/id to base classRob Clark11-40/+56
Before we can shift to passing the address-space object to _get_iova(), we need to fix a few places (dsi+fbdev) that were hard-coding the adress space id. That gets somewhat easier if we just move these to the kms base class. Prep work for next patch. Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-06-16drm/msm/mdp5: kill pipe_lockRob Clark1-10/+0
It serves no purpose, things should be sufficiently synchronized already by atomic framework. And it is somewhat awkward to be holding a spinlock when msm_gem_iova() is going to start needing to grab a mutex. Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-06-16drm/msm: fix locking inconsistency for gpu->hw_init()Rob Clark6-16/+17
Most, but not all, paths where calling the with struct_mutex held. The fast-path in msm_gem_get_iova() (plus some sub-code-paths that only run the first time) was masking this issue. So lets just always hold struct_mutex for hw_init(). And sprinkle some WARN_ON()'s and might_lock() to avoid this sort of problem in the future. Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-06-16drm/msm: Remove memptrs->wptrJordan Crouse2-4/+0
memptrs->wptr seems to be unused. Remove it to avoid confusing the upcoming preemption code. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-06-16drm/msm: Add a struct to pass configuration to msm_gpu_init()Jordan Crouse3-10/+26
The amount of information that we need to pass into msm_gpu_init() is steadily increasing, so add a new struct to stabilize the function call and make it easier to add new configuration down the line. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-06-16drm/msm: Add hint to DRM_IOCTL_MSM_GEM_INFO to return an object IOVAJordan Crouse2-4/+27
Modify the 'pad' member of struct drm_msm_gem_info to 'flags'. If the user sets 'flags' to non-zero it means that they want a IOVA for the GEM object instead of a mmap() offset. Return the iova in the 'offset' member. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> [robclark: s/hint/flags in commit msg] Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-06-16drm/msm: Remove idle function hookJordan Crouse6-11/+10
There isn't any generic code that uses ->idle so remove it. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-06-16drm/msm: Remove DRM_MSM_NUM_IOCTLSJordan Crouse2-2/+1
The ioctl array is sparsely populated but the compiler will make sure that it is sufficiently sized for all the values that we have so we can safely use ARRAY_SIZE() instead of having a constantly changing #define in the uapi header. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-06-16drm/msm: gpu: Enable zap shader for A5XXJordan Crouse5-2/+183
The A5XX GPU powers on in "secure" mode. In secure mode the GPU can only render to buffers that are marked as secure and inaccessible to the kernel and user through a series of hardware protections. In practice secure mode is used to draw things like a UI on a secure video frame. In order to switch out of secure mode the GPU executes a special shader that clears out the GMEM and other sensitve registers and then writes a register. Because the kernel can't be trusted the shader binary is signed and verified and programmed by the secure world. To do this we need to read the MDT header and the segments from the firmware location and put them in memory and present them for approval. For targets without secure support there is an out: if the secure world doesn't support secure then there are no hardware protections and we can freely write the SECVID_TRUST register from the CPU. We don't have 100% confidence that we can query the secure capabilities at run time but we have enough calls that need to go right to give us some confidence that we're at least doing something useful. Of course if we guess wrong you trigger a permissions violation which usually ends up in a system crash but thats a problem that shows up immediately. [v2: use child device per Bjorn] [v3: use generic MDT loader per Bjorn] [v4: use managed dma functions and ifdefs for the MDT loader] [v5: Add depends for QCOM_MDT_LOADER] Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> [robclark: fix Kconfig to use select instead of depends + #if IS_ENABLED()] Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-06-15drm: Reduce scope of 'state' variableDawid Kurek1-1/+2
Smaller scope reduces visibility of variable and makes usage of uninitialized variable less possible. Changes in v2: - separate declaration and initialization Changes in v3: - add missing signed-off-by tag Signed-off-by: Dawid Kurek <dawikur@gmail.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170615174556.GA8872@gmail.com
2017-06-15drm: mxsfb_crtc: Reset the eLCDIF controllerFabio Estevam1-0/+42
According to the eLCDIF initialization steps listed in the MX6SX Reference Manual the eLCDIF block reset is mandatory. Without performing the eLCDIF reset the display shows garbage content when the kernel boots. In earlier tests this issue has not been observed because the bootloader was previously showing a splash screen and the bootloader display driver does properly implement the eLCDIF reset. Add the eLCDIF reset to the driver, so that it can operate correctly independently of the bootloader. Tested on a imx6sx-sdb board. Cc: <stable@vger.kernel.org> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/1494007301-14535-1-git-send-email-fabio.estevam@nxp.com
2017-06-15drm/amdgpu: Fix compiler warningsHarish Kasiviswanathan1-4/+4
Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-06-15drm/amdgpu: vm_update_ptes remove code duplicationHarish Kasiviswanathan1-57/+16
CPU and GPU paths were mostly the same. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-06-15drm/amd/amdgpu: Port VCN over to new SOC15 macrosTom St Denis1-82/+82
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2017-06-15drm/amd/amdgpu: Port PSP v10.0 over to new SOC15 macrosTom St Denis1-7/+7
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2017-06-15drm/amd/amdgpu: Port PSP v3.1 over to new SOC15 macrosTom St Denis1-16/+16
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2017-06-15drm/amd/amdgpu: Port NBIO v7.0 driver over to new SOC15 macrosTom St Denis1-25/+17
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2017-06-15drm/amd/amdgpu: Port NBIO v6.1 driver over to new SOC15 macrosTom St Denis1-31/+23
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2017-06-15drm/amd/amdgpu: Port UVD 7.0 over to new SOC15 macrosTom St Denis1-87/+87
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2017-06-15drm/amd/amdgpu: Port MMHUB over to new SOC15 macrosTom St Denis1-14/+11
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2017-06-15drm/amd/amdgpu: Cleanup gfxhub read-modify-write patternsTom St Denis1-8/+3
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2017-06-15drm/amd/amdgpu: Port GFXHUB over to new SOC15 macrosTom St Denis1-14/+12
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2017-06-15drm/amd/amdgpu: Add offset variant to SOC15 macrosTom St Denis1-0/+14
Allows reading/writing via SOC15 macros with offset for various register banks. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2017-06-15drm/amd/powerplay: add avfs control for Vega10Eric Huang1-0/+1
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2017-06-15drm/amdgpu: add virtual display support for ravenAlex Deucher1-0/+2
Same as other asics. If enabled, exposes a user selectable number of virtual displays. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-06-15drm/amdgpu/gfx9: fix compute ring doorbell indexAlex Deucher1-1/+1
This got lost when the code was revamped. Copy/paste bug from gfx8. Reported-by: Evan Quan <evan.quan@amd.com> Fixes: 78c168342 (drm/amdgpu: allow split of queues with kfd at queue granularity v4) Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-06-15drm/amd/amdgpu: Rename KIQ ring to avoid spacesTom St Denis1-1/+1
Swap space for underscore in ring name. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-06-15drm/amd/amdgpu: gfx9 tidy ups (v2)Tom St Denis1-19/+7
A couple of simple tidy ups to register programming. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v2): Avoid using 'data' uninitialized Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-06-15drm/amdgpu: add contiguous flag in ucode bo createhorchen1-1/+2
Under VF environment, the ucode would be settled to the visible VRAM, As it would be pinned to the visible VRAM, it's better to add contiguous flag,otherwise it need to move gpu address during the pin process. This movement is not necessary. Signed-off-by: horchen <horace.chen@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-06-15drm/amdgpu: fix missed gpu info firmware when cache firmware during S3Huang Rui2-8/+13
gpu_info firmware is released after data is used. But when system enters into suspend, upper class driver will cache all firmware names. At that time, gpu_info will be failing to load. It seems an upper class issue, that we should not release gpu_info firmware until device finished. [ 903.236589] cache_firmware: amdgpu/vega10_sdma1.bin [ 903.236590] fw_set_page_data: fw-amdgpu/vega10_sdma1.bin buf=ffff88041eee10c0 data=ffffc90002561000 size=17408 [ 903.236591] cache_firmware: amdgpu/vega10_sdma1.bin ret=0 [ 903.464160] __allocate_fw_buf: fw-amdgpu/vega10_gpu_info.bin buf=ffff88041eee2c00 [ 903.471815] (NULL device *): loading /lib/firmware/updates/4.11.0-custom/amdgpu/vega10_gpu_info.bin failed with error -2 [ 903.482870] (NULL device *): loading /lib/firmware/updates/amdgpu/vega10_gpu_info.bin failed with error -2 [ 903.492716] (NULL device *): loading /lib/firmware/4.11.0-custom/amdgpu/vega10_gpu_info.bin failed with error -2 [ 903.503156] (NULL device *): direct-loading amdgpu/vega10_gpu_info.bin Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-06-15drm/amdgpu: export test ib debugfs interfaceHuang Rui1-0/+54
As Christian and David's suggestion, submit the test ib ring debug interfaces. It's useful for debugging with the command submission without VM case. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-06-15drm/amd/powerplay: add GPU power display for vega10Eric Huang1-0/+20
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-06-15drm/amd/powerplay: update vega10_ppsmc.hEric Huang1-1/+2
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-06-15drm/amdgpu: avoid to reset wave_front_size to 0Hawking Zhang1-2/+0
No need to clear it. The values are set explicitly. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-06-15drm/amdgpu: add new member in gpu_info fwHawking Zhang3-0/+11
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-06-14drm: Remove duplicate forward declarationDawid Kurek1-2/+0
Forward declarations in C are great but I'm pretty sure one is enough. Signed-off-by: Dawid Kurek <dawikur@gmail.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170614213518.GA3554@gmail.com
2017-06-14drm/panel: s6e3ha2: Add support for s6e3hf2 panel on TM2e boardHoegeun Kwon1-7/+57
This patch supports TM2e panel and the panel has 1600x2560 resolution in 5.65" physical. This identify panel type with compatibility string, also invoke display mode that matches the type. So add the check code for s6e3ha2 compatibility and s6e3hf2 type and select the drm_display_mode of default and edge type. Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com> Reviewed-by: Andrzej Hajda <a.hajda@samsung.com> Reviewed-by: Inki Dae <inki.dae@samsung.com> [treding@nvidia.com: fixup checkpatch warnings] Signed-off-by: Thierry Reding <treding@nvidia.com> Link: http://patchwork.freedesktop.org/patch/msgid/1492504836-19225-3-git-send-email-hoegeun.kwon@samsung.com
2017-06-14dt-bindings: Add support for samsung s6e3hf2 panelHoegeun Kwon1-1/+4
The samsung s6e3hf2 panel is a 5.65" 1600x2560 AMOLED panel connected using MIPI-DSI interfaces. The s6e3hf2 is add to samsung,s6e3ha2.txt binding because it is a panel similar to the s6e3ha2. So add the compatible string and comments. Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com> Reviewed-by: Andrzej Hajda <a.hajda@samsung.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com> Link: http://patchwork.freedesktop.org/patch/msgid/1492504836-19225-2-git-send-email-hoegeun.kwon@samsung.com
2017-06-14drm/panel: add backlight dependency for sitronix-st7789vArnd Bergmann1-0/+1
Without the dependency, we run into a link error: drivers/gpu/drm/panel/panel-sitronix-st7789v.o: In function `st7789v_probe': panel-sitronix-st7789v.c:(.text.st7789v_probe+0xc0): undefined reference to `of_find_backlight_by_node' Fixes: 7142afb3a186 ("drm/panel: Add driver for sitronix ST7789V LCD controller") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Hoegeun Kwon <hoegeun.kwon@samsung.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170419180326.303994-1-arnd@arndb.de
2017-06-14drm/panel: S6E3HA2 needs backlight codeArnd Bergmann1-0/+1
The new S6E3HA2 driver fails to link when backlight is disabled: ERROR: "backlight_device_register" [drivers/gpu/drm/panel/panel-samsung-s6e3ha2.ko] undefined! ERROR: "backlight_device_unregister" [drivers/gpu/drm/panel/panel-samsung-s6e3ha2.ko] undefined! This adds a Kconfig dependency like we have it for some other panel drivers. Fixes: ed29f9426d9b ("drm/panel: Add support for S6E3HA2 panel driver on TM2 board") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Hoegeun Kwon <hoegeun.kwon@samsung.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170419175939.189098-2-arnd@arndb.de
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