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2023-03-07drm/i915: Fix SKL DDI A digital port .connected()Ville Syrjälä2-4/+9
2023-03-07drm/i915: Populate dig_port->connected() before connector initVille Syrjälä1-17/+19
2023-03-07drm/i915: Bump VBT version for expected child dev size checkVille Syrjälä1-1/+1
2023-03-06drm/i915/rps: split out display rps parts to a separate fileJani Nikula4-72/+111
2023-03-06drm/i915/dmc: mass rename dev_priv to i915Jani Nikula1-85/+81
2023-03-06drm/i915/dmc: allocate dmc structure dynamicallyJani Nikula4-40/+53
2023-03-06drm/i915/dmc: add i915_to_dmc() and dmc->i915 and use themJani Nikula2-39/+56
2023-03-06drm/i915/dmc: use has_dmc_id_fw() instead of poking dmc->dmc_info directlyJani Nikula1-2/+2
2023-03-06drm/i915/power: move dc state members to struct i915_power_domainsJani Nikula6-30/+39
2023-03-06drm/i915: remove unnecessary intel_pm.h includesJani Nikula13-13/+0
2023-03-06drm/i915/pm: drop intel_suspend_hw()Jani Nikula3-19/+0
2023-03-06drm/i915/pm: drop intel_pm_setup()Jani Nikula4-8/+2
2023-03-06drm/i915/wm: remove display/ prefix from includeJani Nikula1-1/+1
2023-03-06drm/i915/display: split out DSC and DSS registersJani Nikula6-450/+465
2023-03-06drm/i915/dsi: fix DSS CTL register offsets for TGL+Jani Nikula1-3/+15
2023-03-01drm/i915/hwmon: Accept writes of value 0 to power1_max_intervalAshutosh Dixit1-5/+9
2023-03-01drm/i915/psr: Fix the delayed vblank w/aVille Syrjälä1-7/+2
2023-03-01drm/i915/vrr: Fix "window2" handlingVille Syrjälä1-8/+2
2023-03-01drm/i915: Get HDR DPCD refresh timeout from VBTVille Syrjälä3-2/+14
2023-02-27drm/i915/gen12: Update combo PHY init sequenceMatt Roper2-5/+4
2023-02-25drm/i915: Move MCR_REG define to i915_reg_defs.hLucas De Marchi2-2/+2
2023-02-24drm/i915: Remove unused tmp assignment.Rodrigo Vivi1-7/+4
2023-02-24drm/i915/dg2: Add HDMI pixel clock frequencies 267.30 and 319.89 MHzAnkit Nautiyal1-0/+62
2023-02-24drm/i915/psr: Use calculated io and fast wake linesJouni Högander2-17/+63
2023-02-23drm/i915: Drop useless intel_dp_has_audio() argumentVille Syrjälä1-3/+2
2023-02-23drm/i915: Fix audio ELD handling for DP MSTVille Syrjälä1-9/+16
2023-02-23drm/i915: Mask page table errors on gen2/3 with FBCVille Syrjälä1-2/+20
2023-02-23drm/i915: Extract {i9xx,i965)_error_mask()Ville Syrjälä1-21/+25
2023-02-23drm/i915: Dump PGTBL_ER on gen2/3/4 error interruptVille Syrjälä1-0/+6
2023-02-23drm/i915: Undo rmw damage to gen3 error interrupt handlerVille Syrjälä1-5/+5
2023-02-23drm/i915: Mark FIFO underrun disabled earlierVille Syrjälä4-18/+32
2023-02-23drm/i915/audio: Track audio state per-transcoderVille Syrjälä4-50/+48
2023-02-21drm/i915/display/power: use intel_de_rmw if possibleAndrzej Hajda2-92/+39
2023-02-20drm/i915: Remove pointless register readVille Syrjälä1-2/+2
2023-02-20drm/i915: Sprinkle some FIXMEs about TGL+ DSI transcoder timing messVille Syrjälä2-1/+7
2023-02-20drm/i915: Configure TRANS_SET_CONTEXT_LATENCY correctly on ADL+Ville Syrjälä1-3/+25
2023-02-20drm/i915/dsb: Skip DSB command buffer setup if we have no LUTsVille Syrjälä1-0/+3
2023-02-20drm/i915/dsb: Nuke the DSB debugVille Syrjälä1-5/+0
2023-02-20drm/i915/dsb: Allow vblank synchronized DSB executionVille Syrjälä3-3/+6
2023-02-20drm/i915/dsb: Define more DSB registersVille Syrjälä1-2/+48
2023-02-20drm/i915/psr: Stop clobbering TRANS_SET_CONTEXT_LATENCYVille Syrjälä1-13/+0
2023-02-17drm/i915: Define transcoder timing register bitmasksVille Syrjälä4-36/+75
2023-02-17drm/i915: Add local adjusted_mode variableVille Syrjälä1-19/+16
2023-02-17drm/i915: Define the "unmodified vblank" interrupt bitVille Syrjälä1-0/+1
2023-02-17drm/i915: Dump blanking start/endVille Syrjälä1-7/+9
2023-02-17drm/i915: s/PIPECONF/TRANSCONF/Ville Syrjälä17-198/+199
2023-02-17drm/i915: Give CPU transcoder timing registers TRANS_ prefixVille Syrjälä8-127/+129
2023-02-17drm/i915: Flatten intel_ddi_{enable,disable}_transcoder_clock()Ville Syrjälä1-19/+20
2023-02-17drm/i915: Rename intel_ddi_{enable,disable}_pipe_clock()Ville Syrjälä4-17/+17
2023-02-17drm/i915: Fix platform default aux ch for sklVille Syrjälä1-2/+12
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