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2018-12-17mmc: renesas_sdhi_internal_dmac: Whitelist r8a774c0Biju Das1-0/+1
We need r8a774c0 to be whitelisted for SDHI to work on the RZ/G2E, but we don't care about the revision of the SoC, so just whitelist the generic part number. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-12-17dt-bindings: mmc: renesas_sdhi: Add r8a774c0 supportFabrizio Castro1-0/+1
Document RZ/G2E (R8A774C0) SoC bindings. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-12-17mmc: core: Cleanup BKOPS supportUlf Hansson5-83/+21
It's been ~6 years ago since we introduced the BKOPS support for eMMC cards. The current code is a bit messy and primarily that's because it prepares to support running BKOPS in an asynchronous mode. However, that mode has never been fully implemented/enabled. Instead BKOPS is always executed in synchronously, when the card has reported an urgent BKOPS level. For these reasons, let's make the code more readable by dropping the unused parts. Let's also rename mmc_start_bkops() to mmc_run_bkops(), as to make it more descriptive. Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-12-17mmc: core: Drop redundant check in mmc_send_hpi_cmd()Ulf Hansson1-6/+0
There is no point checking if HPI is supported in mmc_send_hpi_cmd() as mmc_interrupt_hpi(), which is the only caller, already checks if HPI has been enabled. Therefore, let's drop the check and the corresponding error path. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-12-17mmc: core: Use a minimum 1600ms timeout when enabling CACHE ctrlUlf Hansson1-4/+10
Some eMMCs from Micron have been reported to need ~800 ms timeout, while enabling the CACHE ctrl after running sudden power failure tests. The needed timeout is greater than what the card specifies as its generic CMD6 timeout, through the EXT_CSD register, hence the problem. Normally we would introduce a card quirk to extend the timeout for these specific Micron cards. However, due to the rather complicated debug process needed to find out the error, let's simply use a minimum timeout of 1600ms, the double of what has been reported, for all cards when enabling CACHE ctrl. Reported-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reported-by: Andreas Dannenberg <dannenberg@ti.com> Reported-by: Faiz Abbas <faiz_abbas@ti.com> Cc: <stable@vger.kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-12-17mmc: core: Allow BKOPS and CACHE ctrl even if no HPI supportUlf Hansson1-4/+2
In commit 5320226a0512 ("mmc: core: Disable HPI for certain Hynix eMMC cards"), then intent was to prevent HPI from being used for some eMMC cards, which didn't properly support it. However, that went too far, as even BKOPS and CACHE ctrl became prevented. Let's restore those parts and allow BKOPS and CACHE ctrl even if HPI isn't supported. Fixes: 5320226a0512 ("mmc: core: Disable HPI for certain Hynix eMMC cards") Cc: Pratibhasagar V <pratibha@codeaurora.org> Cc: <stable@vger.kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-12-17mmc: core: Reset HPI enabled state during re-init and in case of errorsUlf Hansson1-1/+3
During a re-initialization of the eMMC card, we may fail to re-enable HPI. In these cases, that isn't properly reflected in the card->ext_csd.hpi_en bit, as it keeps being set. This may cause following attempts to use HPI, even if's not enabled. Let's fix this! Fixes: eb0d8f135b67 ("mmc: core: support HPI send command") Cc: <stable@vger.kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-12-17mmc: omap_hsmmc: fix DMA API warningRussell King1-1/+11
While booting with rootfs on MMC, the following warning is encountered on OMAP4430: omap-dma-engine 4a056000.dma-controller: DMA-API: mapping sg segment longer than device claims to support [len=69632] [max=65536] This is because the DMA engine has a default maximum segment size of 64K but HSMMC sets: mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; mmc->max_seg_size = mmc->max_req_size; which ends up telling the block layer that we support a maximum segment size of 65535*512, which exceeds the advertised DMA engine capabilities. Fix this by clamping the maximum segment size to the lower of the maximum request size and of the DMA engine device used for either DMA channel. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Cc: <stable@vger.kernel.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-12-17mmc: tegra: Fix for SDMMC pads autocal parsing from dtSowjanya Komatineni1-4/+4
Some of the SDMMC pads auto calibration values parsed from devicetree are assigned incorrectly. This patch fixes it. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Acked-by: Thierry Reding <treding@nvidia.com> Fixes: 51b77c8ea784 ("mmc: tegra: Program pad autocal offsets from dt") Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-12-17mmc: sdhci: Fix sdhci_do_enable_v4_modeSowjanya Komatineni1-2/+2
V4_MODE is Bit-15 of SDHCI_HOST_CONTROL2 register. Need to perform word access to this register. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Fixes: b3f80b434f72 ("mmc: sdhci: Add sd host v4 mode") Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-12-17mmc: sdhci-omap: Workaround errata regarding SDR104/HS200 tuning failures (i929)Faiz Abbas2-1/+91
Errata i929 in certain OMAP5/DRA7XX/AM57XX silicon revisions (SPRZ426D - November 2014 - Revised February 2018 [1]) mentions unexpected tuning pattern errors. A small failure band may be present in the tuning range which may be missed by the current algorithm. Furthermore, the failure bands vary with temperature leading to different optimum tuning values for different temperatures. As suggested in the related Application Report (SPRACA9B - October 2017 - Revised July 2018 [2]), tuning should be done in two stages. In stage 1, assign the optimum ratio in the maximum pass window for the current temperature. In stage 2, if the chosen value is close to the small failure band, move away from it in the appropriate direction. References: [1] http://www.ti.com/lit/pdf/sprz426 [2] http://www.ti.com/lit/pdf/SPRACA9 Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-12-17dt-bindings: sdhci-omap: Add note for cpu_thermalFaiz Abbas1-0/+2
The driver fetches a thermal zone using the string "cpu_thermal" for tuning operation. Add a note for the same. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-12-17mmc: sdhci-acpi: Disable LED control for Intel BYT-based controllersAdrian Hunter1-2/+5
Intel BYT-based controllers do not have a LED signal line. Nevertheless sdhci_led_control() takes more than twice as long as sdhci_send_command(), even though it does nothing. Use the new SDHCI_QUIRK_NO_LED quirk to disable LED control for Intel BYT-based controllers. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-12-17mmc: sdhci-pci: Disable LED control for Intel BYT-based controllersAdrian Hunter1-5/+10
Intel BYT-based controllers do not have a LED signal line. Nevertheless sdhci_led_control() takes more than twice as long as sdhci_send_command(), even though it does nothing. Use the new SDHCI_QUIRK_NO_LED quirk to disable LED control for Intel BYT-based controllers. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-12-17mmc: sdhci: Add quirk to disable LED controlAdrian Hunter2-0/+14
Host controllers may not have a LED signal line, whereas the register updates to control the non-existent LED can be relatively time consuming. Add a quirk to disable LED control. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-12-17mmc: mmci: add variant property to set command stop bitLudovic Barre2-0/+8
On cmd12 (STOP_TRANSMISSION), STM32 sdmmc variant needs to set cmdstop bit in command register. The CPSM ("Command Path State Machine") treats the command as a Stop Transmission command and signals abort to the DPSM ("Data Path State Machine"). Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-12-17misc: alcor_pci: fix spelling mistake "invailid" -> "invalid"Colin Ian King1-2/+2
There are spelling mistakes in a couple of dev_dbg messages, fix these. Signed-off-by: Colin Ian King <colin.king@canonical.com> Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-12-17mmc: meson-gx: add signal resamplingJerome Brunet1-1/+11
With some eMMC devices, there is still issues with the new phase settings. Enabling signal resampling seems to solve the problem for these. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-12-17mmc: meson-gx: align default phase on soc vendor treeJerome Brunet1-7/+1
Align the default Core and Tx phase with the SoC vendor tree. Even if the Tx phase is different from what the documentation recommends, it seems to provide better results. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-12-17mmc: meson-gx: remove useless lockJerome Brunet1-7/+0
The spinlock is only used within the irq handler so it does not seem very useful. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-12-17mmc: meson-gx: make sure the descriptor is stopped on errorsJerome Brunet1-10/+63
On errors, if we don't stop the descriptor chain, it may continue to run and raise IRQ after we have called mmc_request_done(). This is bad because we won't be able to get cmd anymore and properly deal with the IRQ. This patch makes sure the descriptor chain is stopped before calling mmc_request_done() Fixes: 79ed05e329c3 ("mmc: meson-gx: add support for descriptor chain mode") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-12-17mmc: sdhci_am654: Add Initial Support for AM654 SDHCI driverFaiz Abbas4-46/+387
The host controllers on TI's AM654 SOCs are not compatible with the phy and consumer model of the sdhci-of-arasan driver. It turns out that for optimal operation at higher speeds, a special tuning procedure needs to be implemented which involves configuration of platform specific phy registers. Therefore, branch out to a new sdhci_am654 driver and add the phy register space with all phy configurations to it. Populate AM654 specific callbacks to sdhci_ops and add SDHCI_QUIRKS wherever applicable. Only add support for upto High Speed for SD card and upto DDR52 speed mode for eMMC. Higher speeds will be added in subsequent patches. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2018-12-17dt-bindings: mmc: sdhci-of-arasan: Add deprecated message for AM65Faiz Abbas1-0/+4
Commit 26a4f38d1316 ("dt-bindings: mmc: sdhci-of-arasan: Add new compatible for AM654 MMC PHY") added a new compatible for supporting controllers on TI's AM65x SOCs. It turns out that the controller is not compatible with the arasan driver's phy and consumer model as it requires some phy registers for core sdhci functionality. This calls for the binding to branch out to a new driver. Therefore, add a deprecated message for the ti,am654-sdhci-5.1 binding. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>