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2020-07-01drm/amdgpu: make sure to reserve tmr region on all asics which support itAlex Deucher1-1/+1
This includes older APUs like renoir. Acked-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu/display: Unlock mutex on errorJohn van der Kamp1-2/+4
Make sure we pass through ret label to unlock the mutex. Signed-off-by: John van der Kamp <sjonny@suffe.me.uk> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd: fix potential memleak in err branchBernard Zhao1-0/+1
The function kobject_init_and_add alloc memory like: kobject_init_and_add->kobject_add_varg->kobject_set_name_vargs ->kvasprintf_const->kstrdup_const->kstrdup->kmalloc_track_caller ->kmalloc_slab, in err branch this memory not free. If use kmemleak, this path maybe catched. These changes are to add kobject_put in kobject_init_and_add failed branch, fix potential memleak. Signed-off-by: Bernard Zhao <bernard@vivo.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/radeon: fix fb_div check in ni_init_smc_spll_table()Denis Efremov1-1/+1
clk_s is checked twice in a row in ni_init_smc_spll_table(). fb_div should be checked instead. Fixes: 69e0b57a91ad ("drm/radeon/kms: add dpm support for cayman (v5)") Cc: stable@vger.kernel.org Signed-off-by: Denis Efremov <efremov@linux.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/powerplay: return current DCEFCLK on sysfs read (v2)Nirmoy Das2-0/+6
This fixes incorrect output when reading pp_dpm_dcefclk sysfs. Output before this patch: cat /sys/devices/pci0000:<snip>/pp_dpm_dcefclk 0: 506Mhz 1: 42949671Mhz * 2: 1266Mhz v2: squash in arcturus fix Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/powerplay: fix compilation warningNirmoy Das1-1/+1
If (smu)->ppt_funcs->intf is not initialized then smu_send_smc_msg(smu, SMU_MSG_ReadSerialNumBottom32, &bottom32) and smu_send_smc_msg(smu, SMU_MSG_ReadSerialNumTop32, &top32) will not touch bottom32 and top32. Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: 3.2.91Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Fix ineffective setting of max bpc propertyStylon Wang1-1/+2
[Why] Regression was introduced where setting max bpc property has no effect on the atomic check and final commit. It has the same effect as max bpc being stuck at 8. [How] Correctly propagate max bpc with the new connector state. Signed-off-by: Stylon Wang <stylon.wang@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: [FW Promotion] Release 1.0.19Anthony Koo1-4/+5
[Header Changes] - Add debug flag for psr to use hw locking mgr state machine Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: DP link layer test 4.2.1.1 fix due to specs updateWenjing Liu9-50/+59
[why] DP link layer CTS specs updated to change the test parameters in test 4.2.1.1. Before it requires source to delay 400us on aux no reply. With the specs updates Errata5, it requires source to delay 3.2ms (based on LTTPR aux timeout) This causes our test to fail after updating with the latest test equipment firmware. [how] the change is to allow LTTPR 3.2ms aux timeout delay by default. And set back to 400us if LTTPR feature is not enabled. We will set 3.2ms and always enable LTTPR non transparent mode if LTTPR feature is enabled and LTTPR is present. Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: allow query ddc data over aux to be read only operationWenjing Liu1-11/+18
[why] Two issues: 1. Add read only operation support for query ddc data over aux. 2. Fix a bug where if read size is multiple of 16, mot of the last read transaction will not be set to 0. Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Compare v_front_porch when checking if streams are synchronizableDavid Galiffi1-0/+4
[Why] If the front porch of the two timings differ, then there may not be enough time while both streams are in vertical blank to perform a memory clock change. This can hang the system. [How] Check the each streams timing.v_front_porch when determining if the two streams are synchronizable. Signed-off-by: David Galiffi <David.Galiffi@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: enable seamless boot for dcn30Martin Leung2-127/+126
why: seamless boots requires split of init_hw into hw and pipes to work. This was implemented in dcn10_init_hw but did not apply yet to dcn30. how: Copy over dcn10_init_hw and adapt it to dcn30 using recent changes to dcn3. Behavior will be different in init sequence. Signed-off-by: Martin Leung <martin.leung@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Red screen observed on startupPeikang Zhang1-1/+2
[Why] We try to to change new_clocks->dppclk_khz to 100000 when new_clocks->dppclk_khz is 0 [How] Don't change new_clocks->dppclk_khz value when new_clocks->dppclk_khz is 0 Signed-off-by: Peikang Zhang <peikang.zhang@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Allow 4 split on 10K 420 modesChris Park2-5/+5
[Why] 10K YCbCr420 does not need ODM 4:1, but it requires MPC 4 split indicated on the flags. [How] Make pixel encoding and resolution size specific workaround to enable ODM combine on YCbCr420 high resolution modes. Signed-off-by: Chris Park <Chris.Park@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: VSC SDP supported for SSTDerek Lai2-4/+2
[why] If a typeC to HDMI dongle supports YCbCr420 pass through and VSC colorimetry and pixel encoding formats in the Extended Receiver Capability, we shall allow VSC SDP to be used. [How] The Extended Receiver Capability field shall check the EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT bit in the TRAINING_AUX_RD_INTERVAL register. Removed DPCD rev checking for VSC SDP. Signed-off-by: Derek Lai <Derek.Lai@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Fill in dmub_srv fw_version from firmware metadataNicholas Kazlauskas1-0/+10
[Why] DMCUB firmware version is now available from firmware metadata block. We should be passing this into dmub_srv so we can know when to apply firmware version specific functionality like using CW4 only instead of the REGION4. [How] We don't have the helpers for DM to actually extract out firmware metadata block themselves. We could add that and add helpers in DM to grab this, but not every creation sequence has firmware instruction before dmub_srv_create. Easiest way to handle this is to fill this in automatically per DM in the place we do have it - when calculating the region parameters. But only fill it in if DM already hasn't in case we need to override with a specific version. We aren't do anything firmware version specific in dmub_srv_create today that does require fw_version, so while it's a little unituitive to do it when calculating region parameters it works for now. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Enable output_bpc property on all outputsStylon Wang1-1/+3
[Why] Connector property output_bpc is available on DP/eDP only. New IGT tests would benifit if this property works on HDMI. [How] Enable this read-only property on all types of connectors. Signed-off-by: Stylon Wang <stylon.wang@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Force ODM combine on 5K+ 420 modesChris Park1-0/+10
[Why] All YCbCr420 resolutions 5K and above have tiling and discoloration issues. The issue can be remedied by forcing ODM combine from 5K to 8K. 10K resolution requires ODM 4:1. The mechanism of what the real problem is, that is inherent in ODM combine programming, doesn't seem to be pointed at singular register programming (CLK, MPC, DCSURF, etc.), and needs more in-depth programming sequence review for these new use case scenarios. Until then, workaround to enable ODM combine is proposed. While it is not our policy, HW spreadsheet also recommends turning on ODM for these scenario to lower the voltage. [How] Make pixel encoding and resolution size specific workaround to enable ODM combine on YCbCr420 high resolution modes. Signed-off-by: Chris Park <Chris.Park@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: fix 4to1 odm MPC_OUT_FLOW_CONTROL_COUNTDmytro Laktyushkin1-1/+1
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: use dispclk AVFS for dppclkBrandon Syu2-5/+14
[Why] There is using pixelclk AVFS for dppclk, that would cause issue. [How] To use dispclk AVFS for both dispclk and dppclk. There would choose dppclk for request voltage when dispclk wouldn't be updated case. If dispclk need to be updated, then it'll choose the bigger one from dppclk and dispclk for request voltage. Signed-off-by: Brandon Syu <Brandon.Syu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: add mechanism to skip DCN initEric Yang10-72/+46
[Why] If optimized init is done in FW. DCN init be skipped in driver. This need to be communicated between driver and fw and maintain backwards compatibility. [How] Use DMUB scratch 0 bit 2 to indicate optimized init done in fw and use DMUB scatch 4 bit 0 to indicate drive supports the optimized flow so FW will perform it. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: fine tune logic of edid max TMDS clock checkDale Zhao2-6/+2
[WHY] Check max_tmds_clk_mhz firstly will restrict pixel clock under HDMI 1.4, thus HDMI2.0 port can't correctly support 4K 60Hz. [HOW] Fine tune the logic to check max_forum_tmds_clk_mhz firstly. Signed-off-by: Dale Zhao <dale.zhao@amd.com> Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Added local_sink null check before accessJake Wang1-2/+4
[Why & How] Need to check if local_sink is NULL before accessing. Signed-off-by: Jake Wang <haonan.wang2@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: clip plane rects in DM before passing into DCAurabindo Pillai1-0/+25
[Why] DC global validation can fail when userspace requests to draw large plane without performing the clipping themselves. This is observed in the IGT kms_plane panning tests for 4K displays where they draw an 8K plane without any clipping while expecting only the top 4K to be drawn. [How] DRM already has helpers to take care of the clipping necessary and to mark whether a plane is visible or not, so make use of these helpers in DM before passing the plane to DC. Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: 3.2.90Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: [FW Promotion] Release 1.0.18Anthony Koo1-6/+39
[Header Changes] - Update scratch information for boot status Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Correctly respond in psr enablement interfaceCamille Cho1-2/+4
[Why] dc_link_set_psr_allow_active() always returns true, even in the case that PSR is not supported. [How] Hook up the return value of dc_link_set_psr_allow_active(). Signed-off-by: Camille Cho <Camille.Cho@amd.com> Reviewed-by: Josip Pavic <Josip.Pavic@amd.com> Acked-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Fix DML failures caused by doubled stereo viewportNicholas Kazlauskas2-2/+17
[Why] Side-by-side and Top-and-bottom stereo configurations fail DML mode validation due to Viewport exceeded. This is because we consider the planes as being pipe split in pipe population so we end up doubling the viewport width, eg. from 4k to 8k. [How] These pipes technically aren't hsplit, so add a check for determining whether is_hsplit should be set. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: enable assrBhawanpreet Lakha2-0/+38
[Why] assr is content protection for eDP, in order to use it we need to call psp ta (dtm) [How] We have a enable_assr callback, hook into this and call the correct psp cmd id to enable assr. Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: implement edid max TMDS clock check in DCMichael Strauss2-0/+13
[WHY] Currently DC doesn't check requested pixel clock against an EDID specified TMDS max clock if it exists, passing modes that should fail [HOW] Add max TMDS clk to edid caps and perform check during validation Signed-off-by: Michael Strauss <michael.strauss@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: [FW Promotion] Release 1.0.17Anthony Koo1-2/+2
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Fixed using wrong eDP power sequence function pointerYi-Ling Chen1-2/+2
[why] dc->hwss->edp_backlight_control is null, it would casue it only be off main-link of eDP. It is not worng behavior for eDP power sequence off. [how] Must use hwseq->funcs.edp_backlight_control finction pointer for edp backlight. Signed-off-by: Yi-Ling Chen <Yi-Ling.Chen2@amd.com> Reviewed-by: Sung Lee <Sung.Lee@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Fix calculation of virtual channel payloadMikita Lipski2-11/+10
[why] The calculation of virtual channel payload would not take link settings in account. As we calculate VCPI slots needed both PBN for stream and also PBN per time slot. Before we would use generic PBN per time slot, which would not change with link settings causing wrong Payload allocation. [how] Provide PBN per time slot for each Virtual channel payload calculation. Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: [FW Promotion] Release 1.0.16Anthony Koo1-2/+2
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: Use dmub fw to lock pipe, cursor, digWyatt Wood8-14/+200
[Why] Hw lock manager adds the ability to lock pipe, cursor, and dig in fw. [How] Send hw lock command to fw to lock pipe, cursor, and dig. Signed-off-by: Wyatt Wood <wyatt.wood@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm amdgpu: SI UVD enabled on Verde, Tahiti, PitcairnSonny Jiang1-1/+1
Enable asic Verde, Tahiti and Pitcairn UVD block. Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm amdgpu: SI UVD enable for OlandSonny Jiang1-2/+2
Enable Oland UVD block. Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm amdgpu: SI UVD add uvd_v3_1 to makefileSonny Jiang1-1/+2
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm amdgpu: SI UVD context rreg/wregSonny Jiang1-2/+24
Implement SI uvd_ctx_rreg/wreg functions. Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm amdgpu: SI UVD v3_1 (v2)Sonny Jiang2-0/+822
Implement SI UVD. The SI UVD firmware requires validation. v2: squash in missing brace fix (Colin Ian King) Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm amdgpu: SI UVD registersSonny Jiang2-0/+902
Add SI UVD registers files. Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm amdgpu: SI UVD PACKET_TYPE0Sonny Jiang1-3/+4
Fix packet_type0 definition in sid. Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm amdgpu: SI UVD add firmwaresSonny Jiang1-0/+26
For implement UVD on SI asic, add Oland, Pitcairn, Verde, Tahiti firmwares. Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu/uvd3.x: fix register definition warningsAlex Deucher3-19/+3
drop the duplicate register macros from sid.h and use the standard ones in the oss register headers. Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amd/display: fix compilation error on allmodconfigQingqing Zhuo1-5/+1
when compiled with allmodconfig option, there are error messages as below: ERROR: modpost: "mod_color_is_table_init" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: modpost: "mod_color_get_table" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! ERROR: modpost: "mod_color_set_table_init_state" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined! To fix the issue, this commits removes CONFIG_DRM_AMD_DC_DCN guard in color/makefile. Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com> CC: Lewis Huang <Lewis.Huang@amd.com> CC: Aric Cyr <Aric.Cyr@amd.com> CC: Alexander Deucher <Alexander.Deucher@amd.com> CC: Harry Wentland <hwentlan@amd.com> CC: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> CC: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> CC: Stephen Rothwell <sfr@canb.auug.org.au> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: fix unused variableJames Zhu8-113/+102
SOC15_WAIT_ON_RREG's return value needn't always been handled by caller. new design is to fix this kind of unused variable. Signed-off-by: James Zhu <James.Zhu@amd.com> Reported-by: kernel test robot <lkp@intel.com> Acked-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: add fw release for sdma v5_0Wenhui Sheng1-1/+5
sdma fw isn't released when module exit Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Wenhui Sheng <Wenhui.Sheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: sdma v5_2 ring bo mem leakWenhui Sheng1-0/+4
invoke amdgpu_ring_fini for each sdma instance Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Wenhui Sheng <Wenhui.Sheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-07-01drm/amdgpu: remove perf level dpm in one-VFWenhui Sheng1-1/+1
On Navi12 platform, node power_dpm_force_performance_level doesn't work correctly in one-VF mode with at least three smu messages not supported: SMU_MSG_SetSoftMaxByFreq SMU_MSG_SetSoftMinByFreq SMU_MSG_TransferTableDram2Smu Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Wenhui Sheng <Wenhui.Sheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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