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2020-10-20clk: qcom: gdsc: Keep RETAIN_FF bit set if gdsc is already onStephen Boyd1-0/+8
If the GDSC is enabled out of boot but doesn't have the retain ff bit set we will get confusing results where the registers that are powered by the GDSC lose their contents on the first power off of the GDSC but thereafter they retain their contents. This is because gdsc_init() fails to make sure the RETAIN_FF bit is set when it probes the GDSC the first time and thus powering off the GDSC causes the register contents to be reset. We do set the RETAIN_FF bit the next time we power on the GDSC, see gdsc_enable(), so that subsequent GDSC power off's don't lose register contents state. Forcibly set the bit at device probe time so that the kernel's assumed view of the GDSC is consistent with the state of the hardware. This fixes a problem where the audio PLL doesn't work on sc7180 when the bootloader leaves the lpass_core_hm GDSC enabled at boot (e.g. to make a noise) but critically doesn't set the RETAIN_FF bit. Cc: Douglas Anderson <dianders@chromium.org> Cc: Taniya Das <tdas@codeaurora.org> Cc: Rajendra Nayak <rnayak@codeaurora.org> Fixes: 173722995cdb ("clk: qcom: gdsc: Add support to enable retention of GSDCR") Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20201017020137.1251319-1-sboyd@kernel.org Reviewed-by: Taniya Das <tdas@codeaurora.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: Douglas Anderson <dianders@chromium.org>
2020-10-14clk: Restrict CLK_HSDK to ARC_SOC_HSDKGeert Uytterhoeven1-1/+1
The HSDK PLL driver is only useful when building for an ARC HSDK platform. As ARC selects OF, the dependency on OF can just be replaced by a dependency on ARC_SOC_HSDK. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200807094351.1046-1-geert+renesas@glider.be Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-14clk: at91: sam9x60: support only two programmable clocksClaudiu Beznea1-1/+1
According to datasheet (Chapter 29.16.13, PMC Programmable Clock Register) there are only two programmable clocks on SAM9X60. Fixes: 01e2113de9a5 ("clk: at91: add sam9x60 pmc driver") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1602686072-28296-1-git-send-email-claudiu.beznea@microchip.com Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_ratePaul Cercueil1-0/+2
Clocks that don't have a divider are in our case all marked with the CLK_SET_RATE_PARENT flag. In this case, the .round_rate implementation should modify the value pointed to by parent_rate, in order to propagate the rate change to the parent, as explained in the documentation of clk_set_rate(). Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200903015048.3091523-5-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENTPaul Cercueil1-7/+7
The custom clocks have custom functions to round, get or set their rate. Therefore, we can't assume that they need the CLK_SET_RATE_PARENT flag. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200903015048.3091523-4-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13clk: ingenic: Don't use CLK_SET_RATE_GATE for PLLPaul Cercueil1-2/+7
CLK_SET_RATE_GATE means that the clock must be gated when being reclocked. This is not the case for the PLLs in Ingenic SoCs. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200903015048.3091523-3-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13clk: ingenic: Use readl_poll_timeout instead of custom loopPaul Cercueil1-26/+29
Use the readl_poll_timeout() function instead of rolling our own busy-wait loops. This makes the code simpler. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200903015048.3091523-2-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13clk: ingenic: Use to_clk_info() macro for all clocksPaul Cercueil1-39/+15
The to_clk_info() previously had a BUG_ON() to check that it was only called for PLL clocks. Yet, all the other clocks were doing the exact same thing the macro does, in-line. Move the to_clk_info() macro to the top of the file, remove the hardcoded BUG_ON(), and use it everywhere it makes sense. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20200903015048.3091523-1-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13clk: bcm2835: add missing release if devm_clk_hw_register failsNavid Emamdoost1-1/+3
In the implementation of bcm2835_register_pll(), the allocated pll is leaked if devm_clk_hw_register() fails to register hw. Release pll if devm_clk_hw_register() fails. Signed-off-by: Navid Emamdoost <navid.emamdoost@gmail.com> Link: https://lore.kernel.org/r/20200809231202.15811-1-navid.emamdoost@gmail.com Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13clk: at91: clk-sam9x60-pll: remove unused variableClaudiu Beznea1-2/+1
Fix variable set but not used compilation warning. Fixes: 43b1bb4a9b3e ("clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputs") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1598338751-20607-4-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13clk: at91: clk-main: update key before writing AT91_CKGR_MORClaudiu Beznea1-3/+8
SAMA5D2 datasheet specifies on chapter 33.22.8 (PMC Clock Generator Main Oscillator Register) that writing any value other than 0x37 on KEY field aborts the write operation. Use the key when selecting main clock parent. Fixes: 27cb1c2083373 ("clk: at91: rework main clk implementation") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/1598338751-20607-3-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13clk: at91: remove the checking of parent_nameClaudiu Beznea1-2/+2
There is no need to check parent_name variable while assigning it to init.parent_names. parent_name variable is already checked at the beginning of at91_clk_register_peripheral() function. Fixes: 6114067e437eb ("clk: at91: add PMC peripheral clocks") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/1598338751-20607-2-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13clk: clk-prima2: fix return value check in prima2_clk_init()Xu Wang1-1/+1
In case of error, the function clk_register() returns ERR_PTR() and never returns NULL. The NULL test in the return value check should be replaced with IS_ERR(). Signed-off-by: Xu Wang <vulab@iscas.ac.cn> Link: https://lore.kernel.org/r/20200921034522.9077-1-vulab@iscas.ac.cn Acked-by: Barry Song <baohua@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13clk: mmp2: Fix the display clock divider baseLubomir Rintel1-2/+2
The LCD clock dividers are apparently based on one. No datasheet, determined empirically, but seems to be confirmed by line 19 of lcd.fth in OLPC laptop's Open Firmware [1]: h# 00000700 value pmua-disp-clk-sel \ PLL1 / 7 -> 113.86 MHz [1] https://raw.githubusercontent.com/quozl/openfirmware/65a08a73b2cac/cpu/arm/olpc/lcd.fth Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lore.kernel.org/r/20200925233914.227786-1-lkundrak@v3.sk Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13clk: pxa: Constify static struct clk_opsRikard Falkeborn1-4/+4
Constify a couple of static struct clk_ops that are not modified. Their only usage is inside the macros and their address is passed to clk_register_composite() which takes pointers to const struct clk_ops. This allows the compiler to put them in read-only memory. Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20200922184715.1854-1-rikard.falkeborn@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13clk: baikal-t1: Mark Ethernet PLL as criticalSerge Semin1-6/+8
We've discovered that disabling the so called Ethernet PLL causes reset of the devices consuming its outgoing clock. The resets happen automatically even if each underlying clock gate is turned off. Due to that we can't disable the Ethernet PLL until the kernel is prepared for the corresponding resets. So for now just mark the PLL clock provider as critical. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Cc: linux-mips@vger.kernel.org Link: https://lore.kernel.org/r/20200920110335.18034-1-Sergey.Semin@baikalelectronics.ru Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13clk: qoriq: modify MAX_PLL_DIV to 32Zhao Qiang1-1/+1
On LS2088A, Watchdog need clk divided by 32, so modify MAX_PLL_DIV to 32 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Link: https://lore.kernel.org/r/20200916030311.17280-1-qiang.zhao@nxp.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13clk: axi-clkgen: Set power bits for fractional modeLars-Peter Clausen1-0/+7
Using the fractional dividers requires some additional power bits to be set. The fractional power bits are not documented and the current heuristic for setting them seems be insufficient for some cases. Just always set all the fractional power bits when in fractional mode. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201001085948.21412-2-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13clk: axi-clkgen: Add support for fractional dividersLars-Peter Clausen1-51/+129
The axi-clkgen has (optional) fractional dividers on the output clock divider and feedback clock divider path. Utilizing the fractional dividers allows for a better resolution of the output clock, being able to synthesize more frequencies. Rework the driver support to support the fractional register fields, both for setting a new rate as well as reading back the current rate from the hardware. For setting the rate if no perfect divider settings were found in non-fractional mode try again in fractional mode and see if better settings can be found. This appears to be the recommended mode of operation. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20201001085948.21412-1-alexandru.ardelean@analog.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13clk: qcom: Add display clock controller driver for SM8150 and SM8250Jonathan Marek3-0/+1117
Add support for the display clock controller found on SM8150 and SM8250. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> (SM8250) Link: https://lore.kernel.org/r/20200927190653.13876-3-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13dt-bindings: clock: add QCOM SM8150 and SM8250 display clock bindingsJonathan Marek3-0/+160
Add device tree bindings for display clock controller for Qualcomm Technology Inc's SM8150 and SM8250 SoCs. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> (SM8250) Link: https://lore.kernel.org/r/20200927190653.13876-2-jonathan@marek.ca Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13clk: qcom: add video clock controller driver for SM8250Jonathan Marek3-0/+379
Add support for the video clock controller found on SM8250 based devices. Derived from the downstream driver. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20200923160635.28370-6-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13clk: qcom: add video clock controller driver for SM8150Jonathan Marek3-0/+286
Add support for the video clock controller found on SM8150 based devices. Derived from the downstream driver. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20200923160635.28370-5-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13dt-bindings: clock: add SM8250 QCOM video clock bindingsJonathan Marek2-1/+37
Add device tree bindings for video clock controller for SM8250 SoCs. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200923160635.28370-4-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13dt-bindings: clock: add SM8150 QCOM video clock bindingsJonathan Marek2-1/+28
Add device tree bindings for video clock controller for SM8150 SoCs. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200923160635.28370-3-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13dt-bindings: clock: combine qcom,sdm845-videocc and qcom,sc7180-videoccJonathan Marek2-70/+9
These two bindings are almost identical, so combine them into one. This will make it easier to add the sm8150 and sm8250 videocc bindings. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200923160635.28370-2-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13clk: qcom: gcc-msm8994: Add missing clocks, resets and GDSCsKonrad Dybcio2-1/+423
This change adds GDSCs, resets and most of the missing clocks to the msm8994 GCC driver. The remaining ones are of local_vote_clk and gate_clk type, which are not yet supported upstream. Also reorder them to match the original downstream driver. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20201005145855.149206-1-konradybcio@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13clk: meson: use semicolons rather than commas to separate statementsJulia Lawall1-1/+1
Replace commas with semicolons. What is done is essentially described by the following Coccinelle semantic patch (http://coccinelle.lip6.fr/): // <smpl> @@ expression e1,e2; @@ e1 -, +; e2 ... when any // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr> Link: https://lore.kernel.org/r/1601233948-11629-11-git-send-email-Julia.Lawall@inria.fr Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13clk: mvebu: ap80x-cpu: use semicolons rather than commas to separate statementsJulia Lawall1-1/+1
Replace commas with semicolons. What is done is essentially described by the following Coccinelle semantic patch (http://coccinelle.lip6.fr/): // <smpl> @@ expression e1,e2; @@ e1 -, +; e2 ... when any // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr> Link: https://lore.kernel.org/r/1601233948-11629-10-git-send-email-Julia.Lawall@inria.fr Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13clk: uniphier: use semicolons rather than commas to separate statementsJulia Lawall2-2/+2
Replace commas with semicolons. What is done is essentially described by the following Coccinelle semantic patch (http://coccinelle.lip6.fr/): // <smpl> @@ expression e1,e2; @@ e1 -, +; e2 ... when any // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr> Link: https://lore.kernel.org/r/1601233948-11629-2-git-send-email-Julia.Lawall@inria.fr Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13clk/qcom: fix spelling typoWang Qing1-5/+5
Modify the comment typo: "compliment" -> "complement". Signed-off-by: Wang Qing <wangqing@vivo.com> Link: https://lore.kernel.org/r/1600930506-394-1-git-send-email-wangqing@vivo.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13clk: mediatek: Add MT8167 clock supportFabien Parent8-0/+1505
Add the following clock support for MT8167 SoC: topckgen, apmixedsys, infracfg, audsys, imgsys, mfgcfg, vdecsys. Signed-off-by: Fabien Parent <fparent@baylibre.com> Link: https://lore.kernel.org/r/20200918132303.2831815-2-fparent@baylibre.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-13dt-bindings: clock: mediatek: add bindings for MT8167 clocksFabien Parent8-0/+138
Add binding documentation for topckgen, apmixedsys, infracfg, audsys, imgsys, mfgcfg, vdecsys on MT8167 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200918132303.2831815-1-fparent@baylibre.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-08clk: mediatek: add UART0 clock supportHanks Chen1-0/+2
Add MT6779 UART0 clock support. Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support") Signed-off-by: Wendell Lin <wendell.lin@mediatek.com> Signed-off-by: Hanks Chen <hanks.chen@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-10-07clk: rockchip: Initialize hw to error to avoid undefined behaviorStephen Boyd1-1/+1
We can get down to this return value from ERR_CAST() without initializing hw. Set it to -ENOMEM so that we always return something sane. Fixes the following smatch warning: drivers/clk/rockchip/clk-half-divider.c:228 rockchip_clk_register_halfdiv() error: uninitialized symbol 'hw'. drivers/clk/rockchip/clk-half-divider.c:228 rockchip_clk_register_halfdiv() warn: passing zero to 'ERR_CAST' Cc: Elaine Zhang <zhangqing@rock-chips.com> Cc: Heiko Stuebner <heiko@sntech.de> Fixes: 956060a52795 ("clk: rockchip: add support for half divider") Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-23clk: tegra: Drop !provider check in tegra210_clk_emc_set_rate()Stephen Boyd1-1/+1
The provider variable is already dereferenced earlier in this function. Drop the check for NULL as it is impossible. Found with smatch drivers/clk/tegra/clk-tegra210-emc.c:131 tegra210_clk_emc_set_rate() warn: variable dereferenced before check 'provider' (see line 124) Cc: Joseph Lo <josephl@nvidia.com> Cc: Thierry Reding <treding@nvidia.com> Fixes: 0ac65fc946d3 ("clk: tegra: Implement Tegra210 EMC clock") Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20200922191641.2305144-1-sboyd@kernel.org Acked-by: Thierry Reding <treding@nvidia.com>
2020-09-22clk: ti: dra7: add missing clkctrl register for SHA2 instanceTero Kristo2-0/+2
DRA7 SoC has two SHA instances. Add the clkctrl entry for the second one. Signed-off-by: Tero Kristo <t-kristo@ti.com> Link: https://lore.kernel.org/r/20200907082600.454-4-t-kristo@ti.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-22clk: ti: clockdomain: fix static checker warningTero Kristo1-0/+2
Fix a memory leak induced by not calling clk_put after doing of_clk_get. Reported-by: Dan Murphy <dmurphy@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Link: https://lore.kernel.org/r/20200907082600.454-3-t-kristo@ti.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-22clk: ti: autoidle: add checks against NULL pointer referenceTero Kristo1-2/+12
The clk pointer passed to omap2_clk_(deny|allow)_idle can be NULL, so add checks for this. Reported-by: Dan Murphy <dmurphy@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Link: https://lore.kernel.org/r/20200907082600.454-2-t-kristo@ti.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-22clk: keystone: sci-clk: add 10% slack to set_rateTero Kristo1-1/+2
Currently, we request exact clock rates from the firmware to be set with set_rate. Due to some rounding errors and internal functionality of the firmware itself, this can fail. Thus, add some slack to the set_rate functionality so that we are always guaranteed to pass. The firmware always attempts to use frequency as close to the target freq as possible despite the slack given here. Signed-off-by: Tero Kristo <t-kristo@ti.com> Link: https://lore.kernel.org/r/20200907085740.1083-4-t-kristo@ti.com Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-22clk: keystone: sci-clk: cache results of last query rate operationTero Kristo1-0/+14
Cache results of the latest query rate operation. This optimizes the firmware interface a bit, avoiding unnecessary calls to firmware if we know the result already; the firmware interface is pretty expensive to use for query rate functionality. Signed-off-by: Tero Kristo <t-kristo@ti.com> Link: https://lore.kernel.org/r/20200907085740.1083-3-t-kristo@ti.com Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-22clk: keystone: sci-clk: fix parsing assigned-clock data during probeTero Kristo1-1/+1
The DT clock probe loop incorrectly terminates after processing "clocks" only, fix this by re-starting the loop when all entries for current DT property have been parsed. Fixes: 8e48b33f9def ("clk: keystone: sci-clk: probe clocks from DT instead of firmware") Reported-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Link: https://lore.kernel.org/r/20200907085740.1083-2-t-kristo@ti.com Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-22clk: mediatek: fix platform_no_drv_owner.cocci warningsZou Wei1-1/+0
./drivers/clk/mediatek/clk-mt6765.c:912:3-8: No need to set .owner here. The core will do it. Remove .owner field if calls are used which set it automatically Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci Fixes: 1aca9939bf72 ("clk: mediatek: Add MT6765 clock support") Signed-off-by: Zou Wei <zou_wei@huawei.com> Link: https://lore.kernel.org/r/1600761065-71353-1-git-send-email-zou_wei@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-22clk: mediatek: mt7629: simplify the return expression of mtk_infrasys_initLiu Shixin1-7/+2
Simplify the return expression. Signed-off-by: Liu Shixin <liushixin2@huawei.com> Link: https://lore.kernel.org/r/20200921082426.2591042-1-liushixin2@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-22clk: mediatek: mt6797: simplify the return expression of mtk_infrasys_initLiu Shixin1-6/+2
Simplify the return expression. Signed-off-by: Liu Shixin <liushixin2@huawei.com> Link: https://lore.kernel.org/r/20200921082425.2590990-1-liushixin2@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-22clk: socfpga: agilex: Remove unused variable 'cntr_mux'YueHaibing1-13/+0
drivers/clk/socfpga/clk-agilex.c:24:37: warning: ‘cntr_mux’ defined but not used [-Wunused-const-variable=] static const struct clk_parent_data cntr_mux[] = { ^~~~~~~~ There is no caller in tree, so can remove it. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lore.kernel.org/r/20200915020950.4688-1-yuehaibing@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-22clk: si5341: drop unused 'err' variableKrzysztof Kozlowski1-3/+1
'err' is assigned but never read: /drivers/clk/clk-si5341.c: In function ‘si5341_output_get_parent’: drivers/clk/clk-si5341.c:886:6: warning: variable ‘err’ set but not used [-Wunused-but-set-variable] Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200916161740.14173-5-krzk@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-22clk: mmp: pxa1928: drop unused 'clk' variableKrzysztof Kozlowski1-2/+1
'clk' is assigned but never read: drivers/clk/mmp/clk-of-pxa1928.c: In function ‘pxa1928_pll_init’: drivers/clk/mmp/clk-of-pxa1928.c:71:14: warning: variable ‘clk’ set but not used [-Wunused-but-set-variable] Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200916161740.14173-4-krzk@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-22clk: at91: drop unused at91sam9g45_pcr_layoutKrzysztof Kozlowski1-7/+0
The at91sam9g45_pcr_layout is not used so drop it to fix build warning: drivers/clk/at91/at91sam9g45.c:49:36: warning: 'at91sam9g45_pcr_layout' defined but not used [-Wunused-const-variable=] Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20200916161740.14173-1-krzk@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-22clk: davinci: add missing kerneldocKrzysztof Kozlowski1-0/+1
Add missing kerneldoc to fix compile warning: drivers/clk/davinci/da8xx-cfgchip.c:578: warning: Function parameter or member 'dev' not described in 'da8xx_cfgchip_register_usb1_clk48' Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: David Lechner <david@lechnology.com> Link: https://lore.kernel.org/r/20200916161740.14173-3-krzk@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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