Age | Commit message (Collapse) | Author | Files | Lines | |
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2017-11-07 | irqchip/stm32: Select GENERIC_IRQ_CHIP | 1 | -0/+1 | ||
This patch adds GENERIC_IRQ_CHIP to stm32 exti config. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> | |||||
2017-11-07 | irqchip/exiu: Add support for Socionext Synquacer EXIU controller | 3 | -0/+231 | ||
The Socionext Synquacer SoC has an external interrupt unit (EXIU) that forwards a block of 32 configurable input lines to 32 adjacent level-high type GICv3 SPIs. The EXIU has per-interrupt level/edge and polarity controls, and mask bits that keep the outgoing lines de-asserted, even though the controller may still latch interrupt conditions that occur while the line is masked. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> |