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2023-03-27Documentation/ABI: Update IFS ABI docJithu Joseph1-3/+14
Array BIST test doesn't need an IFS test image to operate unlike the SCAN test. Consequently current_batch and image_version files are not applicable for Array BIST IFS device instance, clarify this in the ABI doc. Also given that multiple tests are supported, take the opportunity to generalize descriptions wherever applicable. Signed-off-by: Jithu Joseph <jithu.joseph@intel.com> Reviewed-by: Tony Luck <tony.luck@intel.com> Link: https://lore.kernel.org/r/20230322003359.213046-10-jithu.joseph@intel.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2023-03-27platform/x86/intel/ifs: Update IFS docJithu Joseph1-11/+14
Array BIST is the second test supported by IFS. Modify IFS doc entry to be more general. Signed-off-by: Jithu Joseph <jithu.joseph@intel.com> Reviewed-by: Tony Luck <tony.luck@intel.com> Link: https://lore.kernel.org/r/20230322003359.213046-9-jithu.joseph@intel.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2023-03-27platform/x86/intel/ifs: Implement Array BIST testJithu Joseph2-0/+93
Array BIST test (for a particular core) is triggered by writing to MSR_ARRAY_BIST from one sibling of the core. This will initiate a test for all supported arrays on that CPU. Array BIST test may be aborted before completing all the arrays in the event of an interrupt or other reasons. In this case, kernel will restart the test from that point onwards. Array test will also be aborted when the test fails, in which case the test is stopped immediately without further retry. Signed-off-by: Jithu Joseph <jithu.joseph@intel.com> Reviewed-by: Tony Luck <tony.luck@intel.com> Link: https://lore.kernel.org/r/20230322003359.213046-8-jithu.joseph@intel.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2023-03-27platform/x86/intel/ifs: Sysfs interface for Array BISTJithu Joseph4-6/+24
The interface to trigger Array BIST test and obtain its result is similar to the existing scan test. The only notable difference is that, Array BIST doesn't require any test content to be loaded. So binary load related options are not needed for this test. Add sysfs interface for array BIST test, the testing support will be added by subsequent patch. Signed-off-by: Jithu Joseph <jithu.joseph@intel.com> Reviewed-by: Tony Luck <tony.luck@intel.com> Link: https://lore.kernel.org/r/20230322003359.213046-7-jithu.joseph@intel.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2023-03-27platform/x86/intel/ifs: Introduce Array Scan test to IFSJithu Joseph2-18/+50
Array BIST is a new type of core test introduced under the Intel Infield Scan (IFS) suite of tests. Emerald Rapids (EMR) is the first CPU to support Array BIST. Array BIST performs tests on some portions of the core logic such as caches and register files. These are different portions of the silicon compared to the parts tested by the first test type i.e Scan at Field (SAF). Make changes in the device driver init flow to register this new test type with the device driver framework. Each test will have its own sysfs directory (intel_ifs_0 , intel_ifs_1) under misc hierarchy to accommodate for the differences in test type and how they are initiated. Upcoming patches will add actual support. Signed-off-by: Jithu Joseph <jithu.joseph@intel.com> Reviewed-by: Tony Luck <tony.luck@intel.com> Link: https://lore.kernel.org/r/20230322003359.213046-6-jithu.joseph@intel.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2023-03-27x86/include/asm/msr-index.h: Add IFS Array test bitsJithu Joseph1-0/+2
Define MSR bitfields for enumerating support for Array BIST test. Signed-off-by: Jithu Joseph <jithu.joseph@intel.com> Reviewed-by: Tony Luck <tony.luck@intel.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Link: https://lore.kernel.org/r/20230322003359.213046-5-jithu.joseph@intel.com Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2023-03-27platform/x86/intel/ifs: IFS cleanupJithu Joseph3-12/+5
Cleanup incorporating misc review comments - Remove the subdirectory intel_ifs/0 for devicenode [1] - Make plat_ifs_groups non static and use it directly without using a function [2] Link: https://lore.kernel.org/lkml/Y+4kQOtrHt5pdsSO@kroah.com/ [1] Link: https://lore.kernel.org/lkml/Y9nyxNesVHCUXAcH@kroah.com/ [2] Signed-off-by: Jithu Joseph <jithu.joseph@intel.com> Reviewed-by: Tony Luck <tony.luck@intel.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Link: https://lore.kernel.org/r/20230322003359.213046-4-jithu.joseph@intel.com Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2023-03-27platform/x86/intel/ifs: Reorganize driver dataJithu Joseph3-12/+25
The struct holding device driver data contained both read only(ro) and read write(rw) fields. Separating ro fields from rw fields was recommended as a preferable design pattern during review[1]. Group ro fields into a separate const struct. Associate it to the miscdevice being registered by keeping its pointer in the same container struct as the miscdevice. Link: https://lore.kernel.org/lkml/Y+9H9otxLYPqMkUh@kroah.com/ [1] Signed-off-by: Jithu Joseph <jithu.joseph@intel.com> Reviewed-by: Tony Luck <tony.luck@intel.com> Link: https://lore.kernel.org/r/20230322003359.213046-3-jithu.joseph@intel.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2023-03-27platform/x86/intel/ifs: Separate ifs_pkg_auth from ifs_dataJithu Joseph3-9/+10
In preparation to supporting additional tests, remove ifs_pkg_auth from per-test scope, as it is only applicable for one test type. This will simplify ifs_init() flow when multiple tests are added. Signed-off-by: Jithu Joseph <jithu.joseph@intel.com> Reviewed-by: Tony Luck <tony.luck@intel.com> Link: https://lore.kernel.org/r/20230322003359.213046-2-jithu.joseph@intel.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2023-03-27platform/x86: Add new msi-ec driverNikita Kravets5-0/+1035
Add a new driver to allow various MSI laptops' functionalities to be controlled from userspace. This includes such features as power profiles (aka shift modes), fan speed, charge thresholds, LEDs, etc. This driver contains EC memory configurations for different firmware versions and exports battery charge thresholds to userspace (note, that start and end thresholds control the same EC parameter and are always 10% apart). Link: https://github.com/BeardOverflow/msi-ec/ Link: https://github.com/BeardOverflow/msi-ec/pull/13 Cc: Aakash Singh <mail@singhaakash.dev> Cc: Jose Angel Pastrana <japp0005@red.ujaen.es> Signed-off-by: Nikita Kravets <teackot@gmail.com> Link: https://lore.kernel.org/r/20230320225509.3559-1-teackot@gmail.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2023-03-22tools/power/x86/intel-speed-select: Update versionZhang Rui1-2/+2
Update tool and supported API version. This is the first version which supports newer Xeon platforms with TPMI support. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: subject and changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Change TRL display for Emerald RapidsSrinivas Pandruvada2-3/+21
Emerald Rapids doesn't specify TRL (Turbo Ratio Limits) based instruction types. Instead it specifies 5 TRL levels, which can be anyone of the instruction types. Increase TRL levels to 5 for Emerald Rapids. Also change display to show by level number. Show only non zero level values. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Identify Emerald RapidsSrinivas Pandruvada3-2/+12
There are some differences compared to Sapphire Rapids. So, add a separate API. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Display AMX base frequencySrinivas Pandruvada2-3/+4
AMX frequency is present in non TPMI platforms also. When platform supports, the value is non zero. So, display AMX base frequency when non zero, irrespective of platform API version. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Use cgroup v2 isolationSrinivas Pandruvada3-2/+173
On supported systems, it is possiible to isolate CPUs instead of CPU online/offline. This is optional and can be specified using -g option when running as daemon or in combination with -o option for SST-PP level change. CPU isolation doesn't isolate IRQs. So IRQs needs to be moved away from isoolated CPUs. This can be done via IRQ sysfs or irqbalance daemon. The IRQ balance daemon is also capable to parse thermal HFI messages to move IRQs away from CPUS, which are supposed be isolated. But this requires version released after July 2022. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Add missing free cpusetSrinivas Pandruvada1-1/+3
During perf level change cpuset is allocated but not freed. Add free_cpu_set() in success and failure path. Although this is not an issue, as the program will exit after processing of online/offline, but for completeness add the free_cpu_set(). Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Fix clos-max display with TPMI I/FZhang Rui1-1/+1
Comparing clos_config->clos_max with 255 is broken with TPMI I/F because of different isst_get_disp_freq_multiplier() used. Checking for clos_config->clos_max * isst_get_disp_freq_multiplier() instead. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Add cpu id checkZhang Rui2-2/+17
Some operations applies to cpu-power-domain only. Add check for cpu id for these functions. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Avoid setting duplicate tdp levelZhang Rui1-33/+46
If the new TDP level requetsted is same as the current TDP level, don't call into driver to change level. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Remove cpu mask display for non-cpu power domainZhang Rui1-21/+23
Non CPU power domains will not have any CPUs. So don't display any CPU count or enable mask. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: subject and changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Hide invalid TRL levelZhang Rui1-0/+3
TRL levels with Zero ratio values is meaningless. Prevent these TRL levels from being displayed. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Display fact info for non-cpu power domainZhang Rui1-1/+2
Allow displaying SST-TF info for non-cpu power domain. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Show level 0 name for new api_versionZhang Rui1-2/+2
level 0 name is not shown in some case for backward compatibility reason. No need to keep this quirk for new api_version. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Prevent cpu clos config for non-cpu power domainZhang Rui1-0/+6
Non-cpu power domain does not support cpu clos config. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Allow display non-cpu power domain infoZhang Rui1-2/+1
Some power domain may not have CPUs associated, allow displaying information for these non-cpu power domains. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Display amx_p1 and cooling_typeZhang Rui1-0/+14
amx_p1 and cooling_type are newly introduced for TPMI interface. Display amx_p1 and cooling_type info for platforms that support them. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Display punit infoZhang Rui1-21/+18
Display punit info for platforms with new api_version. For platforms with old api_version, don't display the punit info to be backward compatible. For example: Intel(R) Speed Select Technology Executing on CPU model:173[0xad] package-0 die-0 powerdomain-0 cpu-0 get-config-current_level:0 package-0 die-0 powerdomain-3 cpu--1 get-config-current_level:0 package-0 die-0 powerdomain-4 cpu--1 get-config-current_level:0 Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Introduce TPMI interface supportZhang Rui4-1/+794
TPMI (Topology Aware Register and PM Capsule Interface) creates a flexible, extendable and software-PCIe-driver-enumerable MMIO interface for PM features. SST feature is exposed via the TPMI interface on newer Xeon platforms. Kernel TPMI based SST driver provides a series of new IOCTLs for userspace to use. Introduce support for the platforms that do SST control via TPMI interface. Compared with previous platforms, Newer Xeons also supports multi-punit in a package/die, including cpu punit and non-cpu punit. These have already been handled in the generic code. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Get punit core mapping informationSrinivas Pandruvada1-16/+41
Get punit core mapping information using format of MSR 0x54. Based on the API version, decode is done using new format. The new format also include a power domain ID. TPMI SST information is for each power domain. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Introduce api_version helperZhang Rui2-0/+6
In some cases, the output format may be different with different api_version because of different capabilities or for backward capabilities reason. Introduce api_version() to get the api_version of the platform running. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Support large clos_min/maxZhang Rui1-2/+2
clos_min/max in TPMI interface is frequency in MHz, thus clos_min/max needs to support larger values. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Introduce is_debug_enabled()Zhang Rui2-0/+6
Platform specific code also needs to give debug output. Introduce is_debug_enabled() for this purpose. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Allow api_version based platform callbacksZhang Rui3-11/+16
Different api_version suggests different kernel driver used and different interface is used to communication with the hardware. Allow setting platform specific callbacks based on api_version. Currently, all platforms with api_version 1 uses Mbox/MMIO interfaces. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Move send_mbox_cmd to isst-core-mbox.cZhang Rui2-187/+195
After the previous cleanup, there is no user of send_mbox_cmd outside of isst-core-mbox.c. Thus move send_mbox_cmd to isst-core-mbox.c as internal functions. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Abstract adjust_uncore_freqZhang Rui4-42/+48
Allow platform specific implementation to adjust the uncore frequency. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Abstract read_pm_configZhang Rui3-14/+22
Allow platform specific implementation to get SST-CP capability and current state. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Abstract clos_associateZhang Rui3-16/+26
Allow platform specific implementation to set per core CLOS setting. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Abstract clos_get_assoc_statusZhang Rui3-17/+24
Allow platform specific implementation to get per core CLOS setting. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Abstract set_closZhang Rui3-20/+28
Allow platform specific implementation to set CLOS priority setting. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Abstract pm_get_closZhang Rui3-15/+23
Allow platform specific implementation to get CLOS priority setting. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Abstract pm_qos_configZhang Rui3-84/+93
Allow platform specific implementation to set CLOS config settings. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Abstract get_clos_informationZhang Rui3-21/+28
Allow platform specific implementation to get CLOS config setting. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Abstract get_get_trlsZhang Rui3-8/+24
Allow platform specific implementation to get turbo ratio limits of each AVX level, for a selected SST-PP level. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Enhance get_tdp_infoZhang Rui2-59/+60
mbox_get_uncore_p0_p1_info/get_p1_info/get_uncore_mem_freq can be done inside get_tdp_info(). Fold the code into get_tdp_info(). No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Abstract get_uncore_p0_p1_infoZhang Rui3-42/+50
Allow platform specific implementation to get uncore frequency info. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Abstract get_fact_infoZhang Rui3-87/+96
Allow platform specific implementation to get SST-TF info. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Abstract set_pbf_fact_statusZhang Rui3-47/+55
Allow platform specific implementation to enable/disable SST-TF/BF. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Remove isst_get_pbf_info_completeZhang Rui3-7/+1
isst_get_pbf_info_complete does nothing but just free the core_mask. Remove the function and do free core_mask directly and free core mask in the caller. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Abstract get_pbf_infoZhang Rui3-61/+72
Allow platform specific implementation to get SST-BF information. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
2023-03-22tools/power/x86/intel-speed-select: Abstract set_tdp_levelZhang Rui3-18/+26
Allow platform specific implementation to set a SST-PP level. No functional changes are expected. Signed-off-by: Zhang Rui <rui.zhang@intel.com> [srinivas.pandruvada@linux.intel.com: changelog edits] Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
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