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2018-12-11drm/nouveau/devinit/tu106: initial supportBen Skeggs1-0/+1
Appears to be compatible with TU104. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/bios/tu106: initial supportBen Skeggs1-0/+1
No real surprised here so far. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/pci/tu106: initial supportBen Skeggs1-0/+1
Appears to be compatible with GP100. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/core: recognise TU106Ben Skeggs1-0/+6
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/core: increase maximum number of nvdec instances to 3Ben Skeggs3-3/+7
RTX2070 appears to have 3 copies of the engine. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/kms/tu104: initial supportBen Skeggs15-19/+457
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/ce/tu104: initial supportBen Skeggs6-0/+50
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/fifo/tu104: initial supportBen Skeggs14-9/+279
Various different bits and pieces vs GV100. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/disp/tu104: initial supportBen Skeggs13-8/+333
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/dma/tu104: initial supportBen Skeggs1-0/+1
Appears to be compatible with GV100. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/therm/tu104: initial supportBen Skeggs1-0/+1
Appears to be compatible with GP100. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/pmu/tu104: initial supportBen Skeggs1-0/+1
Appears to be compatible with GP102. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/fault/tu104: initial supportBen Skeggs6-1/+173
New registers. Currently uncertain how exactly to mask fault buffer interrupts. This will likely be corrected at around the same time as the new MC interrupt stuff has been properly figured out and implemented. For the moment, it shouldn't matter too much. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/bar/tu104: initial supportBen Skeggs4-0/+101
New registers. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/mmu/tu104: initial supportBen Skeggs6-0/+129
New flush method. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/ltc/tu104: initial supportBen Skeggs1-0/+1
Appears to be compatible with GP102. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/fb/tu104: initial supportBen Skeggs1-0/+1
Appears to be compatible with GV100. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/imem/tu104: initial supportBen Skeggs1-0/+1
Appears to be compatible with NV50. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/tmr/tu104: initial supportBen Skeggs1-0/+1
Appears to be compatible with GK20A. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/bus/tu104: initial supportBen Skeggs1-0/+1
Appears to be compatible with GF100. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/mc/tu104: initial supportBen Skeggs6-0/+62
Things are a bit different here on Turing, and will require further changes yet once I've investigated them more thoroughly. For now though, the existing GP100 code is compatible enough with one small hack to forward on fault buffer interrupts. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/fuse/tu104: initial supportBen Skeggs1-0/+1
Appears to be compatible with GM107. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/i2c/tu104: initial supportBen Skeggs1-0/+1
Appears to be compatible with GM200. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/gpio/tu104: initial supportBen Skeggs1-0/+1
Appears to be compatible with GK104. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/ibus/tu104: initial supportBen Skeggs1-0/+1
Appears to be compatible with GM200. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/top/tu104: initial supportBen Skeggs1-0/+1
Appears to be compatible with GK104. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/devinit/tu104: initial supportBen Skeggs4-0/+92
The GPU executes DEVINIT itself now, which makes our lives a bit easier. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/bios/tu104: initial supportBen Skeggs1-0/+1
No real surprises here so far. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/pci/tu104: initial supportBen Skeggs1-0/+1
Appears to be compatible with GP100. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/core: recognise TU104Ben Skeggs4-0/+10
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/kms/nv50-: allow more flexibility with lut formatsBen Skeggs13-42/+77
Will be required for Turing. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau: remove left-over struct memberBen Skeggs1-1/+0
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/fifo/gv100: return work submission token in channel ctor argsBen Skeggs8-13/+63
The token will also contain runlist ID on Turing, so instead expose it as an opaque value from NVKM so the client doesn't need to care. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/fifo/gv100: allocate method bufferBen Skeggs3-3/+22
The GPU saves off some stuff to the address specified in this part of RAMFC when the channel faults, so we should probably point it at a valid address. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/fifo/gm200-: read pbdma count more directlyBen Skeggs8-8/+36
The trick we used (and still use for older GPUs) doesn't work on Turing. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/fifo/gk104-: virtualise pbdma enable functionBen Skeggs3-1/+12
Turing will require different code. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/fifo/gk104-: group pbdma functions togetherBen Skeggs11-13/+28
We're about to be adding more of them. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/fifo/gk104-: separate runlist building from committing to hwBen Skeggs6-25/+41
We will need to bash different registers on Turing. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/fifo/gk104-: support enabling privileged ce functionsBen Skeggs7-17/+28
Will be used by SVM code to allow direct (without going through MMU) memcpy using the GPU copy engines. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/fifo/gk104-: return channel instance in ctor argsBen Skeggs5-6/+14
Will be used to match fault buffer entries with a channel. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/fifo/gf100-: call into BAR to reset BARs after MMU faultBen Skeggs4-4/+26
This is needed for Turing, but we're supposed to wait for completion after re-writing the value on older GPUs anyway. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/disp/gv100: fix name of window channels in debug outputBen Skeggs1-1/+1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/mmu: add more general vmm free/node handling functionsBen Skeggs3-51/+118
Aside from being a nice cleanup, these will to allow the upcoming direct page mapping interfaces to play nicely with normal mappings. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/fault: add explicit control over fault buffer interruptsBen Skeggs4-8/+29
The GPU will continually fire interrupts while a fault buffer GET != PUT, and to stop the spurious interrupts while the handler does its thing, we were disabling the fault buffer temporarily. This is not actually a great idea to begin with, and made worse by Volta resetting GET/PUT when it's reactivated. So, let's not do that. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/fault: store get/put pri address in nvkm_fault_bufferBen Skeggs4-14/+21
Will allow more shared fault buffer handling code between Pascal/Volta. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/fault: remove manual mapping of fault buffers into BAR2Ben Skeggs4-17/+10
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/imem/nv50: support pinning objects in BAR2 and returning addressBen Skeggs2-1/+17
Various structures are accessed by the GPU through BAR2 for some reason on newer GPUs. This commit makes it more convenient to handle. Will be used for GP100- fault buffers, and GV100- fault method buffers. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/tmr: detect stalled gpu timer and break out of waitsBen Skeggs2-10/+54
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/devinit/gm200-: export function to upload+execute PMU/PRE_OSBen Skeggs2-4/+11
Will be used for Turing. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-12-11drm/nouveau/bios: translate USB-C connector typeBen Skeggs2-1/+3
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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