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2019-11-22dmaengine: sf-pdma: replace /** with /* for non-function commentGreen Wan2-2/+2
There are several comments starting from "/**" but not for function comment purpose. It causes kernel-doc parsing wrong string. Replace "/**" with "/*" to fix them. Signed-off-by: Green Wan <green.wan@sifive.com> Link: https://lore.kernel.org/r/20191118143554.16129-1-green.wan@sifive.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-11-22dmaengine: ti: edma: fix missed failure handlingChuhong Yuan1-2/+4
When devm_kcalloc fails, it forgets to call edma_free_slot. Replace direct return with failure handler to fix it. Fixes: 1be5336bc7ba ("dmaengine: edma: New device tree binding") Signed-off-by: Chuhong Yuan <hslester96@gmail.com> Link: https://lore.kernel.org/r/20191118073802.28424-1-hslester96@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-11-22dmaengine: mmp_pdma: add missed of_dma_controller_freeChuhong Yuan1-0/+2
The driver calls of_dma_controller_register in probe but does not free it in remove. Add the call to fix it. Signed-off-by: Chuhong Yuan <hslester96@gmail.com> Link: https://lore.kernel.org/r/20191115083153.12334-1-hslester96@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-11-22dmaengine: mmp_tdma: add missed of_dma_controller_freeChuhong Yuan1-0/+3
The driver calls of_dma_controller_register in probe but does not free it in remove. Add the call to fix it. Signed-off-by: Chuhong Yuan <hslester96@gmail.com> Link: https://lore.kernel.org/r/20191115083100.12220-1-hslester96@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-11-14dmaengine: sprd: Add wrap address support for link-list modeEric Long2-0/+17
The Spreadtrum Audio compress offload mode will use 2-stage DMA transfer to save power. That means we can request 2 dma channels, one for source channel, and another one for destination channel. Once the source channel's transaction is done, it will trigger the destination channel's transaction automatically by hardware signal. In this case, the source channel will transfer data from IRAM buffer to the DSP fifo to decoding/encoding, once IRAM buffer is empty by transferring done, the destination channel will start to transfer data from DDR buffer to IRAM buffer. Since the destination channel will use link-list mode to fill the IRAM data, and IRAM buffer is allocated by 32K, and DDR buffer is larger to 2M, that means we need lots of link-list nodes to do a cyclic transfer, instead wasting lots of link-list memory, we can use wrap address support to reduce link-list node number, which means when the transfer address reaches the wrap address, the transfer address will jump to the wrap_to address specified by wrap_to register, and only 2 link-list nodes can do a cyclic transfer to transfer data from DDR to IRAM. Thus this patch adds wrap address to support this case. [Baolin Wang changes the commit message] Signed-off-by: Eric Long <eric.long@unisoc.com> Signed-off-by: Baolin Wang <baolin.wang@linaro.org> Link: https://lore.kernel.org/r/85a5484bc1f3dd53ce6f92700ad8b35f30a0b096.1571812029.git.baolin.wang@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-11-14MAINTAINERS: Add Green as SiFive PDMA driver maintainerGreen Wan1-0/+6
Update MAINTAINERS for SiFive PDMA driver. Signed-off-by: Green Wan <green.wan@sifive.com> Link: https://lore.kernel.org/r/20191107084955.7580-5-green.wan@sifive.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2019-11-14dmaengine: sf-pdma: add platform DMA support for HiFive Unleashed A00Green Wan6-0/+753
Add PDMA driver, sf-pdma, to enable DMA engine on HiFive Unleashed Rev A00 board. - Implement dmaengine APIs, support MEM_TO_MEM async copy. - Tested by DMA Test client - Supports 4 channels DMA, each channel has 1 done and 1 err interrupt connected to platform-level interrupt controller (PLIC). - Depends on DMA_ENGINE and DMA_VIRTUAL_CHANNELS The datasheet is here: https://static.dev.sifive.com/FU540-C000-v1.0.pdf Follow the DMAengine controller doc, "./Documentation/driver-api/dmaengine/provider.rst" to implement DMA engine. And use the dma test client in doc, "./Documentation/driver-api/dmaengine/dmatest.rst", to test. Each DMA channel has separate HW regs and support done and error ISRs. 4 channels share 1 done and 1 err ISRs. There's no expander/arbitrator in DMA HW. ------ ------ | |--< done 23 >--|ch 0| | |--< err 24 >--| | (dma0chan0) | | ------ | | ------ | |--< done 25 >--|ch 1| | |--< err 26 >--| | (dma0chan1) |PLIC| ------ | | ------ | |--< done 27 >--|ch 2| | |--< err 28 >--| | (dma0chan2) | | ------ | | ------ | |--< done 29 >--|ch 3| | |--< err 30 >--| | (dma0chan3) ------ ------ Signed-off-by: Green Wan <green.wan@sifive.com> Link: https://lore.kernel.org/r/20191107084955.7580-4-green.wan@sifive.com Signed-off-by: Vinod Koul <vkoul@kernel.org>