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2015-06-08ASoC: tas2552: Update DT binding document regarding clock configurationPeter Ujfalusi1-0/+6
Add overview of tas2552's clock configuration and selection. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-08ASoC: tas2552: Use consistent name for 'struct tas2552_data'Peter Ujfalusi1-3/+3
In tas2552_sw_shutdown() tas_data is used while the rest of the driver uses tas2552 when dealing with the 'struct tas2552_data' Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-08ASoC: tas2552: Remove unneeded semicolonPeter Ujfalusi1-1/+1
Double semicolon was added by the following commit: ea178d1456dc ASoC: tas2552: Make the enable-gpio really optional Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-08ASoC: tas2552: Call pm_runtime_disable when the module is removedPeter Ujfalusi1-0/+1
The module can not be loaded again after it has been removed. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-08ASoC: tas2552: Code, define alignment changes for uniformityPeter Ujfalusi2-7/+7
Align the numbers in the header file to the same column. At the same time change the wrapping of CFG_2 register write in the probe function to be uniform with the other calls. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-08ASoC: tas2552: Correct Boost Auto-Pass Through Control register usagePeter Ujfalusi2-14/+13
Correct the bit definition so the code will change the bits what it supposed to change. Also rename the register define to TAS2552_BOOST_APT_CTRL. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-08ASoC: tas2552: Correct Output Data register usagePeter Ujfalusi2-6/+18
Do not write to DOUT Tristate register at probe time, specially not write data which is defined to be used in Output Data Register. Fix the defines for the Output Data Register and correct the register write at probe time. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-08ASoC: tas2552: Add control for selecting DIN sourcePeter Ujfalusi1-0/+11
'DIN source' enum can be used to select the DIN Source (muted, left, right or average of left and right channels). Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-08ASoC: tas2552: Correct the PLL configurationPeter Ujfalusi2-54/+95
Do not restrict the sampling rate to 44.1/48KHz. The pll_clk clock should be (sampling rate * 512) in all cases. Correct the J.D calculation (the D part was incorrectly calculated). Restore PLL enable status after we are done with the configuration. Implement hardware constraint handling towards the pll_clkin: if D != 0 (in J.D) then 1.1MHz <= pll_clkin <= 9.2MHz needs to be checked. If the PLL setup does not met with this constraint, fall back to BCLK as reference clock, if BCLK fails, use the internal 1.8MHz clock. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-05ASoC: tas2552: Configure the WCLK frequency based on the streamPeter Ujfalusi2-21/+59
Instead of hard wiring the WCLK frequency at probe time do it runtime. The hard wired 88_96KHz was not even setting the correct bits since it was defined as (1 << 6) which will change the I2S_OUT_SEL bit and will leave the amplifier configured for 8KHz. At the same time clean up and fix the CFG3 register bits. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-05ASoC: tas2552: Add support for word length configurationPeter Ujfalusi2-0/+48
Configure the word length based on the params_width of the stream. Also configure the clock per frame value which is used when tas2552 is bus master. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-05ASoC: tas2552: Implement startup/stop sequence as per TRMPeter Ujfalusi1-16/+28
Certain sequence need to be followed in order to have smooth power up and power down performance. Execute this sequence via DAPM_POST widget. Remove patching the RESERVED_0D register at probe time since it has to be handled every time when we stop or start the amplifier. In order to be able to execute the sequence at the correct time, the driver need to request to ignore the pmdown time. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-05ASoC: tas2552: Correct the Speaker Driver Playback Volume (PGA_GAIN)Peter Ujfalusi1-2/+2
The last parameter for DECLARE_TLV_DB_SCALE() is to tell if the gain will be muted or not when it is set to raw 0. IN this case it is not muted. The PGA_GAIN is in 0-4 bits in the register. Fix the offset in the SOC_SINGLE_TLV() for this. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-05ASoC: tas2552: Clean up the Digital - Analog DAPM route definitionPeter Ujfalusi1-8/+6
The strings should be: 'static const char * const tas2552_input_texts[]' SOC_DAPM_ENUM should have "Route" in place of xname and no need to have it as an array. Also align the parameters. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-05ASoC: tas2552: Add TDM supportPeter Ujfalusi2-4/+58
TDM support is achieved using DSP transfer mode and setting a programmable offset which specifies where data begins with respect to the frame sync. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-05ASoC: tas2552: Correct and clean up data format and BCLK/WCLK directionPeter Ujfalusi2-18/+17
Use names from the datasheet for the definitions. Correct the data format definitions since they were not correct. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-05ASoC: tas2552: Correct dai format supportPeter Ujfalusi1-14/+15
DSP_A mode require one bit delay from the FS, DSP_B is without data delay. When checking the requested format, also match the bit and fs inversion flag along with the format since it is not possible to change inversion. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-06-05ASoC: tas2552: Add support for pll and pdm source clock selectionPeter Ujfalusi1-4/+29
Instead of hard wiring the PLL_CLKIN and PDM_CLK to be sourced from BCLK add proper clock configuration via the set_dai_sysclk callback. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@kernel.org>