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2018-10-16clk: ti: Prepare for remove of OF node nameStephen Boyd1-6/+3
Another patch is going to change this code to use %pOFn for DT node names. Fix up the code to make this easy to pick this side of the merge instead of fixing it up in a merge commit later. Cc: Tero Kristo <t-kristo@ti.com> Cc: Rob Herring <robh+dt@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-11clk: Clean up suspend/resume coding styleStephen Boyd1-20/+22
The normal style is to use 'core' for struct clk_core pointers and to directly access the core pointer from the clk_hw pointer when we're within the common clk framework. Update the patches to make it a bit easier to handle. Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-07clk: keystone: add missing MODULE_LICENSEArnd Bergmann2-0/+10
A randconfig build showed that two clk modules have no license tag: WARNING: modpost: missing MODULE_LICENSE() in drivers/clk/keystone/gate.o see include/linux/module.h for more information WARNING: modpost: missing MODULE_LICENSE() in drivers/clk/keystone/pll.o see include/linux/module.h for more information Add the appropriate information from the comment at the start of the two files. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Santosh Shilimkar <ssantosh@krenel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-03clk: ti: Add functions to save/restore clk contextRuss Dill7-0/+206
SoCs like AM43XX lose clock registers context during RTC-only suspend. Hence add functions to save/restore the clock registers context. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Russ Dill <Russ.Dill@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2018-10-03clk: clk: Add clk_gate_restore_context functionKeerthy2-0/+21
The clock gate restore context function enables or disables the gate clocks based on the enable_count. This is done in cases where the clock context is lost and based on the enable_count the clock either needs to be enabled/disabled. Signed-off-by: Keerthy <j-keerthy@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2018-10-03clk: Add functions to save/restore clock context en-masseRuss Dill3-0/+106
Deep enough power saving mode can result into losing context of the clock registers also, and they need to be restored once coming back from the power saving mode. Hence add functions to save/restore clock context. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Russ Dill <Russ.Dill@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
2018-10-03clk: ti: dra7: add new clkctrl dataTero Kristo3-3/+874
The new clkctrl data layout for dra7xx is split based on clockdomain boundaries. Previously the split was based on CM boundaries. This patch adds the new data as separate data entity, retaining the compatibility data also for now. The compatibility data can be removed once no longer needed. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com>
2018-10-03clk: ti: dra7xx: rename existing clkctrl data as compat dataTero Kristo5-804/+829
Rename the existing clkctrl data in preparation of upcoming clkdm based split for it. Once the DT data has transitioned also, the compat data can be removed. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com>
2018-10-03clk: ti: am43xx: add new clkctrl data for am43xxTero Kristo3-5/+268
The new clkctrl data layout for am43xx is split based on clockdomain boundaries. Previously the split was based on CM boundaries. This patch adds the new data as separate data entity, retaining the compatibility data also for now. The compatibility data can be removed once no longer needed. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com>
2018-10-03clk: ti: am43xx: rename existing clkctrl data as compat dataTero Kristo5-207/+233
Rename the existing clkctrl data in preparation of upcoming clkdm based split for it. Once the DT data has transitioned also, the compat data can be removed. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com>
2018-10-03clk: ti: am33xx: add new clkctrl data for am33xxTero Kristo3-3/+250
The new clkctrl data layout for am33xx is split based on clockdomain boundaries. Previously the split was based on CM boundaries. This patch adds the new data as separate data entity, retaining the compatibility data also for now. The compatibility data can be removed once no longer needed. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com>
2018-10-03clk: ti: am33xx: rename existing clkctrl data as compat dataTero Kristo5-198/+224
Rename the existing clkctrl data in preparation of upcoming clkdm based split for it. Once the DT data has transitioned also, the compat data can be removed. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com>
2018-10-03clk: ti: clkctrl: replace dashes from clkdm name with underscoreTero Kristo1-0/+10
The change in the DTS data node naming prevents using underscore within the node names and force usage of dash instead. On the other hand, clockdomains use underscore instead of dash, so this must be replaced within the driver code so that the mapping between the two can be done properly. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com>
2018-10-03clk: ti: clkctrl: support multiple clkctrl nodes under a cm nodeTero Kristo4-18/+53
Currently, only one clkctrl node can be added under a specific CM node due to limitation with the implementation. Modify the code to pick-up clockdomain name from the clkctrl node instead of CM node if provided. Also, add a new flag to the TI clock driver so that both modes can be supported simultaneously. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com>
2018-10-03dt-bindings: clock: dra7xx: add clkctrl indices for new data layoutTero Kristo1-68/+258
The new data layout will be split based on clockdomain boundaries, instead of CM boundaries. This introduces a few new clkctrl providers, that have different indices for the clkctrl data. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com>
2018-10-03dt-bindings: clock: am43xx: add clkctrl indices for new data layoutTero Kristo1-0/+132
The new data layout will be split based on clockdomain boundaries, instead of CM boundaries. This introduces a few new clkctrl providers, that have different indices for the clkctrl data. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com>
2018-10-03dt-bindings: clock: am33xx: add clkctrl indices for new data layoutTero Kristo1-0/+119
The new data layout will be split based on clockdomain boundaries, instead of CM boundaries. This introduces a few new clkctrl providers, that have different indices for the clkctrl data. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com>
2018-10-02clk: keystone: Enable TISCI clocks if K3_ARCHNishanth Menon2-1/+2
K3_ARCH uses TISCI for clocks as well. Enable the same for the driver support. Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-02clk: davinci: kill davinci_clk_reset_assert/deassert()Bartosz Golaszewski2-39/+0
This code is no longer used. Remove it. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Reviewed-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-01clk: mvebu: ap806: Remove superfluous of_clk_add_providerGregory CLEMENT1-1/+0
While applying the commit a8309cedcdce ("clk: apn806: Add eMMC clock to system controller driver"), of_clk_add_provider was added wheres it was already present in the probe function. This extraneous call is harmless but not useful so remove it. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-10-01clk: mvebu: use SPDX-License-IdentifierGregory CLEMENT17-52/+17
Convert the remaining files to SPDX license description. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-09-28clk: renesas: Convert to SPDX identifiersKuninori Morimoto22-95/+27
This patch updates license to use SPDX-License-Identifier instead of verbose license text. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> [rebased against clk-spdx] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-09-28clk: renesas: r7s9210: Add SPI clocksChris Brandt1-0/+3
Add RSPI clocks for RZ/A2. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-26clk: renesas: r7s9210: Move table update to separate functionChris Brandt1-45/+50
Same functionality, just easier to read. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-26clk: renesas: r7s9210: Convert some clocks to earlyChris Brandt1-6/+26
The OSTM timer driver for RZ/A2 uses TIMER_OF_DECLARE which requires the ostm module clocks to be registers early in boot. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-26clk: renesas: cpg-mssr: Add early clock supportChris Brandt2-21/+89
Add support for SoCs that need to register core and module clocks early in order to use OF drivers that exclusively use macros such as TIMER_OF_DECLARE. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-26clk: meson: meson8b: use the regmap in the internal reset controllerMartin Blumenstingl1-7/+6
For now the reset controller was using raw register access because the early init did not initialize the regmap. However, now that clocks are initialized early we can simply use the regmap also for the reset controller. No functional changes. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-09-26clk: meson: meson8b: register the clock controller earlyMartin Blumenstingl1-60/+34
Until now only the reset controller (part of the clock controller register space) was registered early in the boot process, while the clock controller itself was registered later on. However, some parts of the SoC are initialized early in the boot process, such as the SRAM and the TWD timer. The bootloader already enables these clocks so we didn't see any issues so far. Register the clock controller early so other drivers (such as the SRAM and TWD timer) can use the clocks early in the boot process. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-09-26clk: meson-axg: pcie: drop the mpll3 clock parentYixun Lan1-2/+4
We found the PCIe driver doesn't really work with the mpll3 clock which is actually reserved for debug, So drop it from the mux list. Fixes: 33b89db68236 ("clk: meson-axg: add clocks required by pcie driver") Tested-by: Jianxin Qin <jianxin.qin@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-09-26clk: meson: axg: round audio system master clocks downJerome Brunet1-11/+23
Some of the master clocks provided by the axg audio clock controller are system clock (spdifin and pdm sysclk). They are used to clock an internal DSP of the related devices. Having them constantly rounded down instead of closest is preferable. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-09-26clk: meson: clk-pll: drop hard-coded rates from pll tablesJerome Brunet5-142/+162
Putting hard-coded rates inside the parameter tables assumes that the parent is known and will never change. That's a big assumption we should not make. We have everything we need to recalculate the output rate using the parent rate and the rest of the parameters. Let's do so and drop the rates from the tables. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-09-26clk: meson: clk-pll: remove od parametersJerome Brunet8-498/+493
Remove od parameters from pll clocks and add post dividers clocks instead. Some clock, especially the one which feature several ods, may provide output between those ods. Also, some drivers, such as the hdmi driver, may require a more detailed control of the clock dividers, compared to what CCF would perform automatically. One added benefit of removing ods is that it also greatly reduce the size of the rate parameter tables. In the future, we could possibly take the predivider 'n' out of this driver as well. To do so, we will need to understand the constraints for the PLL to lock and whether or not it depends on the input clock rate. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-09-26clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessaryJerome Brunet3-8/+8
CLK_GET_RATE_NOCACHE should only be necessary when the registers controlling the rate of clock may change outside of CCF. On Amlogic, it should only be the case for the hdmi pll which is directly controlled by the display driver (WIP to fix this). The other plls should not require this flag. Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-09-26clk: meson: clk-pll: add enable bitJerome Brunet5-10/+113
Add the enable the bit of the pll clocks. These pll clocks may be disabled but we can't model this as an external gate since the pll needs to lock when enabled. Adding this bit allows to drop the poke of the first register of PLL. This will be useful to model the different components of the pll using generic clocks elements Acked-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-09-25clk: renesas: r8a77970: Add TPU clockSergei Shtylyov1-0/+1
The TPU0 clock wasn't present in the original R8A77970 patch by Daisuke Matsushita, it was added in a later BSP version... Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-25clk: renesas: r8a77990: Fix incorrect PLL0 divider in commentGeert Uytterhoeven1-2/+2
PLL0 runs at 4.8 GHz, i.e. EXTAL x 100. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-19dt-bindings: clock: renesas: cpg-mssr: Document r8a774c0Fabrizio Castro1-2/+4
This patch documents RZ/G2E (a.k.a. R8A774C0) bindings for the Clock Pulse Generator driver. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-19clk: renesas: cpg-mssr: Add r8a774c0 supportFabrizio Castro5-0/+299
Add RZ/G2E (R8A774C0) Clock Pulse Generator / Module Standby and Software Reset support. Based on Table 8.2g of "RZ/G Series, 2nd Generation User's Manual: Hardware (Rev. 0.61, June 12, 2018)". Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>