wireguard-linux - WireGuard for the Linux kernel

Age	Commit message (Expand)	Author	Files	Lines
2023-11-07	riscv: Add remaining module relocations	Charlie Jenkins	2	-30/+423
2023-11-07	riscv: Avoid unaligned access when relocating modules	Emil Renner Berthing	1	-76/+81
2023-11-07	riscv: split cache ops out of dma-noncoherent.c	Christoph Hellwig	3	-15/+18
2023-11-06	riscv: Improve flush_tlb_kernel_range()	Alexandre Ghiti	2	-15/+30
2023-11-06	riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb	Alexandre Ghiti	4	-81/+72
2023-11-06	riscv: Improve flush_tlb_range() for hugetlb pages	Alexandre Ghiti	1	-1/+28
2023-11-06	riscv: Improve tlb_flush()	Alexandre Ghiti	3	-1/+17
2023-11-06	riscv: select ARCH_PROC_KCORE_TEXT	Andreas Schwab	1	-0/+3
2023-11-06	riscv: kernel: Use correct SYM_DATA_*() macro for data	Clément Léger	1	-5/+4
2023-11-06	riscv: Use SYM_*() assembly macros instead of deprecated ones	Clément Léger	17	-74/+60
2023-11-06	riscv: use ".L" local labels in assembly when applicable	Clément Léger	4	-44/+44
2023-11-06	riscv: boot: Fix creation of loader.bin	Geert Uytterhoeven	1	-0/+1
2023-11-06	riscv: Improve flush_tlb_kernel_range()	Alexandre Ghiti	2	-15/+30
2023-11-06	riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb	Alexandre Ghiti	4	-81/+72
2023-11-06	riscv: Improve flush_tlb_range() for hugetlb pages	Alexandre Ghiti	1	-1/+28
2023-11-06	riscv: Improve tlb_flush()	Alexandre Ghiti	3	-1/+17
2023-11-05	riscv: mm: update T-Head memory type definitions	Jisheng Zhang	1	-5/+9
2023-11-05	riscv: vdso.lds.S: remove hardcoded 0x800 .text start addr	Jisheng Zhang	1	-9/+8
2023-11-05	riscv: vdso.lds.S: merge .data section into .rodata section	Jisheng Zhang	1	-8/+7
2023-11-05	riscv: vdso.lds.S: drop __alt_start and __alt_end symbols	Jisheng Zhang	1	-2/+0
2023-11-05	riscv: add userland instruction dump to RISC-V splats	Yunhui Cui	1	-3/+18
2023-11-05	riscv: kprobes: allow writing to x0	Nam Cao	1	-1/+1
2023-11-05	riscv: provide riscv-specific is_trap_insn()	Nam Cao	1	-0/+6
2023-11-05	riscv: Introduce NAPOT field to PTDUMP	Yu Chien Peter Lin	1	-0/+4
2023-11-05	riscv: Introduce PBMT field to PTDUMP	Yu Chien Peter Lin	1	-0/+16
2023-11-05	riscv: Improve PTDUMP to show RSW with non-zero value	Yu Chien Peter Lin	2	-22/+17
2023-11-05	RISC-V: capitalise CMO op macros	Conor Dooley	5	-29/+29
2023-11-05	riscv: don't probe unaligned access speed if already done	Jisheng Zhang	1	-0/+4
2023-11-05	riscv: defconfig : add CONFIG_MMC_DW for starfive	Jinyu Tang	1	-0/+2
2023-11-05	riscv: signal: handle syscall restart before get_signal	Haorong Lu	1	-39/+46
2023-11-02	RISC-V: hwprobe: Fix vDSO SIGSEGV	Andrew Jones	2	-1/+6
2023-11-02	riscv: configs: defconfig: Enable configs required for RZ/Five SoC	Lad Prabhakar	1	-0/+52
2023-11-02	riscv: errata: prefix T-Head mnemonics with th.	Icenowy Zheng	1	-7/+7
2023-11-01	riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGN	Clément Léger	3	-0/+33
2023-11-01	riscv: report misaligned accesses emulation to hwprobe	Clément Léger	4	-1/+79
2023-11-01	riscv: annotate check_unaligned_access_boot_cpu() with __init	Clément Léger	1	-1/+1
2023-11-01	riscv: add support for sysctl unaligned_enabled control	Clément Léger	2	-0/+10
2023-11-01	riscv: add floating point insn support to misaligned access emulation	Clément Léger	2	-4/+269
2023-11-01	riscv: report perf event for misaligned fault	Clément Léger	1	-0/+5
2023-11-01	riscv: add support for misaligned trap handling in S-mode	Clément Léger	5	-23/+129
2023-11-01	riscv: remove unused functions in traps_misaligned.c	Clément Léger	1	-39/+7
2023-10-31	riscv: put interrupt entries into .irqentry.text	Nam Cao	1	-0/+2
2023-10-31	riscv: mm: Update the comment of CONFIG_PAGE_OFFSET	Song Shuai	1	-2/+2
2023-10-31	riscv: Using TOOLCHAIN_HAS_ZIHINTPAUSE marco replace zihintpause	Minda Chen	1	-1/+1
2023-10-31	riscv/mm: Fix the comment for swap pte format	Xiao Wang	1	-1/+1
2023-10-31	RISC-V: clarify the QEMU workaround in ISA parser	Tsukasa OI	1	-3/+4
2023-10-31	riscv: correct pt_level name via pgtable_l5/4_enabled	Song Shuai	1	-0/+3
2023-10-31	RISC-V: Provide pgtable_l5_enabled on rv32	Palmer Dabbelt	3	-1/+5
2023-10-31	clocksource: timer-riscv: Increase rating of clock_event_device for Sstc	Anup Patel	1	-0/+2
2023-10-31	clocksource: timer-riscv: Don't enable/disable timer interrupt	Anup Patel	1	-2/+13