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2021-06-30clk: divider: Add re-usable determine_rate implementationsMartin Blumenstingl2-14/+67
These are useful when running on 32-bit systems to increase the upper supported frequency limit. clk_ops.round_rate returns a signed long which limits the maximum rate on 32-bit systems to 2^31 (or approx. 2.14GHz). clk_ops.determine_rate internally uses an unsigned long so the maximum rate on 32-bit systems is 2^32 or approx. 4.29GHz. To avoid code-duplication switch over divider_{ro_,}round_rate_parent to use the new divider_{ro_,}determine_rate functions. Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20210627223959.188139-2-martin.blumenstingl@googlemail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-30clk: k210: Fix k210_clk_set_parent()Damien Le Moal1-0/+1
In k210_clk_set_parent(), add missing writel() call to update the mux register of a clock to change its parent. This also fixes a compilation warning with clang when compiling with W=1. Fixes: c6ca7616f7d5 ("clk: Add RISC-V Canaan Kendryte K210 clock driver") Cc: stable@vger.kernel.org Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> Link: https://lore.kernel.org/r/20210622064502.14841-1-damien.lemoal@wdc.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-30clk: lmk04832: Fix spelling mistakes in dev_err messages and commentsColin Ian King1-4/+4
There are handful of spelling mistakes in two dev_err error messages and comments. Fix them. Signed-off-by: Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20210629102956.17901-1-colin.king@canonical.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-30clk: lmk04832: fix return value check in lmk04832_probe()Wang Hai1-6/+6
In case of error, the function devm_kzalloc() and devm_kcalloc() return NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Fixes: 3bc61cfd6f4a ("clk: add support for the lmk04832") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Wang Hai <wanghai38@huawei.com> Link: https://lore.kernel.org/r/20210630020322.2555946-1-wanghai38@huawei.com Reviewed-by: Liam Beguin <lvb@xiphos.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-30clk: stm32mp1: fix missing spin_lock_init()Wang Hai1-0/+1
The driver allocates the spinlock but not initialize it. Use spin_lock_init() on it to initialize it correctly. Fixes: c392df194a2d ("clk: stm32mp1: move RCC reset controller into RCC clock driver") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Wang Hai <wanghai38@huawei.com> Link: https://lore.kernel.org/r/20210630015824.2555840-1-wanghai38@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-28clk: zynqmp: Handle divider specific read only flagRajan Vaja1-1/+9
Add support for divider specific read only CCF flag (CLK_DIVIDER_READ_ONLY). Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Link: https://lore.kernel.org/r/20210628070122.26217-5-rajan.vaja@xilinx.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-28clk: zynqmp: Use firmware specific mux clock flagsRajan Vaja2-1/+30
Use ZynqMP specific mux clock flags instead of using CCF flags. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Link: https://lore.kernel.org/r/20210628070122.26217-4-rajan.vaja@xilinx.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-28clk: zynqmp: Use firmware specific divider clock flagsRajan Vaja2-1/+33
Use ZynqMP specific divider clock flags instead of using CCF flags. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Link: https://lore.kernel.org/r/20210628070122.26217-3-rajan.vaja@xilinx.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-28clk: zynqmp: Use firmware specific common clock flagsRajan Vaja6-6/+52
Currently firmware passes CCF specific flags to ZynqMP clock driver. So firmware needs to be updated if CCF flags are changed. The firmware should have its own 'flag number space' that is distinct from the common clk framework's 'flag number space'. So define and use ZynqMP specific common clock flags instead of using CCF flags. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Link: https://lore.kernel.org/r/20210628070122.26217-2-rajan.vaja@xilinx.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-28clk: lmk04832: Use of match tableStephen Boyd1-2/+4
Presumably we want to use this match table so add a module device table and set the driver match pointer appropriately. Reported-by: kernel test robot <lkp@intel.com> Cc: Liam Beguin <lvb@xiphos.com> Fixes: 3bc61cfd6f4a ("clk: add support for the lmk04832") Link: https://lore.kernel.org/r/20210629060751.3119453-2-sboyd@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-28clk: lmk04832: Depend on SPIStephen Boyd1-0/+1
This driver depends on SPI. Otherwise compilation fails clk-lmk04832.c:(.text+0x1668): undefined reference to `spi_get_device_id' Reported-by: kernel test robot <lkp@intel.com> Cc: Liam Beguin <lvb@xiphos.com> Fixes: 3bc61cfd6f4a ("clk: add support for the lmk04832") Link: https://lore.kernel.org/r/20210629060751.3119453-1-sboyd@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-28clk: stm32mp1: new compatible for secure RCC supportGabriel Fernandez2-1/+110
Platform STM32MP1 can be used in configuration where some clock resources cannot be accessed by Linux kernel when executing in non-secure state of the CPU(s). In such configuration, the RCC clock driver must not register clocks it cannot access. They are expected to be registered from another clock driver such as the SCMI clock driver. This change uses specific compatible string "st,stm32mp1-rcc-secure" to specify RCC clock driver configuration where RCC is secure. Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Link: https://lore.kernel.org/r/20210617051814.12018-12-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-28dt-bindings: clock: stm32mp1 new compatible for secure rccGabriel Fernandez1-2/+4
Introduce new compatible string "st,stm32mp1-rcc-secure" for stm32mp1 clock driver when the device is configured with RCC security support hardened. Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210617051814.12018-11-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-28dt-bindings: reset: add MCU HOLD BOOT ID for SCMI reset domains on stm32mp15Gabriel Fernandez1-0/+2
Add ID to SCMI0 to exposes reset controller for the MCU HOLD BOOT resource. Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210617051814.12018-10-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-28dt-bindings: reset: add IDs for SCMI reset domains on stm32mp15Gabriel Fernandez1-0/+13
stm32mp15 TZ secure firmware provides SCMI reset domains for secure resources. This change defines the SCMI reset domain identifiers used by SCMI agents and servers. Stm32mp15 TZ secure firmware provides SCMI clocks for oscillators, some PLL output and few secure aware interfaces. This change defines the SCMI clock identifiers used by SCMI agents and servers. Server SCMI0 exposes reset controllers for resources under RCC[TZEN] configuration control. Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210617051814.12018-9-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-28dt-bindings: clock: add IDs for SCMI clocks on stm32mp15Gabriel Fernandez1-0/+27
stm32mp15 TZ secure firmware provides SCMI clocks for oscillators, some PLL output and few secure aware interfaces. This change defines the SCMI clock identifiers used by SCMI agents and servers. Server SCMI0 exposes clocks and reset controllers for resources under RCC[TZEN] configuration control. Server SCMI1 exposes clocks for resources under RCC[MCKPROT] control. Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210617051814.12018-8-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-28reset: stm32mp1: remove stm32mp1 resetGabriel Fernandez3-122/+0
st32mp1 RCC reset driver was moved into stm32mp1 RCC clock driver. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Link: https://lore.kernel.org/r/20210617051814.12018-7-gabriel.fernandez@foss.st.com Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: hisilicon: Add clock driver for hi3559A SoCDongjiu Geng5-2/+856
Add clock drivers for hi3559A SoC, this driver controls the SoC registers to supply different clocks to different IPs in the SoC. Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com> Link: https://lore.kernel.org/r/1616498973-47067-3-git-send-email-gengdongjiu1@gmail.com [sboyd@kernel.org: Mark arrays static, add __iomem, drop unused array, avoid kfree of devm memory] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27dt-bindings: Document the hi3559a clock bindingsDongjiu Geng2-0/+224
Add DT bindings documentation for hi3559a SoC clock. Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1616498973-47067-2-git-send-email-gengdongjiu1@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: si5341: Add sysfs properties to allow checking/resetting device faultsRobert Hancock1-0/+96
Add sysfs property files to allow viewing the current and latched states of the input present and PLL lock bits, and allow resetting the latched fault state. This allows manual checks or automated userspace polling for faults occurring after initialization. Signed-off-by: Robert Hancock <robert.hancock@calian.com> Link: https://lore.kernel.org/r/20210325192643.2190069-10-robert.hancock@calian.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: si5341: Add silabs,iovdd-33 propertyRobert Hancock1-1/+9
Add a property to allow specifying that the external I2C IO pins are using 3.3V voltage thresholds rather than 1.8V. Signed-off-by: Robert Hancock <robert.hancock@calian.com> Link: https://lore.kernel.org/r/20210325192643.2190069-9-robert.hancock@calian.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: si5341: Add silabs,xaxb-ext-clk propertyRobert Hancock1-2/+7
Add a property to allow specifying that the device XA/XB pins are used for an external clock input rather than for a clock crystal. Signed-off-by: Robert Hancock <robert.hancock@calian.com> Link: https://lore.kernel.org/r/20210325192643.2190069-8-robert.hancock@calian.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: si5341: Allow different output VDD_SEL valuesRobert Hancock1-26/+110
The driver was not previously programming the VDD_SEL values for each output to indicate what external VDDO voltage was used for each. Add ability to specify a regulator supplying the VDDO pin for each output of the device. The voltage of the regulator is used to automatically set the VDD_SEL value appropriately. If no regulator is specified and the chip is being reconfigured, assume 2.5V which appears to be the chip default. Signed-off-by: Robert Hancock <robert.hancock@calian.com> Link: https://lore.kernel.org/r/20210325192643.2190069-7-robert.hancock@calian.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: si5341: Update initialization magicRobert Hancock1-1/+3
Update the default register settings to include the VCO_RESET_CALCODE settings (set by the SiLabs ClockBuilder software but not described in the datasheet). Also update part of the initialization sequence to match ClockBuilder and the datasheet. Fixes: 3044a860fd ("clk: Add Si5341/Si5340 driver") Signed-off-by: Robert Hancock <robert.hancock@calian.com> Link: https://lore.kernel.org/r/20210325192643.2190069-6-robert.hancock@calian.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: si5341: Check for input clock presence and PLL lock on startupRobert Hancock1-0/+26
After initializing the device, wait for it to report that the input clock is present and the PLL has locked before declaring success. Fixes: 3044a860fd ("clk: Add Si5341/Si5340 driver") Signed-off-by: Robert Hancock <robert.hancock@calian.com> Link: https://lore.kernel.org/r/20210325192643.2190069-5-robert.hancock@calian.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: si5341: Avoid divide errors due to bogus register contentsRobert Hancock1-2/+13
If the Si5341 is being initially programmed and has no stored NVM configuration, some of the register contents may contain unexpected values, such as zeros, which could cause divide by zero errors during driver initialization. Trap errors caused by zero registers or zero clock rates which could result in divide errors later in the code. Fixes: 3044a860fd ("clk: Add Si5341/Si5340 driver") Signed-off-by: Robert Hancock <robert.hancock@calian.com> Link: https://lore.kernel.org/r/20210325192643.2190069-4-robert.hancock@calian.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: si5341: Wait for DEVICE_READY on startupRobert Hancock1-0/+32
The Si5341 datasheet warns that before accessing any other registers, including the PAGE register, we need to wait for the DEVICE_READY register to indicate the device is ready, or the process of the device loading its state from NVM can be corrupted. Wait for DEVICE_READY on startup before continuing initialization. This is done using a raw I2C register read prior to setting up regmap to avoid any potential unwanted automatic PAGE register accesses from regmap at this stage. Fixes: 3044a860fd ("clk: Add Si5341/Si5340 driver") Signed-off-by: Robert Hancock <robert.hancock@calian.com> Link: https://lore.kernel.org/r/20210325192643.2190069-3-robert.hancock@calian.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27dt-bindings: clock: clk-si5341: Add new attributesRobert Hancock1-6/+10
Add new silabs,xaxb-ext-clk and silabs,iovdd-33 properties. Changed vdd-supply on top-level node to optional since it is not actually used by the driver. Removed vdd-supply from output sub-nodes, as it was not supported by the driver and it is not easily possible to support this in that location with the kernel regulator infrastructure. Changed to have vddoX-supply attributes for each output on the top-level device node. Signed-off-by: Robert Hancock <robert.hancock@calian.com> Link: https://lore.kernel.org/r/20210325192643.2190069-2-robert.hancock@calian.com Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27drivers: ti: remove redundant error message in adpll.cYu Jiahua1-4/+1
There is a error message within devm_ioremap_resource already, so remove the dev_err call to avoid redundant error message. Signed-off-by: Yu Jiahua <yujiahua1@huawei.com> Link: https://lore.kernel.org/r/20210616034826.37276-1-yujiahua1@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27dt-bindings: clock: st: clkgen-fsyn: add new introduced compatibleAlain Volmat1-0/+3
New compatible are added, supporting various kind of clkgen-fsyn used for STiH407, STiH410 and STiH418 Signed-off-by: Alain Volmat <avolmat@me.com> Link: https://lore.kernel.org/r/20210331201632.24530-8-avolmat@me.com Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: st: clkgen-fsyn: embed soc clock outputs within compatible dataAlain Volmat1-12/+101
In order to avoid relying on the old style description via the DT clock-output-names, add compatible data describing the flexgen outputs clocks for all STiH407/STiH410 and STiH418 SOCs. In order to ease transition between the two methods, this commit introduce the new compatible without removing the old method. Once DTs will be fixed, the method relying on DT clock-output-names will be removed from this driver as well as old compatibles. Signed-off-by: Alain Volmat <avolmat@me.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20210331201632.24530-7-avolmat@me.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27dt-bindings: clock: st: clkgen-pll: add new introduced compatibleAlain Volmat1-0/+3
New compatible are added, supporting various kind of clkgen-pll used for STiH407, STiH410 and STiH418 Signed-off-by: Alain Volmat <avolmat@me.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210331201632.24530-6-avolmat@me.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: st: clkgen-pll: embed soc clock outputs within compatible dataAlain Volmat1-14/+106
In order to avoid relying on the old style description via the DT clock-output-names, add compatible data describing the flexgen outputs clocks for all STiH407/STiH410 and STiH418 SOCs. In order to ease transition between the two methods, this commit introduce the new compatible without removing the old method. Once DTs will be fixed, the method relying on DT clock-output-names will be removed from this driver as well as old compatibles. Signed-off-by: Alain Volmat <avolmat@me.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20210331201632.24530-5-avolmat@me.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27dt-bindings: clock: st: flexgen: add new introduced compatibleAlain Volmat1-0/+10
New compatible are added, supporting various kind of flexgen in STiH407, STiH410 and STiH418 Signed-off-by: Alain Volmat <avolmat@me.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210331201632.24530-4-avolmat@me.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: st: flexgen: embed soc clock outputs within compatible dataAlain Volmat1-14/+353
In order to avoid relying on the old style description via the DT clock-output-names, add compatible data describing the flexgen outputs clocks for all STiH407/STiH410 and STiH418 SOCs. In order to ease transition between the two methods, this commit introduce the new compatible without removing the old method. Once DTs will be fixed, the method relying on DT clock-output-names will be removed from this driver as well as old compatibles. Signed-off-by: Alain Volmat <avolmat@me.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20210331201632.24530-3-avolmat@me.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: st: clkgen-pll: remove unused variable of struct clkgen_pllAlain Volmat1-1/+0
ODF field within the struct clkgen_pll is never used by the driver and can thus be removed. Signed-off-by: Alain Volmat <avolmat@me.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20210331201632.24530-2-avolmat@me.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: ingenic: Add support for the JZ4760Paul Cercueil5-0/+495
Add the CGU code and the compatible string to the TCU driver to support the JZ4760 SoC. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-7-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: ingenic: Support overriding PLLs M/N/OD calc algorithmPaul Cercueil2-13/+30
SoC-specific code can now provide a callback if they need to compute the M/N/OD values in a specific way. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> # on CU1000-neo/X1000E Link: https://lore.kernel.org/r/20210530164923.18134-6-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: ingenic: Remove pll_info.no_bypass_bitPaul Cercueil3-8/+6
We can express that a PLL has no bypass bit by simply setting the .bypass_bit field to a negative value. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-5-paul@crapouillou.net Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> # on CU1830-neo/X1830 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: ingenic: Read bypass register only when there is onePaul Cercueil1-8/+11
Rework the clock code so that the bypass register is only read when there is actually a bypass functionality. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-4-paul@crapouillou.net Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> # on CU1830-neo/X1830 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: Support bypassing dividersPaul Cercueil5-29/+42
When a clock is declared as both CGU_CLK_DIV and CGU_CLK_MUX, the CGU code expects the mux to be applied first, the divider second. On the JZ4760, and maybe on some other SoCs, some clocks also have a mux setting and a divider, but the divider is not applied to all parents selectable from the mux. This could be solved by creating two clocks, one with CGU_CLK_DIV and one with CGU_CLK_MUX, but that would increase the number of clocks. Instead, add a 8-bit mask to CGU_CLK_DIV clocks. If the bit corresponding to the parent clock's index is set, the divider is bypassed. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210530164923.18134-3-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27dt-bindings: clock: ingenic: Add ingenic,jz4760{,b}-cgu compatiblesPaul Cercueil1-0/+4
Add ingenic,jz4760-cgu and ingenic,jz4760b-cgu compatible strings for the JZ4760 and JZ4760B SoCs respectively. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210530164923.18134-2-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: qcom: clk-alpha-pll: fix CAL_L write in alpha_pll_fabia_prepareJonathan Marek1-1/+1
Caught this when looking at alpha-pll code. Untested but it is clear that this was intended to write to PLL_CAL_L_VAL and not PLL_ALPHA_VAL. Fixes: 691865bad627 ("clk: qcom: clk-alpha-pll: Add support for Fabia PLL calibration") Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20210609022852.4151-1-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: actions: Add NIC and ETHERNET clock support for Actions S500 SoCCristian Ciocaltea1-1/+16
Add support for the missing NIC and ETHERNET clocks in the Actions Semi Owl S500 SoC clock driver. Additionally, change APB clock parent from AHB to the newly added NIC. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/d62e4f1f85c5cef05be14d9e8143e88bbddd2e0f.1623354574.git.cristian.ciocaltea@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27dt-bindings: clock: Add NIC and ETHERNET bindings for Actions S500 SoCCristian Ciocaltea1-2/+4
Add the missing NIC and ETHERNET clock bindings constants for Actions Semi Owl S500 SoC. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/1d0902cf073f76a1a602410061481ccb3fc36a72.1623354574.git.cristian.ciocaltea@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: actions: Fix AHPPREDIV-H-AHB clock chain on Owl S500 SoCCristian Ciocaltea1-8/+11
There are a few issues with the setup of the Actions Semi Owl S500 SoC's clock chain involving AHPPREDIV, H and AHB clocks: * AHBPREDIV clock is defined as a muxer only, although it also acts as a divider. * H clock is using a wrong divider register offset * AHB is defined as a multi-rate factor clock, but it is actually just a fixed pass clock. Let's provide the following fixes: * Change AHBPREDIV clock to an ungated OWL_COMP_DIV definition. * Use the correct register shift value in the OWL_DIVIDER definition for H clock * Drop the unneeded 'ahb_factor_table[]' and change AHB clock to an ungated OWL_COMP_FIXED_FACTOR definition. Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC") Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Link: https://lore.kernel.org/r/21c1abd19a7089b65a34852ac6513961be88cbe1.1623354574.git.cristian.ciocaltea@gmail.com Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: actions: Fix bisp_factor_table based clocks on Owl S500 SoCCristian Ciocaltea1-15/+29
The following clocks of the Actions Semi Owl S500 SoC have been defined to use a shared clock factor table 'bisp_factor_table[]': DE[1-2], VCE, VDE, BISP, SENSOR[0-1] There are several issues involved in this approach: * 'bisp_factor_table[]' describes the configuration of a regular 8-rates divider, so its usage is redundant. Additionally, judging by the BISP clock context, it is incomplete since it maps only 8 out of 12 possible entries. * The clocks mentioned above are not identical in terms of the available rates, therefore cannot rely on the same factor table. Specifically, BISP and SENSOR* are standard 12-rate dividers so their configuration should rely on a proper clock div table, while VCE and VDE require a factor table that is a actually a subset of the one needed for DE[1-2] clocks. Let's fix this by implementing the following: * Add new factor tables 'de_factor_table' and 'hde_factor_table' to properly handle DE[1-2], VCE and VDE clocks. * Add a common div table 'std12rate_div_table' for BISP and SENSOR[0-1] clocks converted to OWL_COMP_DIV. * Drop the now unused 'bisp_factor_table[]'. Additionally, drop the CLK_IGNORE_UNUSED flag for SENSOR[0-1] since there is no reason to always keep ON those clocks. Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC") Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/e675820a46cd9930d8d576c6cae61d41c1a8416f.1623354574.git.cristian.ciocaltea@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: actions: Fix SD clocks factor table on Owl S500 SoCCristian Ciocaltea1-4/+2
Drop the unsupported entries in the factor table used for the SD[0-2] clocks definitions on the Actions Semi Owl S500 SoC. Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC") Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/196c948d708a22b8198c95f064a0f6b6820f9980.1623354574.git.cristian.ciocaltea@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: actions: Fix UART clock dividers on Owl S500 SoCCristian Ciocaltea1-6/+6
Use correct divider registers for the Actions Semi Owl S500 SoC's UART clocks. Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC") Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/4714d05982b19ac5fec2ed74f54be42d8238e392.1623354574.git.cristian.ciocaltea@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2021-06-27clk: bd718xx: Drop BD70528 supportMatti Vaittinen2-12/+5
The only known BD70528 use-cases are such that the PMIC is controlled from separate MCU which is not running Linux. I am not aware of any Linux driver users. Furthermore, it seems there is no demand for this IC. Let's ease the maintenance burden and drop the driver. We can always add it back if there is sudden need for it. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Link: https://lore.kernel.org/r/937ed0828486a08e2d00bce2815d491c1c9c49b4.1621937490.git.matti.vaittinen@fi.rohmeurope.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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