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2025-04-14irqchip/sg2042-msi: Introduce configurable chipinfo for SG2042Inochi Amaoto1-11/+42
As the controller on SG2044 uses different msi_parent_ops and a difffernt irq_chip, it is necessary to provide that information to the probe function. Add a new chipinfo structure to hold that information, implement the necessary logic and make SG2042 use it. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Chen Wang <wangchen20@iscas.ac.cn> # SG2042 Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/all/20250413224922.69719-4-inochiama@gmail.com
2025-04-14irqchip/sg2042-msi: Rename functions and data structures to be SG2042 agnosticInochi Amaoto1-23/+23
As the driver logic can be used in both SG2042 and SG2044 SoCs, rename functions and data structures, which are not SG2042 specific, to SG204x*. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Chen Wang <wangchen20@iscas.ac.cn> # SG2042 Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/all/20250413224922.69719-3-inochiama@gmail.com
2025-04-14dt-bindings: interrupt-controller: Add Sophgo SG2044 MSI controllerInochi Amaoto1-1/+3
Like SG2042, SG2044 also uses an external MSI controller to provide MSI interrupt for PCIe controllers. The difference between these two MSI controllers are: 1. SG2044 acks the interrupt by writing 0, SG2042 by setting the bit related to the interrupt. 2. SG2044 uses interrupt number modulo 32 as MSI message data, but SG2042 uses the bit related to the interrupt. Add support for the SG2044 MSI controller. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Chen Wang <wangchen20@iscas.ac.cn> # SG2042 Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/all/20250413224922.69719-2-inochiama@gmail.com
2025-04-08genirq/generic-chip: Fix incorrect lock guard conversionsGeert Uytterhoeven1-2/+2
When booting BeagleBone Black: ------------[ cut here ]------------ WARNING: CPU: 0 PID: 0 at kernel/locking/lockdep.c:4398 lockdep_hardirqs_on_prepare+0x23c/0x280 DEBUG_LOCKS_WARN_ON(early_boot_irqs_disabled) CPU: 0 UID: 0 PID: 0 Comm: swapper/0 Not tainted 6.15.0-rc1-boneblack-00004-g195298c3b116 #209 NONE Hardware name: Generic AM33XX (Flattened Device Tree) Call trace: _raw_spin_unlock_irq from irq_map_generic_chip+0x144/0x190 irq_map_generic_chip from irq_domain_associate_locked+0x68/0x164 irq_domain_associate_locked from irq_create_fwspec_mapping+0x34c/0x43c irq_create_fwspec_mapping from irq_create_of_mapping+0x64/0x8c irq_create_of_mapping from irq_of_parse_and_map+0x54/0x7c irq_of_parse_and_map from dmtimer_clkevt_init_common+0x54/0x15c dmtimer_clkevt_init_common from dmtimer_systimer_init+0x41c/0x5b8 dmtimer_systimer_init from timer_probe+0x68/0xf0 timer_probe from start_kernel+0x4a4/0x6bc start_kernel from 0x0 irq event stamp: 0 hardirqs last enabled at (0): [<00000000>] 0x0 hardirqs last disabled at (0): [<00000000>] 0x0 softirqs last enabled at (0): [<00000000>] 0x0 softirqs last disabled at (0): [<00000000>] 0x0 ---[ end trace 0000000000000000 ]--- and: ------------[ cut here ]------------ WARNING: CPU: 0 PID: 0 at init/main.c:1022 start_kernel+0x4e8/0x6bc Interrupts were enabled early CPU: 0 UID: 0 PID: 0 Comm: swapper/0 Tainted: G W 6.15.0-rc1-boneblack-00004-g195298c3b116 #209 NONE Tainted: [W]=WARN Hardware name: Generic AM33XX (Flattened Device Tree) Call trace: unwind_backtrace from show_stack+0x10/0x14 show_stack from dump_stack_lvl+0x6c/0x90 dump_stack_lvl from __warn+0x70/0x1b0 __warn from warn_slowpath_fmt+0x1d4/0x1ec warn_slowpath_fmt from start_kernel+0x4e8/0x6bc start_kernel from 0x0 irq event stamp: 0 hardirqs last enabled at (0): [<00000000>] 0x0 hardirqs last disabled at (0): [<00000000>] 0x0 softirqs last enabled at (0): [<00000000>] 0x0 softirqs last disabled at (0): [<00000000>] 0x0 ---[ end trace 0000000000000000 ]--- Fix this by correcting two misconversions of raw_spin_{,un}lock_irq{save,restore}() to lock guards. Fixes: 195298c3b11628a6 ("genirq/generic-chip: Convert core code to lock guards") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/514f94c5891c61ac0a4a7fdad113e75db1eea367.1744135467.git.geert+renesas@glider.be
2025-04-07genirq/generic-chip: Remove unused lock wrappersThomas Gleixner1-20/+0
All users are converted to lock guards. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/20250313142524.388478168@linutronix.de
2025-04-07irqchip: Convert generic irqchip locking to guardsThomas Gleixner14-127/+56
Conversion was done with Coccinelle and a few manual fixups. In a few interrupt chip callbacks this changes replaces raw_spin_lock_irqsave() with a guard(raw_spinlock). That's intended and correct because those interrupt chip callbacks are invoked with the interrupt descriptor lock held and interrupts disabled. No point in using the irqsave variant. No functional change. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/all/20250313142524.325627746@linutronix.de
2025-04-07gpio: mvebu: Convert generic irqchip locking to guard()Thomas Gleixner1-10/+5
Conversion was done with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/all/20250313142524.262678485@linutronix.de
2025-04-07ARM: orion/gpio:: Convert generic irqchip locking to guard()Thomas Gleixner1-4/+2
Conversion was done with Coccinelle. No functional change. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/all/20250313142524.200515896@linutronix.de
2025-04-07soc: dove: Convert generic irqchip locking to guard()Thomas Gleixner1-2/+1
Conversion was done with Coccinelle. No functional change. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/all/20250313142524.137040686@linutronix.de
2025-04-07genirq/generic-chip: Convert core code to lock guardsThomas Gleixner1-31/+16
Replace the irq_gc_lock/unlock() pairs with guards. There is no point to implement a guard wrapper for them as they just wrap around raw_spin_lock*(). Switch the other lock instances in the core code to guards as well. Conversion was done with Coccinelle plus manual fixups. No functional change. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/all/20250313142524.073826193@linutronix.de
2025-04-07genirq/generic-chip: Make locking unconditionalThomas Gleixner1-5/+0
The SMP conditional wrappers around raw_spin_[un]lock() have no real value. On !SMP kernels the lock operations are NOOPs except for a preempt_disable/enable() pair on PREEMPT enabled kernels, which are not really worth to optimize for. Aside of that this evades lockdep on !SMP kernels. Remove the !SMP stubs and make it unconditional. No functional change. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/20250313142524.011345765@linutronix.de
2025-04-07irqchip: Add EcoNet EN751221 INTCCaleb James DeLisle3-0/+315
Add a driver for the interrupt controller in the EcoNet EN751221 MIPS SoC. Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/20250330170306.2584136-4-cjd@cjdns.fr