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2021-12-20arm64: dts: qcom: sm8450-qrd: Enable USB nodesVinod Koul1-0/+23
Enable the usb phy and usb controller in peripheral mode. This helps to get the adb working with the QRD board. Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211216110813.658384-2-vkoul@kernel.org
2021-12-20arm64: dts: qcom: sm8450: Add usb nodesVinod Koul1-0/+89
SM8450 features a single USB controller which connects to both HS and SS phy. Add the USB and the phy nodes for Qualcomm SM8450 SoC. Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211216110813.658384-1-vkoul@kernel.org
2021-12-20ARM: dts: Remove "spidev" nodesRob Herring12-172/+1
"spidev" is not a real device, but a Linux implementation detail. It has never been documented either. The kernel has WARNed on the use of it for over 6 years. Time to remove its usage from the tree. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20211217221232.3664417-1-robh@kernel.org' Reviwed-by: Mark Brown <broonie@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-12-20dt-bindings: pinctrl: samsung: Add pin drive definitions for Exynos850Sam Protsenko1-1/+12
All Exynos850 GPIO blocks can use EXYNOS5420_PIN_DRV* definitions, except GPIO_HSI block. Add pin drive strength definitions for GPIO_HSI block correspondingly. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211217161549.24836-6-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-12-20dt-bindings: arm: samsung: Document E850-96 board bindingSam Protsenko1-0/+6
Add binding for the WinLink E850-96 board, which is based on Samsung Exynos850 SoC. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20211217161549.24836-5-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-12-20dt-bindings: Add vendor prefix for WinLinkSam Protsenko1-0/+2
WinLink Co., Ltd is a hardware design and manufacturing company based in South Korea. Official web-site: [1]. [1] http://win-link.net/ Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211217161549.24836-4-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-12-19ARM: dts: BCM5301X: correct RX delay and enable flow control on Asus RT-AC88UArınç ÜNAL1-1/+2
The current 'rx-internal-delay-ps' property value on the Realtek switch node, 2000, will be divided by 300, resulting in 6.66, which will be rounded to the closest step value, 7. Change it to 2100 to be accurate. See ef136837aaf6 ("net: dsa: rtl8365mb: set RGMII RX delay in steps of 0.3 ns") for reference. Flow control needs to be enabled on both sides of the internal and external switch. It is already enabled on the CPU port of the Realtek switch so we also enable it on the external switch port of the Broadcom switch as well. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2021-12-19ARM: dts: NSP: Rename SATA unit nameFlorian Fainelli1-1/+1
Rename the SATA controller unit name from ahci to sata in preparation for adding the Broadcom SATA3 controller YAML binding which will bring validation. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2021-12-19ARM: dts: NSP: Fixed iProc PCIe MSI sub-nodeFlorian Fainelli1-3/+3
Rename the msi controller unit name to 'msi' to avoid collisions with the 'msi-controller' boolean property. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2021-12-19ARM: dts: HR2: Fixed iProc PCIe MSI sub-nodeFlorian Fainelli1-2/+2
Rename the msi controller unit name to 'msi' to avoid collisions with the 'msi-controller' boolean property. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2021-12-19ARM: dts: Cygnus: Update PCIe PHY node unit name(s)Florian Fainelli1-3/+3
Update the PCIe PHY node unit name and its sub-nodes to help with upcoming changes converting the Cygnus PCIe PHY DT binding to YAML and later the iProc PCIe controller binding to YAML. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2021-12-19ARM: dts: Cygnus: Fixed iProc PCIe controller propertiesFlorian Fainelli1-6/+6
Rename the msi controller unit name to 'msi' to avoid collisions with the 'msi-controller' boolean property. We also need to re-arrange the 'ranges' property to show the two cells as being separate instead of combined since the DT checker is not able to differentiate otherwise. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2021-12-18dt-bindings: soc: bcm: Convert brcm,bcm2835-vchiq to json-schemaStefan Wahren2-17/+53
This converts the VCHIQ bindings to YAML format. Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Co-developed-by: Nicolas Saenz Julienne <nsaenz@kernel.org> Signed-off-by: Nicolas Saenz Julienne <nsaenz@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211215094448.280796-1-nsaenz@kernel.org
2021-12-17ARM: dts: armada-38x: Add generic compatible to UART nodesMarek Behún1-2/+2
Add generic compatible string "ns16550a" to serial port nodes of Armada 38x. This makes it possible to use earlycon. Fixes: 0d3d96ab0059 ("ARM: mvebu: add Device Tree description of the Armada 380/385 SoCs") Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <kabel@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2021-12-17arm64: dts: marvell: cn9130: enable CP0 GPIO controllersRobert Marko1-0/+8
CN9130 has a built-in CP115 which has 2 GPIO controllers, but unlike in Armada 7k and 8k both are left disabled by the SoC DTSI. This first of all makes no sense as they are always present due to being SoC built-in and its an issue as boards like CN9130-CRB use the CPO GPIO2 pins for regulators and SD card support without enabling them first. So, enable both of them like Armada 7k and 8k do. Fixes: 6b8970bd8d7a ("arm64: dts: marvell: Add support for Marvell CN9130 SoC support") Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2021-12-17arm64: dts: marvell: cn9130: add GPIO and SPI aliasesRobert Marko1-0/+7
CN9130 has one CP115 built in, which like the CP110 has 2 GPIO and 2 SPI controllers built-in. However, unlike the Armada 7k and 8k the SoC DTSI doesn't add the required aliases as both the Orion SPI driver and MVEBU GPIO drivers require the aliases to be present. So add the required aliases for GPIO and SPI controllers. Fixes: 6b8970bd8d7a ("arm64: dts: marvell: Add support for Marvell CN9130 SoC support") Signed-off-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2021-12-17arm64: dts: marvell: armada-37xx: Add xtal clock to comphy nodePali Rohár1-0/+2
Kernel driver phy-mvebu-a3700-comphy.c needs to know the rate of the reference xtal clock. So add missing xtal clock source into comphy device tree node. If the property is not present, the driver defaults to 25 MHz xtal rate (which, as far as we know, is used by all the existing boards). Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Marek Behún <kabel@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2021-12-17arm/arm64: dts: Add MV88E6393X to CN9130-CRB device treeChris Packham1-0/+130
The CN9130-CRB boards have a MV88E6393X switch connected to eth0. Add the necessary dts nodes and properties for this. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2021-12-17arm/arm64: dts: Enable CP0 GPIOs for CN9130-CRBChris Packham1-0/+10
Enable the CP0 GPIO devices for the CN9130-CRB. This is needed for a number of the peripheral devices to function. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2021-12-17arm64: tegra: Add host1x hotflush reset on Tegra210Thierry Reding1-2/+2
Add the host1x memory client hotflush reset on Tegra210. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-17media: dt: bindings: tegra-vde: Document OPP and power domainDmitry Osipenko1-0/+12
Document new OPP table and power domain properties of the video decoder hardware. Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-17media: dt: bindings: tegra-vde: Convert to schemaDmitry Osipenko2-64/+107
Convert NVIDIA Tegra video decoder binding to schema. Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-17dt-bindings: host1x: Document Memory Client resets of Host1x, GR2D and GR3DDmitry Osipenko1-0/+4
Memory Client should be blocked before hardware reset is asserted in order to prevent memory corruption and hanging of memory controller. Document Memory Client resets of Host1x, GR2D and GR3D hardware units. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-17dt-bindings: host1x: Document OPP and power domain propertiesDmitry Osipenko1-0/+49
Document new DVFS OPP table and power domain properties of the Host1x bus and devices sitting on the bus. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-17dt-bindings: clock: tegra-car: Document new clock sub-nodesDmitry Osipenko1-0/+37
Document sub-nodes which describe Tegra SoC clocks that require a higher voltage of the core power domain in order to operate properly on a higher clock rates. Each node contains a phandle to OPP table and power domain. The root PLLs and system clocks don't have any specific device dedicated to them, clock controller is in charge of managing power for them. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-17dt-bindings: ARM: tegra: Document Pegatron ChagallDavid Heidelberg1-0/+3
Document Pegatron Chagall, which is Tegra30-based tablet device. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-17dt-bindings: ARM: tegra: Document ASUS TransformersSvyatoslav Ryhel1-0/+16
Document Tegra20/30/114-based ASUS Transformer Series tablet devices. This group includes EeePad TF101, Prime TF201, Pad TF300T, TF300TG Infinity TF700T, TF701T. Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Anton Bambura <jenneron@protonmail.com> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-17dt-bindings: usb: tegra-xudc: Document interconnects and iommus propertiesThierry Reding1-0/+13
Add the interconnects, interconnect-names and iommus properties to the device tree bindings for the Tegra XUDC controller. These are used to describe the device's paths to and from memory. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-17dt-bindings: serial: Document Tegra234 TCUThierry Reding1-1/+6
Add the compatible string for the TCU found on the Tegra234 SoC. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-17dt-bindings: serial: tegra-tcu: Convert to json-schemaThierry Reding2-35/+56
Convert the Tegra TCU device tree bindings to json-schema. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-17dt-bindings: thermal: tegra186-bpmp: Convert to json-schemaThierry Reding2-33/+42
Convert the Tegra186 (and later) BPMP thermal device tree bindings from the free-form text format to json-schema. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-17dt-bindings: firmware: tegra: Convert to json-schemaThierry Reding2-107/+186
Convert the NVIDIA Tegra186 (and later) BPMP bindings from the free-form text format to json-schema. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-17dt-bindings: tegra: pmc: Convert to json-schemaThierry Reding2-133/+198
Convert the NVIDIA Tegra186 (and later) PMC bindings from the free-form text format to json-schema. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-17dt-bindings: serial: 8250: Document Tegra234 UARTThierry Reding1-1/+2
Add the compatible string for the UART found on the Tegra234 SoC. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-17dt-bindings: mmc: tegra: Document Tegra234 SDHCIThierry Reding1-0/+6
Add the compatible string for the SDHCI block found on the Tegra234 SoC. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-17dt-bindings: fuse: tegra: Document Tegra234 FUSEThierry Reding1-0/+1
Add the compatible string for the FUSE block found on the Tegra234 SoC. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-17dt-bindings: fuse: tegra: Convert to json-schemaThierry Reding2-42/+88
Convert the NVIDIA Tegra FUSE bindings from the free-form text format to json-schema. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-17dt-bindings: rtc: tegra: Document Tegra234 RTCThierry Reding1-0/+1
Add the compatible string for the RTC block found on the Tegra234 SoC. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-17dt-bindings: rtc: tegra: Convert to json-schemaThierry Reding2-24/+60
Convert the NVIDIA Tegra RTC bindings from the free-form text format to json-schema. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-17dt-bindings: mailbox: tegra: Document Tegra234 HSPThierry Reding1-0/+3
Add the compatible string for the HSP block found on the Tegra234 SoC. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-17dt-bindings: mailbox: tegra: Convert to json-schemaThierry Reding2-72/+111
Convert the NVIDIA Tegra HSP bindings from the free-form text format to json-schema. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-17dt-bindings: mmc: tegra: Convert to json-schemaThierry Reding2-143/+311
Convert the NVIDIA Tegra SDHCI bindings from the free-form text format to json-schema. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-17ARM: tegra: Add host1x hotflush reset on Tegra124Thierry Reding1-2/+2
Add the host1x memory client hotflush reset on Tegra124. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-17ARM: tegra: Add memory client hotflush resets on Tegra114Thierry Reding1-6/+6
Add the host1x, gr2d and gr3d memory client hotflush resets on Tegra114. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-17arm64: dts: renesas: Fix pin controller node namesGeert Uytterhoeven2-2/+2
Align all pin controller node names with the expectations of the DT bindings in Documentation/devicetree/bindings/pinctrl/pinctrl.yaml. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/09a09c8ac9cb1a11b859c1ab9d9eae84cfefb1bb.1639666967.git.geert+renesas@glider.be