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2018-07-16drm/nouveau/bios/vpstate: There are some fermi vbios with no boost or tdp entryKarol Herbst1-2/+8
If the entry size is too small, default to invalid values for both boost_id and tdp_id, so as to default to the base clock in both cases. Signed-off-by: Karol Herbst <karolherbst@gmail.com> Signed-off-by: Martin Peres <martin.peres@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-07-16drm/nouveau/kms/nv50-: Allow vblank_disable_immediateMario Kleiner1-0/+3
With instantaneous high precision vblank timestamping that updates at leading edge of vblank, the emulated "hw vblank counter" from vblank timestamping, which increments at leading edge of vblank, and reliable page flip execution and completion at leading edge of vblank, we should meet the requirements for fast/ immediate vblank irq disable/enable. This is only allowed on nv50+ gpu's, ie. the ones with atomic modesetting. One requirement for immediate vblank disable is that high precision vblank timestamping works reliably all the time on all connectors. This is not the case on all pre-nv50 parts for analog VGA outputs, where we currently don't always have support for scanout position queries and therefore fall back to vblank interrupt timestamping. The implementation in nv04_head_state() does not return valid values for vblanks, vtotal, hblanks, htotal for VGA outputs on all cards, but those are needed for scanout position queries. Testing on Linux-4.12-rc5 + drm-next on a GeForce 9500 GT (NV G96) with timing measurement equipment indicates this works fine, so allow immediate vblank disable for power saving. For debugging in case of unexpected trouble, booting with kernel cmdline option drm.vblankoffdelay=0 (or echo 0 > /sys/module/drm/parameters/vblankoffdelay) would keep vblank irqs permanently on to approximate old behavior. Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-07-16drm/nouveau/kms/nv50-: remove duplicate assignmentBen Skeggs1-1/+0
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-07-16drm/nouveau/kms/nv50-: fix drm-get-put.cocci warningskbuild test robot1-1/+1
Use drm_*_get() and drm_*_put() helpers instead of drm_*_reference() and drm_*_unreference() helpers. Generated by: scripts/coccinelle/api/drm-get-put.cocci Fixes: 30ed49b55b6e ("drm/nouveau/kms/nv50-: move code underneath dispnv50/") Signed-off-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Julia Lawall <julia.lawall@lip6.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-07-16drm/nouveau/disp/nv50-gp10x: fix coverity warningBen Skeggs2-3/+3
Change values to u32, there's no need for them to be 64-bit. Reported-by: Colin Ian King <colin.king@canonical.com> Suggested-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-07-16drm/nouveau/core: ERR_PTR vs NULL bug in nvkm_engine_info()Ben Skeggs1-1/+2
Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-07-16drm/nouveau/mmu/gp10b: remove ghost fileJérôme Glisse1-0/+0
This ghost file have been haunting us. Signed-off-by: Jérôme Glisse <jglisse@redhat.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-07-16drm/nouveau/secboot/tegra: Enable gp20b/gp10b firmware tag when relevantNicolas Chauvet2-0/+4
This allows to have the related MODULE_FIRMWARE tag only on relevant arch (arm64). This will saves about 400k on initramfs when not relevant Signed-off-by: Nicolas Chauvet <kwizart@gmail.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-07-16drm/nouveau/fault/gv100: fix fault buffer initialisationBen Skeggs3-13/+19
Not sure how this happened, it worked last time I tested it! Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-07-16drm/nouveau/gr/gv100: handle multiple SM-per-TPC for shader exceptionsBen Skeggs1-7/+14
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-07-06drm/vmwgfx: Expose SM4_1 param to user spaceDeepak Rawat3-3/+10
A new param DRM_VMW_PARAM_SM4_1, is added for user space to determine availability of SM4.1. Minor version bump for SM4.1. Signed-off-by: Deepak Rawat <drawat@vmware.com> Reviewed-by: Sinclair Yeh <syeh@vmware.com> Reviewed-by: Brian Paul <brianp@vmware.com> Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com> Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
2018-07-06drm/vmwgfx: Add support for multisamplingDeepak Rawat3-5/+34
Support for SVGA3D_SURFACE_MULTISAMPLE and surface mob size according to sample count. Signed-off-by: Deepak Rawat <drawat@vmware.com> Reviewed-by: Sinclair Yeh <syeh@vmware.com> Reviewed-by: Brian Paul <brianp@vmware.com> Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com> Reviewed-by: Charmaine Lee <charmainel@vmware.com> Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
2018-07-06drm/vmwgfx: Add new ioctl for GB surface create and referenceDeepak Rawat6-175/+437
New ioctls DRM_VMW_GB_SURFACE_CREATE_EXT and DRM_VMW_GB_SURFACE_REF_EXT are added which support 64-bit wide svga device surface flags, quality level and multisample pattern. Signed-off-by: Deepak Rawat <drawat@vmware.com> Reviewed-by: Sinclair Yeh <syeh@vmware.com> Reviewed-by: Brian Paul <brianp@vmware.com> Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com> Reviewed-by: Charmaine Lee <charmainel@vmware.com> Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
2018-07-06drm/vmwgfx: Support for SVGA3dSurfaceAllFlags in vmwgfxDeepak Rawat2-9/+16
Since svga device introduced new 64bit SVGA3dSurfaceAllFlags, vmwgfx now stores the surface flags internally as SVGA3dSurfaceAllFlags. For legacy surface define commands, only lower 32-bit is used. Signed-off-by: Deepak Rawat <drawat@vmware.com> Reviewed-by: Sinclair Yeh <syeh@vmware.com> Reviewed-by: Brian Paul <brianp@vmware.com> Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com> Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
2018-07-06drm/vmwgfx: Add support for SVGA3dCmdDefineGBSurface_v3Deepak Rawat3-2/+35
SVGA device added new command SVGA3dCmdDefineGBSurface_v3 which allows 64-bit SVGA3dSurfaceAllFlags. This commit adds support for SVGA3dCmdDefineGBSurface_v3 command in vmwgfx. Signed-off-by: Deepak Rawat <drawat@vmware.com> Reviewed-by: Sinclair Yeh <syeh@vmware.com> Reviewed-by: Brian Paul <brianp@vmware.com> Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com> Reviewed-by: Charmaine Lee <charmainel@vmware.com> Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
2018-07-06drm/vmwgfx: Add SM4_1 flagDeepak Rawat2-2/+17
A boolean flag in device private structure to specify if the device support SM4_1. Signed-off-by: Deepak Rawat <drawat@vmware.com> Reviewed-by: Sinclair Yeh <syeh@vmware.com> Reviewed-by: Brian Paul <brianp@vmware.com> Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com> Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
2018-07-06drm/vmwgfx: Add support for SVGA3dCmdIntraSurfaceCopy commandNeha Bhende1-0/+28
A new command to support Intra-Surface-Copy. Signed-off-by: Neha Bhende <bhenden@vmware.com> Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com> Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
2018-07-06drm/vmwgfx: Add CAP2 support in vmwgfxNeha Bhende4-0/+22
The device exposes a new capability register. Add support for it. Signed-off-by: Neha Bhende <bhenden@vmware.com> Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com> Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
2018-07-05drm/amd: Add sphinx documentation for amd_ip_funcsDarren Powell1-18/+27
Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amdgpu: update documentation for amdgpu_drv.cSonny Jiang2-7/+232
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Acked-by: Junwei Zhang <Jerry.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amd/display: add a check for display depth validityMikita Lipski1-0/+42
[why] HDMI 2.0 fails to validate 4K@60 timing with 10 bpc [how] Adding a helper function that would verify if the display depth assigned would pass a bandwidth validation. Drop the display depth by one level till calculated pixel clk is lower than maximum TMDS clk. Bugzilla: https://bugs.freedesktop.org/106959 Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Tested-by: Mike Lothian <mike@fireburn.co.uk> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amd/display: adding ycbcr420 pixel encoding for hdmiMikita Lipski1-2/+5
[why] HDMI EDID's VSDB contains spectial timings for specifically YCbCr 4:2:0 colour space. In those cases we need to verify if the mode provided is one of the special ones has to use YCbCr 4:2:0 pixel encoding for display info. [how] Verify if the mode is using specific ycbcr420 colour space with the help of DRM helper function and assign the mode to use ycbcr420 pixel encoding. Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Tested-by: Mike Lothian <mike@fireburn.co.uk> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amd: Remove errors from sphinx documentationDarren Powell2-10/+15
Eliminating the warnings produced by sphinx when processing the sphinx comments in amdgpu_device.c & amdgpu_mn.c Signed-off-by: Darren Powell <darren.powell@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amd/display/dc/dce: Fix multiple potential integer overflowsGustavo A. R. Silva1-5/+5
Add suffix ULL to constant 5 and cast variables target_pix_clk_khz and feedback_divider to uint64_t in order to avoid multiple potential integer overflows and give the compiler complete information about the proper arithmetic to use. Notice that such constant and variables are used in contexts that expect expressions of type uint64_t (64 bits, unsigned). The current casts to uint64_t effectively apply to each expression as a whole, but they do not prevent them from being evaluated using 32-bit arithmetic instead of 64-bit arithmetic. Also, once the expressions are properly evaluated using 64-bit arithmentic, there is no need for the parentheses that enclose them. Addresses-Coverity-ID: 1460245 ("Unintentional integer overflow") Addresses-Coverity-ID: 1460286 ("Unintentional integer overflow") Addresses-Coverity-ID: 1460401 ("Unintentional integer overflow") Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)") Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amd/display: Use 2-factor allocator callsKees Cook1-4/+4
As already done treewide, switch from open-coded multiplication to 2-factor allocation helper. Signed-off-by: Kees Cook <keescook@chromium.org> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05Revert "drm/amd/display: Fix indentation in dcn10 resource constructor"Harry Wentland1-2/+1
That change was a merge gone bad. This reverts commit cb1d7eacb58f7d1b7d0e57b26dc02d45eada4a3c. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amd/display: off by one in find_irq_source_info()Dan Carpenter1-1/+1
The ->info[] array has DAL_IRQ_SOURCES_NUMBER elements so this condition should be >= instead of > or we could read one element beyond the end of the array. Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amd/pp: Remove the same struct define in powerplayRex Zhu6-60/+27
delete the same struct define in powerplay, share the struct with display. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amd/display: Fix copy error when set memory clocksRex Zhu1-2/+2
Set memory clocks same as soc clocks Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amd/display: Refine the implementation of dm_pp_get_funcs_rvRex Zhu1-40/+40
powerplay/dpm export all interfaces in struct amd_pm_funcs. so call common exported interfaces instead of powerplay inner interfaces Also not include header file hwmgr.h Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amd/pp: Export notify_smu_enable_pwe to displayRex Zhu2-3/+24
Display can notify smu to enable pwe after gpu suspend. It is used in case when display resumes from S3 and wants to start audio driver by enabling pwe Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm: drop drm_pcie_get_speed_cap_mask and drm_pcie_get_max_link_widthAlex Deucher2-65/+0
These functions duplicated functionality which was ultimately added to the pci core. All users of these functions have been ported to using the newly exposed pci functionality. These functions are no longer used, so drop them. Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/radeon: use pcie functions for link widthAlex Deucher6-32/+60
This is the last user of drm_pcie_get_speed_cap_mask. Use the pci version so we can drop drm_pcie_get_speed_cap_mask. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amdgpu: use pcie functions for link width and speedAlex Deucher4-31/+65
Use the newly exported pci functions to get the link width and speed rather than using the drm duplicated versions. Also query the GPU link caps directly rather than hardcoding them. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amdgpu: update amd_pcie.h to include gen4 speedsAlex Deucher1-0/+2
Internal header used by the driver to specify pcie gen speeds of the asic and chipset. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05PCI: Export pcie_get_speed_cap and pcie_get_width_capAlex Deucher2-0/+5
So drivers can use them. This can be used to replace duplicate code in the drm subsystem. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amdgpu: switch firmware path for SI partsAlex Deucher3-46/+46
Use separate firmware path for amdgpu to avoid conflicts with radeon on SI parts. Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amdgpu: switch firmware path for CIK parts (v2)Alex Deucher7-73/+70
Use separate firmware path for amdgpu to avoid conflicts with radeon on CIK parts. v2: squash in logic simplification (Alex) Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amdgpu: fix user fence write race conditionNicolai Hähnle1-6/+6
The buffer object backing the user fence is reserved using the non-user fence, i.e., as soon as the non-user fence is signaled, the user fence buffer object can be moved or even destroyed. Therefore, emit the user fence first. Both fences have the same cache invalidation behavior, so this should have no user-visible effect. Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amd/pp: Remove duplicate code in vega12_hwmgr.cRex Zhu1-42/+1
use smu_helper function smu_set_watermarks_for_clocks_ranges in vega12_set_watermarks_for_clocks_ranges. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amd/pp: Refine the interface exported to displayRex Zhu8-13/+14
use void * as function parameter type in order for extension. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amd/display: Notify powerplay the display controller idrex zhu1-0/+7
powerplay can recalculate the number of active display Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amd/display: Notify powerplay the min_dcef clockrex zhu1-0/+5
powerplay can notify smu to recalculates the maximum deep-sleep divider display allowed. Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amd/pp: Switch the tolerable latency for displayrex zhu1-1/+1
Select the lowest MCLK frequency that is within the tolerable latency defined in DISPALY Acked-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amd/pp: Memory Latency is always 25us on Vega10Rex Zhu1-21/+2
For HBM, 25us latency is enough for memory clock switch. Acked-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amd/pp: Convert clock unit to KHz as definedRex Zhu4-42/+34
Convert clock unit 10KHz to KHz as the data sturct defined. e.g. struct pp_clock_with_latency { uint32_t clocks_in_khz; uint32_t latency_in_us; }; Meanwhile revert the same conversion in display side. Acked-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amdgpu: update uvd_v6_0_ring_vm_funcs to use new nop packetAlex Deucher1-2/+1
Was missed when updating the uvd 6 module. Fixes: 1aac3c9180 (drm/amdgpu: fix insert nop for UVD6 ring) Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2018-07-05drm/amdgpu: fix the wrong type of gem object creationHuang Rui2-4/+4
We still use legacy type of gem_object_create, it should update to ttm_bo_type now. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/radeon: add SPDX identifier and clarify licenseDirk Hohndel (VMware)1-0/+1
This is dual licensed under GPL-2.0 or MIT. Acked-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Dirk Hohndel (VMware) <dirk@hohndel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05drm/amd: add SPDX identifier and clarify licenseDirk Hohndel (VMware)1-0/+1
This is dual licensed under GPL-2.0 or MIT. Acked-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Dirk Hohndel (VMware) <dirk@hohndel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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