aboutsummaryrefslogtreecommitdiffstatshomepage
path: root/tools/perf/scripts/python/export-to-postgresql.py (unfollow)
AgeCommit message (Collapse)AuthorFilesLines
2020-09-30arm64: dts: ti: k3-j7200-common-proc-board: Configure the SERDES lane functionKishon Vijay Abraham I1-0/+6
First two lanes of SERDES is connected to PCIe, third lane is connected to QSGMII and the last lane is connected to USB. However, Cadence torrent SERDES doesn't support more than 2 protocols at the same time. Configure it only for PCIe and QSGMII. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20200930122032.23481-6-rogerq@ti.com
2020-09-30arm64: dts: ti: k3-j7200-main: Add USB controllerRoger Quadros1-0/+30
j7200 has on USB controller instance. Add that. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20200930122032.23481-5-rogerq@ti.com
2020-09-30arm64: dts: ti: k3-j7200-main.dtsi: Add USB to SERDES lane MUXRoger Quadros1-0/+6
The USB controller can be connected to one of the 2 lanes of SERDES0 using a MUX. Add a MUX controller node for that. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20200930122032.23481-4-rogerq@ti.com
2020-09-30arm64: dts: ti: k3-j7200-main: Add SERDES lane control muxRoger Quadros1-0/+15
The SERDES lane control mux registers are present in the CTRLMMR space. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20200930122032.23481-3-rogerq@ti.com
2020-09-30dt-bindings: ti-serdes-mux: Add defines for J7200 SoCRoger Quadros1-0/+22
There are 4 lanes in each J7200 SERDES. Each SERDES lane mux can select upto 4 different IPs. Define all the possible functions. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Peter Rosin <peda@axentia.se> Cc: Peter Rosin <peda@axentia.se> Link: https://lore.kernel.org/r/20200930122032.23481-2-rogerq@ti.com
2020-09-26arm64: dts: apm: add required gpio-cells to DW APB GPIO controller portKrzysztof Kozlowski2-0/+2
The Synopsys DesignWare APB GPIO controller port must have gpio-cells property, as pointed by dtschema: arch/arm64/boot/dts/apm/apm-mustang.dt.yaml: gpio@1c024000: gpio-controller@0: '#gpio-cells' is a required property Link: https://lore.kernel.org/r/20200917165040.22908-2-krzk@kernel.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2020-09-26arm64: dts: apm: drop unused reg-io-width from DW APB GPIO controllerKrzysztof Kozlowski2-2/+0
The Synopsys DesignWare APB GPIO controller driver does not parse reg-io-width and dtschema does not allow it so drop it to fix dtschema warnings like: arch/arm64/boot/dts/apm/apm-mustang.dt.yaml: gpio@1c024000: 'reg-io-width' does not match any of the regexes: '^gpio-(port|controller)@[0-9a-f]+$', 'pinctrl-[0-9]+' Link: https://lore.kernel.org/r/20200917165040.22908-1-krzk@kernel.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2020-09-26ARM: dts: picoxcell: drop unused reg-io-width from DW APB GPIO controllerKrzysztof Kozlowski2-2/+0
The Synopsys DesignWare APB GPIO controller driver does not parse reg-io-width and dtschema does not allow it so drop it to fix dtschema warnings like: arch/arm/boot/dts/picoxcell-pc7302-pc3x2.dt.yaml: gpio@20000: 'reg-io-width' does not match any of the regexes: '^gpio-(port|controller)@[0-9a-f]+$', 'pinctrl-[0-9]+' Link: https://lore.kernel.org/r/20200917164909.22490-1-krzk@kernel.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Jamie Iles <jamie@jamieiles.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2020-09-26ARM: dts: picoxcell: build DTBs with make dtbsKrzysztof Kozlowski1-0/+3
Add ARCH_PICOXCELL entries to Makefil so the DTBs get built with `make dtbs`. Link: https://lore.kernel.org/r/20200917163957.21895-1-krzk@kernel.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Olof Johansson <olof@lixom.net>
2020-09-25arm64: dts: ti: k3-j721e-common-proc-board: align GPIO hog names with dtschemaKrzysztof Kozlowski1-2/+2
The convention for node names is to use hyphens, not underscores. dtschema for pca95xx expects GPIO hogs to end with 'hog' prefix. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20200916155715.21009-7-krzk@kernel.org
2020-09-24arm64: dts: ti: k3-j7200-common-proc-board: Add support for eMMC and SD cardFaiz Abbas1-0/+28
Add support for the eMMC and SD card connected on the common processor board sdhci0 is connected to an eMMC while sdhci1 is connected to the micro SD slot. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Sekhar Nori <nsekhar@ti.com> Link: https://lore.kernel.org/r/20200924112644.11076-3-faiz_abbas@ti.com
2020-09-24arm64: dts: ti: k3-j7200-main: Add support for MMC/SD controller nodesFaiz Abbas1-0/+37
Add support for MMC/SD controller nodes present on TI's j7200 SoCs. There are two nodes: 1. sdhci0 (8 bit bus width, 200 MHz, HS200, 200 MBps) 2. sdhci1 (4 bit bus width, 50 MHz, HS, 25 MBps) Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Sekhar Nori <nsekhar@ti.com> Link: https://lore.kernel.org/r/20200924112644.11076-2-faiz_abbas@ti.com
2020-09-24arm64: dts: ti: k3-j7200-som-p0: Add HyperFlash nodeVignesh Raghavendra1-0/+36
J7200 SoM has a HyperFlash connected to HyperBus memory controller. But HyperBus is muxed with OSPI, therefore keep HyperBus node disabled. Bootloader will detect the mux and enable the node as required. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Sekhar Nori <nsekhar@ti.com> Link: https://lore.kernel.org/r/20200923163150.16973-3-vigneshr@ti.com
2020-09-24arm64: dts: ti: k3-j7200-mcu-wakeup: Add HyperBus nodeVignesh Raghavendra1-0/+27
J7200 has a Flash SubSystem that has one OSPI and one HyperBus.. Add DT nodes for HyperBus controller for now. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Sekhar Nori <nsekhar@ti.com> Link: https://lore.kernel.org/r/20200923163150.16973-2-vigneshr@ti.com
2020-09-24arm64: dts: ti: k3-j7200-common-proc-board: Add I2C IO expandersVignesh Raghavendra1-0/+49
Add DT nodes for I2C GPIO expanders on main_i2c0 and main_i2c1 and also add the pinmux corresponding to these I2C instances. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Faiz Abbas <faiz_abbas@ti.com> Link: https://lore.kernel.org/r/20200923155400.13757-3-vigneshr@ti.com
2020-09-24arm64: dts: ti: k3-j7200: Add I2C nodesVignesh Raghavendra2-0/+110
J7200 has 7 I2Cs in main domain, 2 I2Cs in MCU and 1 in wakeup domain. Add DT nodes for the same. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Faiz Abbas <faiz_abbas@ti.com> Link: https://lore.kernel.org/r/20200923155400.13757-2-vigneshr@ti.com
2020-09-24arm64: dts: ti: k3-j7200-common-proc-board: add mcu cpsw nuss pinmux and phy defsGrygorii Strashko1-0/+45
The TI J7200 EVM base board has TI DP83867 PHY connected to external CPSW NUSS Port 1 in rgmii-rxid mode. Hence, add pinmux and Ethernet PHY configuration for TI J7200 SoC MCU Gigabit Ethernet two ports Switch subsystem (CPSW NUSS). Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com> Link: https://lore.kernel.org/r/20200923220938.30788-5-grygorii.strashko@ti.com
2020-09-24arm64: dts: ti: k3-j7200-mcu: add mcu cpsw nuss nodeGrygorii Strashko1-0/+74
Add DT node for The TI J7200 MCU SoC Gigabit Ethernet two ports Switch subsystem (MCU CPSW NUSS). Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com> Link: https://lore.kernel.org/r/20200923220938.30788-4-grygorii.strashko@ti.com
2020-09-24arm64: dts: ti: k3-j7200-main: add main navss cpts nodeGrygorii Strashko1-0/+12
Add DT node for Main NAVSS CPTS module. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com> Link: https://lore.kernel.org/r/20200923220938.30788-3-grygorii.strashko@ti.com
2020-09-24arm64: dts: ti: k3-j7200: add DMA supportPeter Ujfalusi2-0/+80
Add the ringacc and udmap nodes for Main and MCU NAVSS. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com> Link: https://lore.kernel.org/r/20200923220938.30788-2-grygorii.strashko@ti.com
2020-09-24arm64: dts: qcom: sm8250: Add thermal zones and throttling supportAmit Kucheria1-0/+766
sm8250 has 24 thermal sensors split across two tsens controllers. Add the thermal zones to expose them and wireup the cpus to throttle on crossing passive temperature thresholds. Signed-off-by: Amit Kucheria <amitk@kernel.org> Link: https://lore.kernel.org/r/89b83b3caa4e32db08fe402cfa510feb25232aa0.1599732068.git.amitk@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2020-09-23ARM: dts: stm32: add arm-pmu node on stm32mp15Alexandre Torgue2-0/+13
Add arm-pmu node on stm32mp15. Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Marek Vasut <marex@denx.de> # update to linux-next Tested-by: Marek Vasut <marex@denx.de> # on DH PDK2 and Avenger96 Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-09-23ARM: dts: stm32: add FMC2 EBI support for stm32mp157cChristophe Kerello2-21/+38
This patch adds FMC2 External Bus Interface support on stm32mp157c. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-09-23ARM: dts: stm32: lxa-mc1: enable DDR50 mode on eMMCAhmad Fatoum1-0/+1
The "eMMC high-speed DDR mode (3.3V I/O)" at 50MHz is supported on the eMMC-interface of the lxa-mc1. Set it in the device tree to benefit from the speed improvement. Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Holger Assmann <h.assmann@pengutronix.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-09-23ARM: dts: stm32: Fix DH PDK2 display PWM channelMarek Vasut1-1/+1
The display PWM channel is number 3 (PWM2 CH4), make it so. Fixes: 34e0c7847dcf ("ARM: dts: stm32: Add DH Electronics DHCOM STM32MP1 SoM and PDK2 board") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-09-23ARM: dts: stm32: Enable RTS/CTS for DH AV96 UART7Marek Vasut1-0/+1
The DH AV96 has RTS/CTS lines available on UART7, describe them in DT. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-09-23ARM: dts: stm32: Swap PHY reset GPIO and TSC2004 IRQ on DHCOM SOMMarek Vasut1-2/+2
On the production revision of the SoM, 587-200, the PHY reset GPIO and touchscreen IRQs are swapped to prevent collision between EXTi IRQs, reflect that in DT. Fixes: 34e0c7847dcf ("ARM: dts: stm32: Add DH Electronics DHCOM STM32MP1 SoM and PDK2 board") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-09-23ARM: dts: stm32: use stm32h7 usart compatible string for stm32h743Tobias Schramm1-2/+2
Previously the FIFO on the stm32h743 usart was not utilized, because the stm32f7 compatible configures it without FIFO support. Signed-off-by: Tobias Schramm <t.schramm@manjaro.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-09-23ARM: dts: stm32: add resets property to spi device nodes on stm32h743Tobias Schramm1-0/+6
The stm32 spi driver tries to determine the fifo size of spi devices dynamically. However, if the spi was already configured by the bootloader the fifo size check can become an endless loop, because the driver expects the spi to be in its initial "after device reset" state. The driver does already support resetting the spi device at probe, thus this patch adds only the required device tree properties Signed-off-by: Tobias Schramm <t.schramm@manjaro.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-09-23ARM: dts: stm32: add display controller node to stm32h743Tobias Schramm1-0/+10
Declare LTDC (display controller) on stm32h743. Signed-off-by: Tobias Schramm <t.schramm@manjaro.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-09-23ARM: dts: stm32: Enable RTS/CTS for DH PDK2 UART8Marek Vasut1-1/+2
The DH PDK2 has RTS/CTS lines available on UART8, describe them in DT. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-09-23ARM: dts: stm32: Drop QSPI CS2 pinmux on DHCOMMarek Vasut1-2/+2
The QSPI CS2 is not used on DHCOM, remove the pinmux settings. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-09-23ARM: dts: stm32: Add STM32MP1 UART8 RTS/CTS pinmuxMarek Vasut1-0/+8
Add extra RTS/CTS line pinmux for STM32MP1 UART8. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Acked-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-09-23ARM: dts: stm32: add initial support for stm32mp157-odyssey boardMarcin Sloniewski4-1/+376
Add support for Seeed Studio's stm32mp157c odyssey board. Board consists of SoM with stm32mp157c with 4GB eMMC and 512 MB DDR3 RAM and carrier board with USB and ETH interfaces, SD card connector, wifi and BT chip AP6236. In this patch only basic kernel boot is supported and interfacing SD card and on-board eMMC. Signed-off-by: Marcin Sloniewski <marcin.sloniewski@gmail.com> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-09-23dt-bindings: arm: stm32: document Odyssey compatibleMarcin Sloniewski1-0/+6
Document device tree bindings of Seeed SoM and carrier board. Signed-off-by: Marcin Sloniewski <marcin.sloniewski@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-09-23dt-bindings: vendor-prefixes: add Seeed StudioMarcin Sloniewski1-0/+2
Add the "seeed" vendor prefix for Seeed Technology Co., Ltd Website: https://www.seeedstudio.com/ Signed-off-by: Marcin Sloniewski <marcin.sloniewski@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-09-23ARM: dts: stm32: lxa-mc1: Fix kernel warning about PHY delaysHolger Assmann1-2/+0
The KSZ9031 PHY skew timings for rxc/txc, originally set to achieve the desired phase shift between clock- and data-signal, now trigger a kernel warning when used in rgmii-id mode: *-skew-ps values should be used only with phy-mode = "rgmii" This is because commit bcf3440c6dd7 ("net: phy: micrel: add phy-mode support for the KSZ9031 PHY") now configures own timings when phy-mode = "rgmii-id". Device trees wanting to set their own delays should use phy-mode "rgmii" instead as the warning prescribes. The "standard" timings now used with "rgmii-id" work fine on this board, so drop the explicit timings in the device tree and thereby silence the warning. Fixes: 666b5ca85cd3 ("ARM: dts: stm32: add STM32MP1-based Linux Automation MC-1 board") Signed-off-by: Holger Assmann <h.assmann@pengutronix.de> Acked-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-09-23ARM: dts: stm32: Add USB OTG support to DH PDK2Marek Vasut1-2/+5
The DH PDK2 board is capable of USB OTG on the X14 USB Mini-AB connector, fill in the missing bits to make USB OTG possible instead of peripheral. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-09-23ARM: dts: stm32: Fix sdmmc2 pins on AV96Marek Vasut1-3/+3
The AV96 uses sdmmc2_d47_pins_c and sdmmc2_d47_sleep_pins_c, which differ from sdmmc2_d47_pins_b and sdmmc2_d47_sleep_pins_b in one pin, SDMMC2_D5, which is PA15 in the former and PA9 in the later. The PA15 is correct on AV96, so fix this. This error is likely a result of rebasing across the stm32mp1 DT pinctrl rework. Fixes: 611325f68102 ("ARM: dts: stm32: Add eMMC attached to SDMMC2 on AV96") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-09-23ARM: dts: stm32: Add DHSOM based DRC02 boardMarek Vasut4-2/+195
Add DT for DH DRC02 unit, which is a universal controller device. The system has two ethernet ports, two CANs, RS485 and RS232, USB, capacitive buttons and an OLED display. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-09-23ARM: dts: stm32: Move ethernet PHY into DH SoM DTMarek Vasut2-33/+36
The PHY and the VIO regulator is populated on the SoM, move it into the SoM DT. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-09-23arm64: dts: ti: Add support for J7200 Common Processor BoardLokesh Vutla3-0/+96
Add support for J7200 Common Processor Board. The EVM architecture is very similar to J721E as follows: +------------------------------------------------------+ | +-------------------------------------------+ | | | | | | | Add-on Card 1 Options | | | | | | | +-------------------------------------------+ | | | | | | +-------------------+ | | | | | | | SOM | | | +--------------+ | | | | | | | | | | | Add-on | +-------------------+ | | | Card 2 | | Power Supply | | Options | | | | | | | | | +--------------+ | <--- +------------------------------------------------------+ Common Processor Board Common Processor board is the baseboard that has most of the actual connectors, power supply etc. A SOM (System on Module) is plugged on to the common processor board and this contains the SoC, PMIC, DDR and basic high speed components necessary for functionality. Note: * The minimum configuration required to boot up the board is System On Module(SOM) + Common Processor Board. * Since there is just a single SOM and Common Processor Board, we are maintaining common processor board as the base dts and SOM as the dtsi that we include. In the future as more SOM's appear, we should move common processor board as a dtsi and include configurations as dts. * All daughter cards beyond the basic boards shall be maintained as overlays. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com> Link: https://lore.kernel.org/r/20200914162231.2535-6-lokeshvutla@ti.com
2020-09-23arm64: dts: ti: Add support for J7200 SoCLokesh Vutla3-0/+503
The J7200 SoC is a part of the K3 Multicore SoC architecture platform. It is targeted for automotive gateway, vehicle compute systems, Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications. The SoC aims to meet the complex processing needs of modern embedded products. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, two clusters of lockstep capable dual Cortex-R5F MCUs and a Centralized Device Management and Security Controller (DMSC). * Configurable L3 Cache and IO-coherent architecture with high data throughput capable distributed DMA architecture under NAVSS. * Integrated Ethernet switch supporting up to a total of 4 external ports in addition to legacy Ethernet switch of up to 2 ports. * Upto 1 PCIe-GEN3 controller, 1 USB3.0 Dual-role device subsystems, 20 MCANs, 3 McASP, eMMC and SD, OSPI/HyperBus memory controller, I3C and I2C, eCAP/eQEP, eHRPWM among other peripherals. * One hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL management. See J7200 Technical Reference Manual (SPRUIU1, June 2020) for further details: https://www.ti.com/lit/pdf/spruiu1 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20200914162231.2535-5-lokeshvutla@ti.com
2020-09-23dt-bindings: arm: ti: Add bindings for J7200 SoCLokesh Vutla1-0/+4
The J7200 SoC is a part of the K3 Multicore SoC architecture platform. It is targeted for automotive gateway, vehicle compute systems, Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications. The SoC aims to meet the complex processing needs of modern embedded products. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, two clusters of lockstep capable dual Cortex-R5F MCUs and a Centralized Device Management and Security Controller (DMSC). * Configurable L3 Cache and IO-coherent architecture with high data throughput capable distributed DMA architecture under NAVSS. * Integrated Ethernet switch supporting up to a total of 4 external ports in addition to legacy Ethernet switch of up to 2 ports. * Upto 1 PCIe-GEN3 controller, 1 USB3.0 Dual-role device subsystems, 20 MCANs, 3 McASP, eMMC and SD, OSPI/HyperBus memory controller, I3C and I2C, eCAP/eQEP, eHRPWM among other peripherals. * One hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL management. See J7200 Technical Reference Manual (SPRUIU1, June 2020) for further details: https://www.ti.com/lit/pdf/spruiu1 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Suman Anna <s-anna@ti.com> Link: https://lore.kernel.org/r/20200914162231.2535-4-lokeshvutla@ti.com
2020-09-23dt-bindings: arm: ti: Convert K3 board/soc bindings to DT schemaLokesh Vutla3-27/+32
Convert TI K3 Board/SoC bindings to DT schema format. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Suman Anna <s-anna@ti.com> Link: https://lore.kernel.org/r/20200914162231.2535-3-lokeshvutla@ti.com
2020-09-23arm64: dts: ti: Makefile: Use ARCH_K3 for building dtbsLokesh Vutla1-3/+3
To allow lesser dependency and better maintainability use CONFIG_ARCH_K3 for building dtbs for all K3 based devices. This is as per the discussion in [0]. [0] https://lore.kernel.org/linux-arm-kernel/20200908112534.t5bgrjf7y3a6l2ss@akan/ Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com> Link: https://lore.kernel.org/r/20200914162231.2535-2-lokeshvutla@ti.com
2020-09-23arm64: dts: rockchip: add ir-receiver node to rk3399-khadas-edgeArtem Lapkin1-0/+14
add missed ir-receiver and ir_rx pinctl nodes to rk3399-khadas-edge Khadas Edge board uses gpio-ir-receiver on RK_PB6 gpio Signed-off-by: Artem Lapkin <art@khadas.com> Link: https://lore.kernel.org/r/20200923130823.1612533-3-art@khadas.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-09-23arm64: dts: rockchip: add spiflash node to rk3399-khadas-edgeArtem Lapkin1-0/+10
The Khadas Edge Boards uses winbond - w25q128 spi flash with 104Mhz Signed-off-by: Artem Lapkin <art@khadas.com> Link: https://lore.kernel.org/r/20200923130823.1612533-2-art@khadas.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-09-22arm64: dts: rockchip: Add support for FriendlyARM NanoPi R2SDavid Bauer2-0/+369
This adds support for the NanoPi R2S from FriendlyARM. Rockchip RK3328 SoC 1GB DDR4 RAM Gigabit Ethernet (WAN) Gigabit Ethernet (USB3) (LAN) USB 2.0 Host Port MicroSD slot Reset button WAN - LAN - SYS LED Signed-off-by: David Bauer <mail@david-bauer.net> Link: https://lore.kernel.org/r/20200920154528.88185-2-mail@david-bauer.net [adapted from sdmmc0m1_gpio to renamed sdmmc0m1_pin] Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-09-22dt-bindings: Add doc for FriendlyARM NanoPi R2SDavid Bauer1-0/+5
Add devicetree binding documentation for the FriendlyARM NanoPi R2S. Signed-off-by: David Bauer <mail@david-bauer.net> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200920154528.88185-1-mail@david-bauer.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.