wireguard-linux - WireGuard for the Linux kernel

Age	Commit message (Expand)	Author	Files	Lines
2021-07-27	clk: mediatek: Add MT8192 camsys clock support	Chun-Jie Chen	3	-0/+114
2021-07-27	clk: mediatek: Add MT8192 audio clock support	Chun-Jie Chen	3	-0/+125
2021-07-27	clk: mediatek: Add MT8192 basic clocks support	Chun-Jie Chen	5	-4/+1358
2021-07-27	clk: mediatek: Add mtk_clk_simple_probe() to simplify clock providers	Chun-Jie Chen	2	-0/+31
2021-07-27	clk: mediatek: Add configurable enable control to mtk_pll_data	Chun-Jie Chen	2	-14/+21
2021-07-27	clk: mediatek: Fix asymmetrical PLL enable and disable control	Chun-Jie Chen	1	-4/+16
2021-07-27	clk: mediatek: Get regmap without syscon compatible check	Chun-Jie Chen	4	-4/+4