wireguard-linux - WireGuard for the Linux kernel

Age	Commit message (Expand)	Author	Files	Lines
2022-03-17	RISC-V: Do no continue isa string parsing without correct XLEN	Atish Patra	1	-0/+5
2022-03-17	RISC-V: Implement multi-letter ISA extension probing framework	Atish Patra	2	-6/+34
2022-03-17	RISC-V: Extract multi-letter extension names from "riscv, isa"	Tsukasa OI	1	-8/+27
2022-03-17	RISC-V: Minimal parser for "riscv, isa" strings	Tsukasa OI	1	-11/+61
2022-03-17	RISC-V: Correctly print supported extensions	Tsukasa OI	1	-3/+5
2022-03-10	riscv: Fixed misaligned memory access. Fixed pointer comparison.	Michael T. Kloos	1	-58/+310
2022-03-09	MAINTAINERS: update riscv/microchip entry	Conor Dooley	1	-0/+2
2022-03-09	riscv: dts: microchip: add new peripherals to icicle kit device tree	Conor Dooley	2	-0/+213
2022-03-09	riscv: dts: microchip: update peripherals in icicle kit device tree	Conor Dooley	2	-17/+29
2022-03-09	riscv: dts: microchip: refactor icicle kit device tree	Conor Dooley	2	-50/+52
2022-03-09	riscv: dts: microchip: add fpga fabric section to icicle kit	Conor Dooley	3	-0/+34
2022-03-09	riscv: dts: microchip: use clk defines for icicle kit	Conor Dooley	2	-13/+14