aboutsummaryrefslogtreecommitdiffstatshomepage
path: root/tools/perf/scripts/python/export-to-sqlite.py (unfollow)
AgeCommit message (Expand)AuthorFilesLines
2023-09-28drm/i915: Factor out a helper to check/compute all the CRTC statesImre Deak1-32/+46
2023-09-28drm/i915: Rename intel_modeset_all_pipes() to intel_modeset_all_pipes_late()Imre Deak4-7/+7
2023-09-28drm/i915: Add helper to modeset a set of pipesImre Deak2-21/+83
2023-09-28drm/i915/dp: Limit the output link bpp in DSC modeImre Deak3-0/+12
2023-09-28drm/i915/dp: Update the link bpp limits for DSC modeImre Deak4-22/+108
2023-09-28drm/i915/dp: Skip computing a non-DSC link config if DSC is neededImre Deak2-14/+33
2023-09-28drm/i915/dp: Track the pipe and link bpp limits separatelyImre Deak4-18/+45
2023-09-28drm/i915/dp: Factor out helpers to compute the link limitsImre Deak2-45/+68
2023-09-27drm/i915/dsb: Use DEwake to combat PkgC latencyVille Syrjälä3-14/+82
2023-09-27drm/i915: Introduce intel_crtc_scanline_to_hw()Ville Syrjälä2-0/+15
2023-09-27drm/i915: Introduce skl_watermark_max_latency()Ville Syrjälä2-0/+16
2023-09-27drm/i915/dsb: Evade transcoder undelayed vblank when using DSBVille Syrjälä1-1/+4
2023-09-27drm/i915/dsb: Use non-posted register writes for legacy LUTVille Syrjälä1-0/+11
2023-09-27drm/i915/dsb: Load LUTs using the DSB during vblankVille Syrjälä4-7/+32
2023-09-27drm/i915/dsb: Don't use DSB to load the LUTs during full modesetVille Syrjälä1-0/+4
2023-09-27drm/i915/dsb: Add support for non-posted DSB registers writesVille Syrjälä2-0/+23
2023-09-27drm/i915/dsb: Introduce intel_dsb_reg_write_masked()Ville Syrjälä2-0/+20
2023-09-27drm/i915/dsb: Introduce intel_dsb_noop()Ville Syrjälä2-0/+10
2023-09-27drm/i915/dsb: Define the contents of some intstructions bit betterVille Syrjälä1-4/+8
2023-09-27drm/i915/dsb: Define more DSB bitsVille Syrjälä1-0/+31
2023-09-27drm/i915/dsb: Use non-locked register accessVille Syrjälä1-9/+9
2023-09-26drm/i915/cx0: prefer forward declarations over includesJani Nikula1-6/+8
2023-09-26drm/i915/dp: refactor aux_ch_name()Jani Nikula2-18/+25
2023-09-25drm/i915/irq: Clear GFX_MSTR_IRQ as part of IRQ resetGustavo Sousa1-0/+2
2023-09-25drm/i915: Zap some empty linesTvrtko Ursulin1-7/+0
2023-09-22drm/i915/display: Print display info inside driver display initializationBalasubramani Vivekanandan2-2/+5
2023-09-21drm/i915/bios: Fixup h/vsync_end instead of h/vtotalVille Syrjälä1-8/+15
2023-09-21drm/i915/lnl: Start using CDCLK through PLLStanislav Lisovskiy2-2/+8
2023-09-21drm/i915/xe2lpd: Add DC state supportMatt Roper2-1/+21
2023-09-21drm/i915/xe2lpd: Add display power wellRavi Kumar Vodapalli4-1/+82
2023-09-21drm/i915/lnl: Add CDCLK tableStanislav Lisovskiy1-1/+29
2023-09-21drm/i915/lnl: Add gmbus/ddc supportLucas De Marchi2-2/+6
2023-09-21drm/i915/xe2lpd: Extend Wa_15010685871Lucas De Marchi1-3/+4
2023-09-21drm/i915/xe2lpd: Add support for HPDGustavo Sousa1-2/+19
2023-09-21drm/i915/xe2lpd: Enable odd size and panning for planar yuvJuha-Pekka Heikkilä1-0/+8
2023-09-21drm/i915/xe2lpd: Read pin assignment from IOMLuca Coelho2-0/+29
2023-09-21drm/i915/xe2lpd: Handle port AUX interruptsGustavo Sousa3-4/+8
2023-09-21drm/i915/xe2lpd: Re-order DP AUX regsLucas De Marchi3-9/+24
2023-09-21drm/i915/display: Use _PICK_EVEN_2RANGES() in DP AUX regsLucas De Marchi1-20/+10
2023-09-21drm/i915/display: Fix style and conventions for DP AUX regsLucas De Marchi1-37/+35
2023-09-21drm/i915/xe2lpd: Register DE_RRMR has been removedClint Taylor1-1/+1
2023-09-21drm/i915/xe2lpd: Don't try to program PLANE_AUX_DISTMatt Roper1-1/+1
2023-09-21drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB allocationStanislav Lisovskiy2-10/+12
2023-09-21drm/i915/xe2lpd: Add fake PCHGustavo Sousa2-1/+6
2023-09-21drm/i915: Re-order if/else ladder in intel_detect_pch()Lucas De Marchi1-5/+8
2023-09-21drm/i915/display: Remove FBC capability from fused off pipesClint Taylor1-0/+3
2023-09-21drm/i915/xe2lpd: FBC is now supported on all pipesMatt Roper2-0/+6
2023-09-21drm/i915/lnl: Add display definitionsBalasubramani Vivekanandan1-0/+5
2023-09-21drm/i915/xelpdp: Add XE_LPDP_FEATURESLucas De Marchi1-11/+46
2023-09-21Revert "drm/i915/mst: Populate connector->ddc"Ville Syrjälä1-4/+2
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.