aboutsummaryrefslogtreecommitdiffstatshomepage
path: root/tools/perf/scripts/python/export-to-sqlite.py (unfollow)
AgeCommit message (Expand)AuthorFilesLines
2023-06-20drm/i915: Beef up SDVO/HDMI port checksVille Syrjälä2-5/+29
2023-06-20drm/i915: Assert that the port being initialized is validVille Syrjälä8-0/+24
2023-06-20drm/i915: Assert that device info bitmasks have enough bitsVille Syrjälä1-0/+4
2023-06-20drm/i915: Introduce device info port_maskVille Syrjälä3-50/+113
2023-06-20drm/i915: Remove bogus DDI-F from hsw/bdw output initVille Syrjälä1-2/+0
2023-06-20drm/i915/adlp+: Allow DC states along with PW2 only for PWB functionalityImre Deak1-8/+8
2023-06-16drm/i915/psr: Re-enable PSR1 on hsw/bdwVille Syrjälä1-0/+4
2023-06-16drm/i915/psr: Allow PSR with sprite enabled on hsw/bdwVille Syrjälä2-0/+8
2023-06-16drm/i915/psr: Don't skip both TP1 and TP2/3 on hsw/bdwVille Syrjälä1-0/+9
2023-06-16drm/i915/psr: Do no mask display register writes on hsw/bdwVille Syrjälä1-1/+5
2023-06-16drm/i915/psr: Implement WaPsrDPRSUnmaskVBlankInSRD:hswVille Syrjälä1-0/+8
2023-06-16drm/i915/psr: Implement WaPsrDPAMaskVBlankInSRD:hswVille Syrjälä1-0/+3
2023-06-16drm/i915/psr: Restore PSR interrupt handler for HSWVille Syrjälä1-0/+14
2023-06-16drm/i915/psr: HSW/BDW have no PSR2Ville Syrjälä1-1/+3
2023-06-16drm/i915/psr: Bring back HSW/BDW PSR AUX CH registers/setupVille Syrjälä4-1/+78
2023-06-16drm/i915/psr: Reintroduce HSW PSR1 registersVille Syrjälä2-4/+20
2023-06-16drm/i915/psr: Wrap PSR1 register with functionsVille Syrjälä1-34/+65
2023-06-16drm/i915/psr: Fix BDW PSR AUX CH data register offsetsVille Syrjälä1-1/+1
2023-06-16drm/i915: Re-init clock gating on coming out of PC8+Ville Syrjälä1-3/+3
2023-06-15drm/i915/mtl: Cleanup usage of phy lane resetMika Kahola1-7/+6
2023-06-14drm/i915/hdcp: Modify hdcp_gsc_message msg sending mechanismSuraj Kandpal2-34/+49
2023-06-13drm/i915/dsi: Remove weird has_pch_encoder assertsVille Syrjälä2-4/+0
2023-06-13drm/i915/dsi: Grab the crtc from the customary placeVille Syrjälä1-2/+2
2023-06-13drm/i915/dsi: Move panel reset+power off to be the last thingVille Syrjälä1-6/+8
2023-06-13drm/i915/dsi: Respect power_off_delay on icl+Ville Syrjälä1-0/+2
2023-06-13drm/i915/dsi: Do DSC/scaler disable earlier on icl+Ville Syrjälä1-4/+3
2023-06-13drm/i915/dsi: Move most things from .disable() into .post_disable() on icl+Ville Syrjälä1-9/+10
2023-06-13drm/i915/dsi: Implement encoder->shutdown() for icl+Ville Syrjälä4-7/+9
2023-06-13drm/i915/dsi: Respect power cycle delay on icl+Ville Syrjälä4-14/+20
2023-06-13drm/i915/dsi: Gate DSI clocks earlierVille Syrjälä1-3/+2
2023-06-13drm/i915/dsi: Split icl+ D-PHY vs. DSI timing stepsVille Syrjälä1-26/+42
2023-06-13drm/i915/dsi: Print the VBT MIPI sequence delay durationVille Syrjälä1-1/+1
2023-06-13drm/i915/dsi: Do display on sequence later on icl+Ville Syrjälä1-1/+2
2023-06-13drm/i915/dsi: Do panel power on + reset deassert earlier on icl+Ville Syrjälä1-4/+6
2023-06-13drm/i915/gmch: avoid unused variable warningArnd Bergmann1-3/+1
2023-06-10drm/i915/selftests: add local workqueue for SW fence selftestLuca Coelho1-3/+13
2023-06-10drm/i915: add a dedicated workqueue inside drm_i915_privateLuca Coelho25-54/+110
2023-06-10drm/i915: use pointer to i915 instead of rpm in wakerefLuca Coelho5-20/+20
2023-06-08accel/habanalabs: refactor error info resetDani Liberman3-4/+10
2023-06-08accel/habanalabs: add event queue extra validationOfir Bitton2-1/+7
2023-06-08accel/habanalabs: unsecure TSB_CFG_MTRR regsOfir Bitton1-0/+4
2023-06-08accel/habanalabs: move ioctl error print to debug levelOded Gabbay1-3/+3
2023-06-08accel/habanalabs: fix bug of not fetching addr_dec infoOfir Bitton1-2/+6
2023-06-08accel/habanalabs: add description to several info ioctlsDani Liberman1-0/+10
2023-06-08accel/habanalabs: remove sim codeOded Gabbay2-26/+7
2023-06-08accel/habanalabs: mask part of hmmu page fault captured addressDani Liberman1-3/+11
2023-06-08accel/habanalabs: update state when loading boot fitKoby Elbaz1-15/+10
2023-06-08accel/habanalabs: print qman data on error only for lower qmanTomer Tayar3-128/+31
2023-06-08accel/habanalabs: use lower QM in QM errors handlingTomer Tayar1-5/+5
2023-06-08accel/habanalabs: use binning info when handling razwiDani Liberman1-3/+14
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.