aboutsummaryrefslogtreecommitdiffstatshomepage
path: root/tools/perf/scripts/python/export-to-sqlite.py (unfollow)
AgeCommit message (Expand)AuthorFilesLines
2022-10-27drm/i915/audio: Use intel_de_rmw() for most audio registersVille Syrjälä1-81/+57
2022-10-27drm/i915/audio: Use u32* for ELDVille Syrjälä1-12/+9
2022-10-27drm/i915/audio: Make sure we write the whole ELD bufferVille Syrjälä1-9/+25
2022-10-27drm/i915/audio: Read ELD buffer size from hardwareVille Syrjälä1-7/+45
2022-10-27drm/i915/audio: Nuke intel_eld_uptodate()Ville Syrjälä1-33/+0
2022-10-27drm/i915/audio: Protect singleton register with a lockVille Syrjälä1-0/+7
2022-10-27drm/i915/audio: Unify register bit namingVille Syrjälä2-7/+7
2022-10-27drm/i915/audio: Use REG_BIT() & co.Ville Syrjälä2-51/+45
2022-10-27drm/i915/audio: Extract struct ilk_audio_regsVille Syrjälä1-42/+43
2022-10-27drm/i915/audio: Remove CL/BLC audio stuffVille Syrjälä2-25/+6
2022-10-27drm/i915/audio: Nuke leftover ROUNDING_FACTORVille Syrjälä1-2/+0
2022-10-27drm/i915/audio: s/dev_priv/i915/Ville Syrjälä2-197/+196
2022-10-26drm/i915/display: Move squash_ctl register programming to its own functionAnusha Srivatsa1-9/+14
2022-10-26drm/i915/display: Move chunks of code out of bxt_set_cdclk()Anusha Srivatsa1-15/+24
2022-10-26drm/i915/display: Introduce HAS_CDCLK_SQUASH macroAnusha Srivatsa4-10/+8
2022-10-26drm/i915/display: Change terminology for cdclk actionsAnusha Srivatsa1-8/+8
2022-10-26drm/i915/tgl+: Sanitize DKL PHY register definitionsImre Deak6-152/+159
2022-10-26drm/i915/tgl+: Move DKL PHY register definitions to intel_dkl_phy_regs.hImre Deak7-179/+198
2022-10-26drm/i915: Rename intel_tc_phy_regs.h to intel_mg_phy_regs.hImre Deak4-6/+6
2022-10-26drm/i915/tgl+: Add locking around DKL PHY register accessesImre Deak9-76/+204
2022-10-26drm/i915: Stop loading linear degamma LUT on glk needlesslyVille Syrjälä1-23/+3
2022-10-26drm/i915: Get rid of glk_load_degamma_lut_linear()Ville Syrjälä5-42/+82
2022-10-26drm/i915: Assert {pre,post}_csc_lut were assigned sensiblyVille Syrjälä3-0/+23
2022-10-26drm/i915: Introduce crtc_state->{pre,post}_csc_lutVille Syrjälä6-57/+114
2022-10-26drm/i915: Make ilk_load_luts() deal with degammaVille Syrjälä1-2/+4
2022-10-22drm/i915: Introduce intel_crtc_needs_color_update()Ville Syrjälä4-19/+16
2022-10-22drm/i915: Don't flag both full modeset and fastset at the same timeVille Syrjälä1-1/+8
2022-10-22drm/i915: Remove some local 'mode_changed' boolsVille Syrjälä1-8/+6
2022-10-22drm/i915: Introduce intel_crtc_needs_fastset()Ville Syrjälä7-21/+33
2022-10-22drm/i915: Activate DRRS after state readoutVille Syrjälä1-36/+7
2022-10-21drm/i915: Allow panel fixed modes to have differing sync polaritiesVille Syrjälä1-3/+4
2022-10-21drm/i915: Remove one use macroSuraj Kandpal2-8/+12
2022-10-20drm/i915/dp: Remove whitespace at the end of function.Ankit Nautiyal1-1/+0
2022-10-20drm/i915/dp: Reset frl trained flag before restarting FRL trainingAnkit Nautiyal1-0/+2
2022-10-19drm/i915: Print return value on errorNirmoy Das1-3/+3
2022-10-18drm/i915/dgfx: Keep PCI autosuspend control 'on' by default on all dGPUAnshuman Gupta1-2/+9
2022-10-17drm/i915: fix clear mask in GEN7_MISCCPCTL updateAndrzej Hajda2-4/+4
2022-10-17drm/i915: Use graphics ver, rel info for media on old platformsRadhakrishna Sripada1-1/+9
2022-10-17drm/i915: Add intel_ prefix to struct ip_versionRadhakrishna Sripada3-6/+6
2022-10-17drm/i915: Extend Wa_1607297627 to Alderlake-PJosé Roberto de Souza1-2/+2
2022-10-14drm/i915: Fix simulated GPU reset wrt. encoder HW readoutImre Deak1-7/+17
2022-10-11drm/i915/display: Add DC5 counter and DMC debugfs entries for MTLAnusha Srivatsa1-12/+10
2022-10-11drm/i915: use proper helper for register updatesAndrzej Hajda4-212/+112
2022-10-11drm/i915: make intel_uncore_rmw() write unconditionallyAndrzej Hajda1-4/+4
2022-10-11drm/i915/display: Use intel_uncore alias if definedAndrzej Hajda1-7/+7
2022-10-11drm/i915/display: remove drm_device aliasesAndrzej Hajda15-105/+74
2022-10-10drm/i915: Enable atomic by default on ctg/elkVille Syrjälä1-2/+3
2022-10-10drm/i915: Do the DRIVER_ATOMIC feature disable laterVille Syrjälä2-4/+4
2022-10-07drm/i915: Write watermarks for disabled pipes on gmch platformsVille Syrjälä1-3/+1
2022-10-07drm/i915: Fix pipe gamma enable/disable vs. CxSR on gmch platformsVille Syrjälä1-0/+4
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.