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2019-06-11irqchip/irq-csky-mpintc: Add triger typeGuo Ren1-1/+77
Support 4 triger types: - IRQ_TYPE_LEVEL_HIGH - IRQ_TYPE_LEVEL_LOW - IRQ_TYPE_EDGE_RISING - IRQ_TYPE_EDGE_FALLING All of above could be set in DeviceTree file and it still compatible with the old DeviceTree format. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2019-06-11irqchip/renesas-irqc: Use proper irq_chip name and parentGeert Uytterhoeven1-1/+2
The irq_chip .name field should contain the device's class (not instance) name, while .parent_device should point to the device itself. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2019-06-11irqchip/renesas-intc-irqpin: Use proper irq_chip name and parentGeert Uytterhoeven1-1/+2
The irq_chip .name field should contain the device's class (not instance) name, while .parent_device should point to the device itself. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2019-06-11irqchip/meson-gpio: Add support for Meson-G12A SoCXingyu Chen1-0/+1
The Meson-G12A SoC uses the same GPIO interrupt controller IP block as the other Meson SoCs, A totle of 100 pins can be spied on, which is the sum of: - 223:100 undefined (no interrupt) - 99:97 3 pins on bank GPIOE - 96:77 20 pins on bank GPIOX - 76:61 16 pins on bank GPIOA - 60:53 8 pins on bank GPIOC - 52:37 16 pins on bank BOOT - 36:28 9 pins on bank GPIOH - 27:12 16 pins on bank GPIOZ - 11:0 12 pins in the AO domain Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com> Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2019-06-11dt-bindings: interrupt-controller: New binding for Meson-G12A SoCXingyu Chen1-0/+1
Update the dt-binding document to support new compatible string for the GPIO interrupt controller which found in Amlogic's Meson-G12A SoC. Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com> Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2019-06-11irqchip: Enable compile-testing for Renesas driversGeert Uytterhoeven1-4/+16
Enable compile-testing for all Renesas interrupt controller drivers, except for RENESAS_H8300H_INTC. The latter relies on a function (ctrl_bclr()) that is not available on other architectures. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2019-06-11irqchip/gic-v2m: Add support for Amazon Graviton variant of GICv3+GICv2mZeev Zilberman4-20/+76
Add support for Amazon Graviton custom variant of GICv2m, where the message is encoded using the MSI message address, as opposed to standard GICv2m, where the SPI number is encoded in the MSI message data. In addition, the Graviton flavor of GICv2m is used along GICv3 (and not GICv2). Co-developed-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Zeev Zilberman <zeev@amazon.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2019-05-29irqchip/renesas-irqc: Convert to managed initializationsGeert Uytterhoeven1-39/+15
Simplify error handling by converting the driver to use managed allocations and initializations. Note that platform_get_resource() and ioremap_nocache() are combined in devm_platform_ioremap_resource(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2019-05-29irqchip/renesas-irqc: Replace irqc_priv.pdev by irqc_priv.devGeert Uytterhoeven1-4/+3
Nothing really uses irqc_priv.pdev, all users need irqc_priv.pdev->dev. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2019-05-29irqchip/renesas-irqc: Add helper variable dev = &pdev->devGeert Uytterhoeven1-13/+13
The probe function uses "&pdev->dev" a lot, hence add a shorthand for that. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2019-05-29irqchip/renesas-irqc: Remove error messages on out-of-memory conditionsGeert Uytterhoeven1-2/+0
There is no need to print error messages if kzalloc() or ioremap_nocache() fail, as the memory allocation core already takes care of that. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2019-05-29irqchip/renesas-irqc: Remove unneeded inclusion of <linux/spinlock.h>Geert Uytterhoeven1-1/+0
The driver never used spinlocks, and thus does not need to include <linux/spinlock.h>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2019-05-29irqchip: Add Renesas RZ/A1 Interrupt Controller driverGeert Uytterhoeven3-0/+288
Add a driver for the Renesas RZ/A1 Interrupt Controller. This supports using up to 8 external interrupts on RZ/A1, with configurable sense select. NMI edge select is not yet supported. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>