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2023-06-13clk: qcom: clk-alpha-pll: Add a way to update some bits of test_ctl(_hi)Konrad Dybcio2-4/+17
The "vanilla" Alpha PLL configs are sometimes provided with an intention to only update certain bits of th register. Do so if a mask is found. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Iskren Chernev <me@iskren.info> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230601-topic-alpha_ctl-v1-1-b6a932dfcf68@linaro.org
2023-06-13clk: qcom: gcc-ipq6018: remove duplicate initializersArnd Bergmann1-2/+0
A recent change added new initializers for .config_ctl_val and .config_ctl_hi_val but left the old values in place: drivers/clk/qcom/gcc-ipq6018.c:4155:27: error: initialized field overwritten [-Werror=override-init] 4155 | .config_ctl_val = 0x240d4828, | ^~~~~~~~~~ drivers/clk/qcom/gcc-ipq6018.c:4156:30: error: initialized field overwritten [-Werror=override-init] 4156 | .config_ctl_hi_val = 0x6, | ^~~ Remove the unused ones now to avoid confusion. Fixes: f4f0c8acee0e4 ("clk: qcom: gcc-ipq6018: update UBI32 PLL") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230601213416.3373599-1-arnd@kernel.org
2023-06-13clk: qcom: gcc-ipq9574: Enable crypto clocksAnusha Rao1-0/+72
Enable the clocks required for crypto operation. Reviewed-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230526161129.1454-3-quic_anusha@quicinc.com
2023-06-13dt-bindings: clock: Add crypto clock and reset definitionsAnusha Rao2-0/+5
Add crypto clock and reset ID definitions for ipq9574. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230526161129.1454-2-quic_anusha@quicinc.com
2023-06-13clk: qcom: Add lpass audio clock controller driver for SC8280XPSrinivas Kandagatla1-0/+23
Add support for the lpass audio clock controller found on SC8280XP based devices. This would allow lpass peripheral loader drivers to control the clocks and bring the subsystems out of reset. Currently this patch only supports resets as the Q6DSP is in control of LPASS IP which manages most of the clocks via Q6PRM service on GPR rpmsg channel. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230608125315.11454-5-srinivas.kandagatla@linaro.org
2023-06-13clk: qcom: Add lpass clock controller driver for SC8280XPSrinivas Kandagatla3-0/+74
Add support for the lpass clock controller found on SC8280XP based devices. This would allow lpass peripheral loader drivers to control the clocks and bring the subsystems out of reset. Currently this patch only supports resets as the Q6DSP is in control of LPASS IP which manages most of the clocks via Q6PRM service on GPR rpmsg channel. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230608125315.11454-4-srinivas.kandagatla@linaro.org
2023-06-13dt-bindings: clock: qcom,mmcc: define clocks/clock-names for MSM8226Luca Weiss1-2/+30
Define clock/clock-names properties of the MMCC device node to be used on MSM8226 platform. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Acked-by: Jeffrey Hugo <quic_jhugo@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230509-msm8226-mmcc-parents-v1-2-83a2dfc986ab@z3ntu.xyz
2023-05-26clk: qcom: gpucc-sm8550: Add support for graphics clock controllerJagadeesh Kona3-0/+620
Add support for gpucc driver on SM8550, which provides clocks for the graphics subsystem. Co-developed-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230524181800.28717-3-quic_jkona@quicinc.com
2023-05-26clk: qcom: Add support for SM8450 GPUCCKonrad Dybcio3-0/+775
The GPUCC manages the clocks for the Adreno GPU found on the sm8450 SoCs. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230517-topic-waipio-gpucc-v1-4-4f40e282af1d@linaro.org
2023-05-26clk: qcom: gcc-sm8450: Enable hw_clk_ctrlKonrad Dybcio1-0/+39
Enable hardware clock control on all RCGs. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230517-topic-waipio-gpucc-v1-3-4f40e282af1d@linaro.org
2023-05-26clk: qcom: rcg2: Make hw_clk_ctrl toggleableKonrad Dybcio2-0/+4
Certain SoCs use the HW_CLK_CTRL feature on some of the clocks they host. This allows the clocks to be turned on automatically when a downstream branch tries to change rate or config. Make it togglable so that we can utilize this. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230517-topic-waipio-gpucc-v1-2-4f40e282af1d@linaro.org
2023-05-26dt-bindings: clock: qcom: Add SM8550 graphics clock controllerJagadeesh Kona2-0/+50
Add device tree bindings for the graphics clock controller on Qualcomm SM8550 platform. Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230524181800.28717-2-quic_jkona@quicinc.com
2023-05-26dt-bindings: clock: Add Qcom SM8450 GPUCCKonrad Dybcio3-0/+141
Add device tree bindings for the graphics clock controller on Qualcomm Technology Inc's SM8450 SoCs. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230517-topic-waipio-gpucc-v1-1-4f40e282af1d@linaro.org
2023-05-26clk: qcom: mmcc-msm8974: use clk_rcg2_shared_ops for mdp_clk_src clockDmitry Baryshkov1-1/+1
The mdp_clk_src clock should not be turned off. Instead it should be 'parked' to the XO, as most of other mdp_clk_src clocks. Fix that by using the clk_rcg2_shared_ops. Fixes: d8b212014e69 ("clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC)") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Luca Weiss <luca@z3ntu.xyz> Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230507175335.2321503-1-dmitry.baryshkov@linaro.org
2023-05-26clk: qcom: ipq5332: fix the order of SLEEP_CLK and XO clockKathiravan T1-1/+1
The order of DT_SLEEP_CLK and DT_XO are swapped and it is incorrect. Due to which the clocks for which the parent should be XO is having parent as SLEEP_CLK and vice versa. So fix the same by re-ordering the entries. Fixes: 3d89d52970fd ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC") Reported-by: Devi Priya <quic_devipriy@quicinc.com> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230417105607.4091-1-quic_kathirav@quicinc.com
2023-05-26clk: qcom: ipq5332: fix the src parameter in ftbl_gcc_apss_axi_clk_srcKathiravan T1-1/+1
480MHz is derived from P_GPLL4_OUT_AUX not from P_GPLL4_OUT_MAIN. Update the freq_tbl with the correct src. Fixes: 3d89d52970fd ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC") Reported-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230417044342.9406-1-quic_kathirav@quicinc.com
2023-05-26clk: qcom: dispcc-qcm2290: Fix GPLL0_OUT_DIV handlingKonrad Dybcio1-3/+4
GPLL0_OUT_DIV (.fw_name = "gcc_disp_gpll0_div_clk_src") was previously made to reuse the same parent enum entry as GPLL0_OUT_MAIN (.fw_name = "gcc_disp_gpll0_clk_src") in parent_map_2. Resolve it by introducing its own entry in the parent enum and correctly assigning it in disp_cc_parent_map_2[]. Fixes: cc517ea3333f ("clk: qcom: Add display clock controller driver for QCM2290") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230412-topic-qcm_dispcc-v2-2-bce7dd512fe4@linaro.org
2023-05-26clk: qcom: dispcc-qcm2290: Fix BI_TCXO_AO handlingKonrad Dybcio1-2/+3
BI_TCXO_AO (.fw_name = "bi_tcxo_ao") was previously made to reuse the same parent enum entry as BI_TCXO (.fw_name = "bi_tcxo") in parent_map_2. Resolve it by introducing its own entry in the parent enum and correctly assigning it in disp_cc_parent_map_2[]. Fixes: cc517ea3333f ("clk: qcom: Add display clock controller driver for QCM2290") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230412-topic-qcm_dispcc-v2-1-bce7dd512fe4@linaro.org
2023-05-26clk: qcom: ipq6018: fix networking resetsRobert Marko1-16/+16
Networking resets in IPQ6018 all use bitmask as they require multiple bits to be set and cleared instead of a single bit. So, current networking resets have the same register and bit 0 set which is clearly incorrect. Fixes: d9db07f088af ("clk: qcom: Add ipq6018 Global Clock Controller support") Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230526190855.2941291-2-robimarko@gmail.com
2023-05-26clk: qcom: gcc-ipq6018: update UBI32 PLLRobert Marko1-1/+6
Update the UBI32 alpha PLL config to the latest values from the downstream QCA 5.4 kernel. Signed-off-by: Robert Marko <robimarko@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230526190855.2941291-1-robimarko@gmail.com
2023-05-26clk: qcom: apss-ipq-pll: Add support for IPQ9574Devi Priya1-0/+19
Add the compatible and configuration values for A73 Huayra PLL found on IPQ9574. Co-developed-by: Praveenkumar I <quic_ipkumar@quicinc.com> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230406061314.10916-3-quic_devipriy@quicinc.com
2023-05-26dt-bindings: clock: qcom,a53pll: add IPQ9574 compatibleDevi Priya1-0/+1
IPQ9574 uses A73 PLL of type Huayra. Add the IPQ9574 A73 compatible to A53 bindings as the PLL properties match with that of A53. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230406061314.10916-2-quic_devipriy@quicinc.com
2023-05-24dt-bindings: clock: qcom,gcc-sc7280: document CX power domainKrzysztof Kozlowski1-0/+7
The GCC clock controller needs CX power domain, at least according to DTS: sc7280-herobrine-crd-pro.dtb: clock-controller@100000: Unevaluated properties are not allowed ('power-domains' was unexpected) Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230516105241.30091-3-krzysztof.kozlowski@linaro.org
2023-05-24dt-bindings: clock: qcom,gcc-sc7180: document CX power domainKrzysztof Kozlowski1-0/+7
The GCC clock controller needs CX power domain, at least according to DTS: sc7180-trogdor-pompom-r3.dtb: clock-controller@100000: Unevaluated properties are not allowed ('power-domains' was unexpected) Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230516105241.30091-2-krzysztof.kozlowski@linaro.org
2023-05-24dt-bindings: clock: qcom,gcc-sm8250: add missing bi_tcxo_ao clockKrzysztof Kozlowski1-1/+4
The initial SM8250 GCC driver added in commit 3e5770921a88 ("clk: qcom: gcc: Add global clock controller driver for SM8250") already consumed it on the clock. This fixes warnings like: sm8250-xiaomi-elish-csot.dtb: clock-controller@100000: clock-names: ['bi_tcxo', 'bi_tcxo_ao', 'sleep_clk'] is too long Fixes: 98394efb48f5 ("dt-bindings: clock: Add SM8250 GCC clock bindings") Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230516105241.30091-1-krzysztof.kozlowski@linaro.org
2023-05-24clk: qcom: restrict drivers per ARM/ARM64Krzysztof Kozlowski1-0/+71
There is no point to allow selecting clock controller drivers for Qualcomm ARMv7 SoCs when building ARM64 kernel, and vice versa. This makes kernel configuration more difficult as many do not remember the Qualcomm SoCs model names/numbers. No features should be lost because: 1. There won't be a single image for ARMv7 and ARMv8/9 SoCs. 2. Newer ARMv8/9 SoCs won't be running in arm32 emulation mode. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230514114711.18258-1-krzysztof.kozlowski@linaro.org
2023-05-24clk: qcom: Add GCC driver support for SDX75Imran Shaik3-0/+2979
Add Global Clock Controller (GCC) support for SDX75 platform. Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230512122347.1219-6-quic_tdas@quicinc.com
2023-05-24clk: qcom: rpmh: Add RPMH clocks support for SDX75Imran Shaik1-0/+19
Add support for RPMH clocks for SDX75 platform. Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230512122347.1219-5-quic_tdas@quicinc.com
2023-05-24dt-bindings: clock: qcom: Add RPMHCC for SDX75Imran Shaik1-0/+1
Add compatible string for qcom RPMHCC for SDX75 platform. Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230512122347.1219-4-quic_tdas@quicinc.com
2023-05-24clk: qcom: branch: Extend the invert logic for branch2 clocksImran Shaik1-3/+3
Add support to handle the invert logic for branch2 clocks. Invert branch halt would indicate the clock ON when CLK_OFF bit is '1' and OFF when CLK_OFF bit is '0'. Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230512122347.1219-2-quic_tdas@quicinc.com
2023-05-24clk: qcom: smd-rpm: conditionally enable scaling before doing handoverLuca Weiss1-3/+13
On older platforms like msm8226, msm8974 and msm8916 the driver in the downstream kernel enables scaling first before doing the handover of the clocks. While this normally doesn't seem to cause noticeable problems, on apq8026-asus-sparrow this causes the device to immediately reboot, perhaps due to older rpm firmware that becomes unhappy. On newer platforms the order has swapped and enabling scaling is done after the handover, so let's introduce this behavior only conditionally for msm8226 and msm8974 for now. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230506-rpmcc-scaling-handover-v1-1-374338a8dfd9@z3ntu.xyz
2023-05-24clk: qcom: gcc-sdm660: drop redundant F defineChristian Marangi1-2/+0
The same exact F frequency table entry is defined in clk-rcg.h Drop the redundant define to cleanup code. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230417174408.23722-2-ansuelsmth@gmail.com
2023-05-24clk: qcom: gcc-ipq6018: drop redundant F defineChristian Marangi1-2/+0
The same exact F frequency table entry is defined in clk-rcg.h Drop the redundant define to cleanup code. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230417174408.23722-1-ansuelsmth@gmail.com
2023-05-24dt-bindings: clock: qcom,gcc-msm8953: split to separate schemaKrzysztof Kozlowski2-1/+73
The Qualcomm MSM8953 GCC clock controller has clock inputs, thus existing gcc-other.yaml was not describing it fully. Move the binding to its own schema file and document the clocks based on DTS. Add driver contributors as its maintainers. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230408143729.84097-1-krzysztof.kozlowski@linaro.org
2023-05-24clk: qcom: gcc-qcm2290: Mark RCGs shared where applicableKonrad Dybcio1-31/+31
The vast majority of shared RCGs were not marked as such. Fix it. Fixes: 496d1a13d405 ("clk: qcom: Add Global Clock Controller driver for QCM2290") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230403174807.345185-1-konrad.dybcio@linaro.org
2023-05-24clk: qcom: videocc-sm8550: Add video clock controller driver for SM8550Jagadeesh Kona3-0/+481
Add support for the video clock controller for video clients to be able to request for videocc clocks on SM8550 platform. Co-developed-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230524145203.13153-4-quic_jkona@quicinc.com
2023-05-24dt-bindings: clock: qcom: Add SM8550 video clock controllerJagadeesh Kona1-1/+3
Add compatible string for SM8550 video clock controller. Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230524145203.13153-3-quic_jkona@quicinc.com
2023-05-24clk: qcom: clk-alpha-pll: Add support to configure PLL_TEST_CTL_U2Jagadeesh Kona2-0/+3
The lucid ole pll reuses lucid evo ops but it has an additional test control register which is required to be programmed, add support to program the same. Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230524145203.13153-2-quic_jkona@quicinc.com
2023-05-24clk: qcom: videocc-sm8450: Add video clock controller driver for SM8450Taniya Das3-0/+473
Add support for the video clock controller driver for peripheral clock clients to be able to request for video cc clocks. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230524140656.7076-3-quic_tdas@quicinc.com
2023-05-24clk: qcom: Introduce SM8350 VIDEOCCKonrad Dybcio3-0/+562
Add support for the Video Clock Controller found on the SM8350 SoC. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230413-topic-lahaina_vidcc-v4-2-86c714a66a81@linaro.org
2023-05-24dt-bindings: clock: Add SM8350 VIDEOCCKonrad Dybcio3-0/+121
SM8350, like most recent higher-end chips has a separate clock controller block just for the Venus IP. Document it. The binding was separated as the driver, unlike the earlier ones, doesn't expect clock-names to keep it easier to maintain. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230413-topic-lahaina_vidcc-v4-1-86c714a66a81@linaro.org
2023-05-24dt-bindings: clock: qcom: Add SM8450 video clock controllerTaniya Das2-0/+115
Add device tree bindings for the video clock controller on Qualcomm SM8450 platform. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230524140656.7076-2-quic_tdas@quicinc.com
2023-05-24dt-bindings: clock: qcom: Add GCC clocks for SDX75Imran Shaik2-0/+258
Add support for qcom global clock controller bindings for SDX75 platform. Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230512122347.1219-3-quic_tdas@quicinc.com
2023-05-24clk: qcom: gcc-ipq6018: Use floor ops for sdcc clocksMantas Pucka1-1/+1
SDCC clocks must be rounded down to avoid overclocking the controller. Fixes: d9db07f088af ("clk: qcom: Add ipq6018 Global Clock Controller support") Signed-off-by: Mantas Pucka <mantas@8devices.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1682413909-24927-1-git-send-email-mantas@8devices.com
2023-05-24clk: qcom: smd-rpm: Make BI_TCXO_AO criticalKonrad Dybcio1-1/+2
We should never let go of the active-only XO vote, as otherwise the RPM may decide that there are no online users and it can be shut down, resulting in a total, uncontrolled system collapse. Guarantee this through adding the CLK_IS_CRITICAL flag. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Matti Lehtimäki <matti.lehtimaki@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230501-topic-rpmcc_xo_a-v1-3-93f18e47b607@linaro.org
2023-05-24clk: qcom: smd-rpm: Make DEFINE_CLK_SMD_RPM_BRANCH_A accept flagsKonrad Dybcio1-4/+4
In preparation for supporting keepalive clocks which can never be shut off (as the platform would fall apart otherwise), make the DEFINE_CLK_SMD_RPM_BRANCH_A macro accept clock flags for the active-only clock. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Matti Lehtimäki <matti.lehtimaki@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230501-topic-rpmcc_xo_a-v1-2-93f18e47b607@linaro.org
2023-05-24clk: qcom: smd-rpm_ Make __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX accept flagsKonrad Dybcio1-5/+6
In preparation for supporting keepalive clocks which can never be shut off (as the platform would fall apart otherwise), make the __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX macro accept clock flags for the active-only clock. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Matti Lehtimäki <matti.lehtimaki@gmail.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230501-topic-rpmcc_xo_a-v1-1-93f18e47b607@linaro.org
2023-05-24clk: qcom: smd-rpm: Keep one rpm handle for all clocksKonrad Dybcio1-14/+12
For no apparent reason (as there's just one RPM per SoC), all clocks currently store a copy of a pointer to smd_rpm. Introduce a single, global one to save up on space in each clk definition. bloat-o-meter reports: Total: Before=41887, After=40843, chg -2.49% Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230501130400.107771-1-konrad.dybcio@linaro.org
2023-05-24clk: qcom: camcc-sc7180: Add parent dependency to all camera GDSCsTaniya Das1-7/+12
Camera titan top GDSC is a parent supply to all other camera GDSCs. Titan top GDSC is required to be enabled before enabling any other camera GDSCs and it should be disabled only after all other camera GDSCs are disabled. Ensure this behavior by marking titan top GDSC as parent of all other camera GDSCs. Fixes: 15d09e830bbc ("clk: qcom: camcc: Add camera clock controller driver for SC7180") Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230501142932.13049-1-quic_tdas@quicinc.com
2023-05-24clk: qcom: mmcc-msm8974: remove oxili_ocmemgx_clkDmitry Baryshkov1-19/+0
After the internal discussions, it looks like this clock is managed by RPM itself. Linux kernel should not touch it on its own, as this causes disagreement with RPM. Shutting down this clock causes the OCMEM<->GPU interface to stop working, resulting in GPU hangchecks/timeouts. Fixes: d8b212014e69 ("clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC)") Suggested-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Luca Weiss <luca@z3ntu.xyz> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230508153319.2371645-1-dmitry.baryshkov@linaro.org
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