wireguard-linux - WireGuard for the Linux kernel

Age	Commit message (Expand)	Author	Files	Lines
2017-11-14	clk: hisilicon: Delete an error message for a failed memory allocation in hisi_register_clkgate_sep()	Markus Elfring	1	-3/+1
2017-11-14	clk: hi3660: fix incorrect uart3 clock freqency	Zhong Kaihua	1	-1/+1
2017-11-01	clk: sunxi: explicitly request exclusive reset control	Philipp Zabel	1	-1/+1
2017-11-01	clk: sunxi: fix build warning	Corentin LABBE	1	-2/+0
2017-11-01	clk: hi6220: mark clock cs_atb_syspll as critical	Leo Yan	1	-1/+1
2017-11-01	clk: tegra: Use readl_relaxed_poll_timeout_atomic() in tegra210_clock_init()	Nicolin Chen	1	-2/+2
2017-11-01	clk: tegra: dfll: Fix drvdata overwriting issue	Nicolin Chen	3	-13/+11
2017-11-01	clk: tegra: Fix cclk_lp divisor register	Michał Mirosław	1	-1/+1
2017-11-01	clk: tegra: Bump SCLK clock rate to 216 MHz	Dmitry Osipenko	1	-1/+1
2017-11-01	clk: tegra: Use common definition of APBDMA clock gate	Dmitry Osipenko	1	-5/+1
2017-11-01	clk: tegra: Correct parent of the APBDMA clock	Dmitry Osipenko	1	-1/+1
2017-11-01	clk: tegra: Add AHB DMA clock entry	Dmitry Osipenko	4	-0/+4
2017-11-01	clk: tegra: Mark APB clock as critical	Jon Hunter	1	-1/+1
2017-10-20	clk: renesas: rcar-gen3: Restore R clock during resume	Geert Uytterhoeven	1	-2/+11
2017-10-20	clk: renesas: rcar-gen3: Restore SDHI clocks during resume	Geert Uytterhoeven	1	-13/+50
2017-10-20	clk: renesas: div6: Restore clock state during resume	Geert Uytterhoeven	3	-4/+40
2017-10-20	clk: renesas: cpg-mssr: Add support to restore core clocks during resume	Geert Uytterhoeven	6	-11/+23
2017-10-20	clk: renesas: cpg-mssr: Restore module clocks during resume	Geert Uytterhoeven	1	-0/+84
2017-10-20	MAINTAINERS: Add git repository to Renesas clock driver section	Geert Uytterhoeven	1	-0/+1
2017-10-20	clk: renesas: cpg-mssr: Add du1 clock to R8A7745	Fabrizio Castro	1	-0/+1
2017-10-20	clk: renesas: rz: clk-rz is meant for RZ/A1	Geert Uytterhoeven	2	-3/+3
2017-10-20	clk: meson: gxbb: Add VPU and VAPB clocks data	Neil Armstrong	1	-0/+292
2017-10-20	clk: meson: gxbb: Add VPU and VAPB clockids	Neil Armstrong	2	-1/+16
2017-10-19	clk: tegra: Make tegra_clk_pll_params __ro_after_init	Bhumika Goyal	1	-8/+8
2017-10-19	clk: tegra: Fix sor1_out clock implementation	Thierry Reding	2	-16/+47
2017-10-19	clk: tegra: Use tegra_clk_register_periph_data()	Thierry Reding	4	-13/+4
2017-10-19	clk: tegra: Add peripheral clock registration helper	Thierry Reding	2	-0/+11
2017-10-19	clk: tegra: Check BPMP response return code	Timo Alho	1	-5/+10
2017-10-17	clk: sunxi-ng: sun4i: Export video PLLs	Jonathan Liu	2	-2/+4
2017-10-17	clk: sunxi-ng: Add A83T display clocks	Maxime Ripard	1	-8/+13
2017-10-17	dt-bindings: clock: tegra: Add sor1_out clock	Thierry Reding	1	-0/+1
2017-10-17	firmware: tegra: Propagate error code to caller	Timo Alho	2	-6/+17
2017-10-16	clk: samsung: Add a separate driver for Exynos4412 ISP clocks	Marek Szyprowski	2	-0/+180
2017-10-16	clk: samsung: Add dt bindings for Exynos4412 ISP clock controller	Marek Szyprowski	2	-0/+78
2017-10-16	clk: samsung: Instantiate Exynos4412 ISP clocks only when available	Marek Szyprowski	1	-7/+24
2017-10-16	clk: renesas: r8a77995: Correct parent clock of INTC-AP	Geert Uytterhoeven	1	-1/+1
2017-10-16	clk: renesas: r8a7796: Correct parent clock of INTC-AP	Geert Uytterhoeven	1	-1/+1
2017-10-16	clk: renesas: r8a7795: Correct parent clock of INTC-AP	Geert Uytterhoeven	1	-1/+2
2017-10-14	clk: rockchip: use new cif/vdpu clock ids on rk3188	Heiko Stuebner	1	-6/+6
2017-10-14	clk: rockchip: export clock pclk_efuse_256 for RK3368 SoCs	Romain Perier	1	-1/+1
2017-10-14	clk: rockchip: add more rk3188 graphics clock ids	Heiko Stuebner	1	-2/+7
2017-10-14	clk: rockchip: add clock id for PCLK_EFUSE256 of RK3368 SoCs	Romain Perier	1	-0/+1
2017-10-13	clk: sunxi-ng: sun8i: a23: Use sigma-delta modulation for audio PLL	Chen-Yu Tsai	1	-13/+25
2017-10-13	clk: sunxi-ng: sun6i: Use sigma-delta modulation for audio PLL	Chen-Yu Tsai	1	-13/+25
2017-10-13	clk: sunxi-ng: sun5i: Use sigma-delta modulation for audio PLL	Chen-Yu Tsai	1	-6/+19
2017-10-13	clk: sunxi-ng: sun4i: Use sigma-delta modulation for audio PLL	Chen-Yu Tsai	1	-6/+20
2017-10-13	clk: sunxi-ng: sun8i: h3: Use sigma-delta modulation for audio PLL	Chen-Yu Tsai	1	-13/+25
2017-10-13	clk: sunxi-ng: nm: Add support for sigma-delta modulation	Chen-Yu Tsai	2	-1/+46
2017-10-13	clk: sunxi-ng: Add sigma-delta modulation support	Chen-Yu Tsai	4	-0/+240
2017-10-13	clk: sunxi-ng: nm: Check if requested rate is supported by fractional clock	Chen-Yu Tsai	1	-0/+3