From e0f250c8fd012b010cdae0535903402765f7ffe5 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 30 May 2023 19:49:44 -0700 Subject: arm64: dts: qcom: Drop undocumented "svid" property The Linux typec_mux implementation required that a property named "svid" was present in the remote node of the of_graph for a match to be found. With the introduction of commit '4aebc4f89f00 ("usb: typec: mux: Clean up mux_fwnode_match()")', the implementation is aligned with the binding and this property can be dropped - and the associated DeviceTree validation warning resolved. Signed-off-by: Bjorn Andersson Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20230531024944.4105769-1-quic_bjorande@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 2 -- arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 2 -- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 1 - arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 1 - 4 files changed, 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index b566e403d1db..4fb5e240275d 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -234,7 +234,6 @@ mode-switch; orientation-switch; - svid = /bits/ 16 <0xff01>; port { usb0_sbu_mux: endpoint { @@ -254,7 +253,6 @@ mode-switch; orientation-switch; - svid = /bits/ 16 <0xff01>; port { usb1_sbu_mux: endpoint { diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 7cc3028440b6..6b5a7de6a27d 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -334,7 +334,6 @@ mode-switch; orientation-switch; - svid = /bits/ 16 <0xff01>; port { usb0_sbu_mux: endpoint { @@ -354,7 +353,6 @@ mode-switch; orientation-switch; - svid = /bits/ 16 <0xff01>; port { usb1_sbu_mux: endpoint { diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index 61dd9663fabe..b182f4cf06cc 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -348,7 +348,6 @@ vcc-supply = <&vreg_bob>; mode-switch; orientation-switch; - svid = /bits/ 16 <0xff01>; ports { #address-cells = <1>; diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index bc4c125d1832..d7975b3cf064 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -517,7 +517,6 @@ vcc-supply = <&vreg_bob>; mode-switch; orientation-switch; - svid = /bits/ 16 <0xff01>; ports { #address-cells = <1>; -- cgit v1.2.3-59-g8ed1b From 0c55f6229bc3a17c48c7c488805d98f253ab61d3 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 6 Jun 2023 19:29:19 +0200 Subject: arm64: dts: qcom: qcm2290: Add USB3 PHY Describe the USB3 PHY and hook it up to the USB3 controller. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230606-topic-qcm2290_usb3-v1-1-3e8fbcb89088@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 30 ++++++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index 0ed11e80e5e2..53341dfb4204 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -638,6 +638,32 @@ status = "disabled"; }; + usb_qmpphy: phy@1615000 { + compatible = "qcom,qcm2290-qmp-usb3-phy"; + reg = <0x0 0x01615000 0x0 0x1000>; + + clocks = <&gcc GCC_AHB2PHY_USB_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "cfg_ahb", + "ref", + "com_aux", + "pipe"; + + resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, + <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; + reset-names = "phy", + "phy_phy"; + + #clock-cells = <0>; + clock-output-names = "usb3_phy_pipe_clk_src"; + + #phy-cells = <0>; + + status = "disabled"; + }; + qfprom@1b44000 { compatible = "qcom,qcm2290-qfprom", "qcom,qfprom"; reg = <0x0 0x01b44000 0x0 0x3000>; @@ -1062,8 +1088,8 @@ compatible = "snps,dwc3"; reg = <0x0 0x04e00000 0x0 0xcd00>; interrupts = ; - phys = <&usb_hsphy>; - phy-names = "usb2-phy"; + phys = <&usb_hsphy>, <&usb_qmpphy>; + phy-names = "usb2-phy", "usb3-phy"; iommus = <&apps_smmu 0x120 0x0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; -- cgit v1.2.3-59-g8ed1b From 85c0d230098fcc2fe8e4e52b783919ed71b91b9e Mon Sep 17 00:00:00 2001 From: Varadarajan Narayanan Date: Fri, 9 Jun 2023 11:26:31 +0530 Subject: dt-bindings: clock: Add USB related clocks for IPQ9574 Add the clocks needed for enabling USB in IPQ9574 Reviewed-by: Dmitry Baryshkov Acked-by: Stephen Boyd Signed-off-by: Varadarajan Narayanan Link: https://lore.kernel.org/r/d1c5aa4a8535c645fdb06df62a562918516ba0c6.1686289721.git.quic_varada@quicinc.com [bjorn: Split from driver patch, to allow merging into dts tree] Signed-off-by: Bjorn Andersson --- include/dt-bindings/clock/qcom,ipq9574-gcc.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h index b32a7aa65349..08fd3a37acaa 100644 --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h @@ -214,4 +214,6 @@ #define GCC_CRYPTO_CLK 205 #define GCC_CRYPTO_AXI_CLK 206 #define GCC_CRYPTO_AHB_CLK 207 +#define GCC_USB0_PIPE_CLK 208 +#define GCC_USB0_SLEEP_CLK 209 #endif -- cgit v1.2.3-59-g8ed1b From a98bfb31f6766db26e0d4f39c909b7e8926cb0d8 Mon Sep 17 00:00:00 2001 From: Varadarajan Narayanan Date: Fri, 9 Jun 2023 11:26:32 +0530 Subject: arm64: dts: qcom: ipq9574: Add USB related nodes Add USB phy and controller related nodes SS PHY need two supplies and HS PHY needs three supplies. 0.925V and 3.3V are from fixed regulators and 1.8V is generated from PMIC's LDO Reviewed-by: Dmitry Baryshkov Signed-off-by: Varadarajan Narayanan Link: https://lore.kernel.org/r/37bd667c065b6c254c7e60ab4ad3a3afbe3b0fac.1686289721.git.quic_varada@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 85 +++++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index f120c7c52351..2eadc84fba25 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -505,6 +505,91 @@ status = "disabled"; }; + usb_0_qusbphy: phy@7b000 { + compatible = "qcom,ipq9574-qusb2-phy"; + reg = <0x0007b000 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&xo_board_clk>; + clock-names = "cfg_ahb", + "ref"; + + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; + status = "disabled"; + }; + + usb_0_qmpphy: phy@7d000 { + compatible = "qcom,ipq9574-qmp-usb3-phy"; + reg = <0x0007d000 0xa00>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB0_AUX_CLK>, + <&xo_board_clk>, + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB0_PIPE_CLK>; + clock-names = "aux", + "ref", + "cfg_ahb", + "pipe"; + + resets = <&gcc GCC_USB0_PHY_BCR>, + <&gcc GCC_USB3PHY_0_PHY_BCR>; + reset-names = "phy", + "phy_phy"; + + #clock-cells = <0>; + clock-output-names = "usb0_pipe_clk"; + + status = "disabled"; + }; + + usb3: usb@8af8800 { + compatible = "qcom,ipq9574-dwc3", "qcom,dwc3"; + reg = <0x08af8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_SNOC_USB_CLK>, + <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_ANOC_USB_AXI_CLK>, + <&gcc GCC_USB0_SLEEP_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + assigned-clock-rates = <200000000>, + <24000000>; + + interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event"; + + resets = <&gcc GCC_USB_BCR>; + status = "disabled"; + + usb_0_dwc3: usb@8a00000 { + compatible = "snps,dwc3"; + reg = <0x8a00000 0xcd00>; + clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; + clock-names = "ref"; + interrupts = ; + phys = <&usb_0_qusbphy>, <&usb_0_qmpphy>; + phy-names = "usb2-phy", "usb3-phy"; + tx-fifo-resize; + snps,is-utmi-l1-suspend; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + }; + }; + intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; reg = <0x0b000000 0x1000>, /* GICD */ -- cgit v1.2.3-59-g8ed1b From d5506524d9d9f2be01cbff510b0b8eec0cc9d691 Mon Sep 17 00:00:00 2001 From: Varadarajan Narayanan Date: Fri, 9 Jun 2023 11:26:33 +0530 Subject: arm64: dts: qcom: ipq9574: Add LDO regulator node Add LDO regulator node Reviewed-by: Dmitry Baryshkov Signed-off-by: Varadarajan Narayanan Link: https://lore.kernel.org/r/49b03513a012545651c7d0f149958c78de819880.1686289721.git.quic_varada@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts index 2b3ed8d351f7..8c2451cf9eaa 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts @@ -45,6 +45,13 @@ regulator-min-microvolt = <725000>; regulator-max-microvolt = <1075000>; }; + + mp5496_l2: l2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; }; }; -- cgit v1.2.3-59-g8ed1b From ec4f047679d59294c98095ae2470d34c2f2335a2 Mon Sep 17 00:00:00 2001 From: Varadarajan Narayanan Date: Fri, 9 Jun 2023 11:26:34 +0530 Subject: arm64: dts: qcom: ipq9574: Enable USB Add regulator defines Turn on USB related nodes Provide vdd info Reviewed-by: Dmitry Baryshkov Signed-off-by: Varadarajan Narayanan Link: https://lore.kernel.org/r/5021dbf3a28ee073795e7580bfa019df465e16ed.1686289721.git.quic_varada@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 41 +++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts index 8c2451cf9eaa..877026ccc6e2 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts @@ -21,6 +21,24 @@ chosen { stdout-path = "serial0:115200n8"; }; + + regulator_fixed_3p3: s3300 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-name = "fixed_3p3"; + }; + + regulator_fixed_0p925: s0925 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <925000>; + regulator-boot-on; + regulator-always-on; + regulator-name = "fixed_0p925"; + }; }; &blsp1_uart2 { @@ -105,6 +123,29 @@ }; }; +&usb_0_dwc3 { + dr_mode = "host"; +}; + +&usb_0_qmpphy { + vdda-pll-supply = <&mp5496_l2>; + vdda-phy-supply = <®ulator_fixed_0p925>; + + status = "okay"; +}; + +&usb_0_qusbphy { + vdd-supply = <®ulator_fixed_0p925>; + vdda-pll-supply = <&mp5496_l2>; + vdda-phy-dpdm-supply = <®ulator_fixed_3p3>; + + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + &xo_board_clk { clock-frequency = <24000000>; }; -- cgit v1.2.3-59-g8ed1b From 3091e5820a367f3368132f57e0a9ba6d545da15d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 12 Jun 2023 06:16:23 +0300 Subject: arm64: dts: qcom: sm8150: use proper DSI PHY compatible The DSI PHY on the Qualcomm SM8150 platform requires platform-specific handling. Use the proper SoC-specific compatible string for the DSI PHYs. Reported-by: Degdag Mohamed Fixes: 2ef3bb17c45c ("arm64: dts: qcom: sm8150: Add DISPCC node") Cc: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230612031623.3620155-1-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 18c822abdb88..1ceadd6e0d67 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -3840,7 +3840,7 @@ }; mdss_dsi0_phy: phy@ae94400 { - compatible = "qcom,dsi-phy-7nm"; + compatible = "qcom,dsi-phy-7nm-8150"; reg = <0 0x0ae94400 0 0x200>, <0 0x0ae94600 0 0x280>, <0 0x0ae94900 0 0x260>; @@ -3914,7 +3914,7 @@ }; mdss_dsi1_phy: phy@ae96400 { - compatible = "qcom,dsi-phy-7nm"; + compatible = "qcom,dsi-phy-7nm-8150"; reg = <0 0x0ae96400 0 0x200>, <0 0x0ae96600 0 0x280>, <0 0x0ae96900 0 0x260>; -- cgit v1.2.3-59-g8ed1b From 75a511b1e5ff6ffadb9b51d85beee8c7bcc29ba9 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 14 Jun 2023 13:35:34 +0200 Subject: arm64: dts: qcom: sm6350: Add GPUCC node Add and configure a node for the GPU clock controller. Signed-off-by: Konrad Dybcio Reviewed-by: Luca Weiss Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230315-topic-lagoon_gpu-v2-3-afcdfb18bb13@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 30e77010aed5..fd35810bcfb5 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -1308,6 +1309,20 @@ }; }; + gpucc: clock-controller@3d90000 { + compatible = "qcom,sm6350-gpucc"; + reg = <0 0x03d90000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK>, + <&gcc GCC_GPU_GPLL0_DIV_CLK>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mpss: remoteproc@4080000 { compatible = "qcom,sm6350-mpss-pas"; reg = <0x0 0x04080000 0x0 0x4040>; -- cgit v1.2.3-59-g8ed1b From 5b1e5d9a21ec2ad0654ce192371ed81b12088c6f Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 14 Jun 2023 13:35:35 +0200 Subject: arm64: dts: qcom: sm6350: Add QFPROM node Add a node for the QFPROM NVMEM hw and define the GPU fuse. Signed-off-by: Konrad Dybcio Reviewed-by: Luca Weiss Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230315-topic-lagoon_gpu-v2-4-afcdfb18bb13@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index fd35810bcfb5..c0f34bc1d78c 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -805,6 +805,18 @@ #mbox-cells = <2>; }; + qfprom: qfprom@784000 { + compatible = "qcom,sm6350-qfprom", "qcom,qfprom"; + reg = <0 0x00784000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + + gpu_speed_bin: gpu-speed-bin@2015 { + reg = <0x2015 0x1>; + bits = <0 8>; + }; + }; + rng: rng@793000 { compatible = "qcom,prng-ee"; reg = <0 0x00793000 0 0x1000>; -- cgit v1.2.3-59-g8ed1b From bd9b767502806faccbac6f2c8db09d0ea6ca6e3e Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 14 Jun 2023 13:35:36 +0200 Subject: arm64: dts: qcom: sm6350: Add GPU nodes Add Adreno, GPU SMMU and GMU nodes to hook up everything that the A619 needs to function properly. Co-developed-by: Luca Weiss Signed-off-by: Konrad Dybcio Signed-off-by: Luca Weiss Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230315-topic-lagoon_gpu-v2-5-afcdfb18bb13@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 139 +++++++++++++++++++++++++++++++++++ 1 file changed, 139 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index c0f34bc1d78c..d928e64e33ae 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1321,6 +1321,145 @@ }; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-619.0", "qcom,adreno"; + reg = <0 0x03d00000 0 0x40000>, + <0 0x03d9e000 0 0x1000>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem"; + interrupts = ; + + iommus = <&adreno_smmu 0>; + operating-points-v2 = <&gpu_opp_table>; + qcom,gmu = <&gmu>; + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + + status = "disabled"; + + zap-shader { + memory-region = <&pil_gpu_mem>; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-850000000 { + opp-hz = /bits/ 64 <850000000>; + opp-level = ; + opp-supported-hw = <0x02>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-level = ; + opp-supported-hw = <0x04>; + }; + + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + opp-level = ; + opp-supported-hw = <0x08>; + }; + + opp-565000000 { + opp-hz = /bits/ 64 <565000000>; + opp-level = ; + opp-supported-hw = <0x10>; + }; + + opp-430000000 { + opp-hz = /bits/ 64 <430000000>; + opp-level = ; + opp-supported-hw = <0xff>; + }; + + opp-355000000 { + opp-hz = /bits/ 64 <355000000>; + opp-level = ; + opp-supported-hw = <0xff>; + }; + + opp-253000000 { + opp-hz = /bits/ 64 <253000000>; + opp-level = ; + opp-supported-hw = <0xff>; + }; + }; + }; + + adreno_smmu: iommu@3d40000 { + compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; + reg = <0 0x03d40000 0 0x10000>; + #iommu-cells = <1>; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + ; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + clock-names = "ahb", + "bus", + "iface"; + + power-domains = <&gpucc GPU_CX_GDSC>; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu"; + reg = <0 0x03d6a000 0 0x31000>, + <0 0x0b290000 0 0x10000>, + <0 0x0b490000 0 0x10000>; + reg-names = "gmu", + "gmu_pdc", + "gmu_pdc_seq"; + + interrupts = , + ; + interrupt-names = "hfi", + "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "ahb", + "gmu", + "cxo", + "axi", + "memnoc"; + + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5>; + + operating-points-v2 = <&gmu_opp_table>; + + status = "disabled"; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = ; + }; + }; + }; + gpucc: clock-controller@3d90000 { compatible = "qcom,sm6350-gpucc"; reg = <0 0x03d90000 0 0x9000>; -- cgit v1.2.3-59-g8ed1b From 44bcded2be4fe9b9d0b6e48075c9947b75c0af63 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 14 Jun 2023 13:35:37 +0200 Subject: arm64: dts: qcom: sm6350: Fix ZAP region The previous ZAP region definition was wrong. Fix it. Note this is not a device-specific fixup, but a fixup to the generic PIL load address. Fixes: 5f82b9cda61e ("arm64: dts: qcom: Add SM6350 device tree") Signed-off-by: Konrad Dybcio Reviewed-by: Luca Weiss Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230315-topic-lagoon_gpu-v2-6-afcdfb18bb13@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index d928e64e33ae..cc72c4b4e7c0 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -634,11 +634,6 @@ no-map; }; - pil_gpu_mem: memory@8b715400 { - reg = <0 0x8b715400 0 0x2000>; - no-map; - }; - pil_modem_mem: memory@8b800000 { reg = <0 0x8b800000 0 0xf800000>; no-map; @@ -659,6 +654,11 @@ no-map; }; + pil_gpu_mem: memory@f0d00000 { + reg = <0 0xf0d00000 0 0x1000>; + no-map; + }; + debug_region: memory@ffb00000 { reg = <0 0xffb00000 0 0xc0000>; no-map; -- cgit v1.2.3-59-g8ed1b From 26c71d31f8be3493006140961acf6be204004fdb Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 14 Jun 2023 13:35:38 +0200 Subject: arm64: dts: qcom: sm6350: Add DPU1 nodes Add nodes required to enable MDSS/DPU1 on SM6350. There seem to be no additional changes required to support the derivative SoCs, such as SM7225. Signed-off-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230315-topic-lagoon_gpu-v2-7-afcdfb18bb13@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 218 +++++++++++++++++++++++++++++++++++ 1 file changed, 218 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index cc72c4b4e7c0..7af6278d6b23 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -4,6 +4,7 @@ * Copyright (c) 2022, Luca Weiss */ +#include #include #include #include @@ -1869,6 +1870,223 @@ #power-domain-cells = <1>; }; + mdss: display-subsystem@ae00000 { + compatible = "qcom,sm6350-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", + "bus", + "core"; + + power-domains = <&dispcc MDSS_GDSC>; + iommus = <&apps_smmu 0x800 0x2>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,sm6350-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + clocks = <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "iface", + "rot", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM6350_CX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-373333333 { + opp-hz = /bits/ 64 <373333333>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-448000000 { + opp-hz = /bits/ 64 <448000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-560000000 { + opp-hz = /bits/ 64 <560000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&mdss_dsi_opp_table>; + power-domains = <&rpmhpd SM6350_MX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94a00 0 0x1e0>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sm6350-dispcc"; + reg = <0 0x0af00000 0 0x20000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_CLK>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + clock-names = "bi_tcxo", + "gcc_disp_gpll0_clk", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm6350-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>; -- cgit v1.2.3-59-g8ed1b From 2b812caf5f64df959555e48dfc7bf8f061d9fe8f Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 15 Jun 2023 11:34:21 +0300 Subject: Revert "arm64: dts: qcom: msm8996: rename labels for HDMI nodes" The commit f43b6dc7d56e ("arm64: dts: qcom: msm8996: rename labels for HDMI nodes") is broken, it changes all the HDMI node names, compatible strings instead of changing just node aliases. Revert the commit in order to land a proper clean version. Reported-by: Konrad Dybcio Fixes: f43b6dc7d56e ("arm64: dts: qcom: msm8996: rename labels for HDMI nodes") Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230615083422.350297-2-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 50 ++++++++++++++-------------- arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts | 6 ++-- arch/arm64/boot/dts/qcom/msm8996-mtp.dts | 4 +-- arch/arm64/boot/dts/qcom/msm8996.dtsi | 16 ++++----- 4 files changed, 38 insertions(+), 38 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index 537547b97459..b599909c4463 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -208,6 +208,25 @@ status = "okay"; }; +&hdmi { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>; + pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>; + + core-vdda-supply = <&vreg_l12a_1p8>; + core-vcc-supply = <&vreg_s4a_1p8>; +}; + +&hdmi_phy { + status = "okay"; + + vddio-supply = <&vreg_l12a_1p8>; + vcca-supply = <&vreg_l28a_0p925>; + #phy-cells = <0>; +}; + &hsusb_phy1 { status = "okay"; @@ -232,25 +251,6 @@ status = "okay"; }; -&mdss_hdmi { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mdss_hdmi_hpd_active &mdss_hdmi_ddc_active>; - pinctrl-1 = <&mdss_hdmi_hpd_suspend &mdss_hdmi_ddc_suspend>; - - core-vdda-supply = <&vreg_l12a_1p8>; - core-vcc-supply = <&vreg_s4a_1p8>; -}; - -&mdss_hdmi_phy { - status = "okay"; - - vddio-supply = <&vreg_l12a_1p8>; - vcca-supply = <&vreg_l28a_0p925>; - #phy-cells = <0>; -}; - &mmcc { vdd-gfx-supply = <&vdd_gfx>; }; @@ -433,28 +433,28 @@ drive-strength = <2>; }; - mdss_hdmi_hpd_active: mdss_hdmi-hpd-active-state { + hdmi_hpd_active: hdmi-hpd-active-state { pins = "gpio34"; function = "hdmi_hot"; bias-pull-down; drive-strength = <16>; }; - mdss_hdmi_hpd_suspend: mdss_hdmi-hpd-suspend-state { + hdmi_hpd_suspend: hdmi-hpd-suspend-state { pins = "gpio34"; function = "hdmi_hot"; bias-pull-down; drive-strength = <2>; }; - mdss_hdmi_ddc_active: mdss_hdmi-ddc-active-state { + hdmi_ddc_active: hdmi-ddc-active-state { pins = "gpio32", "gpio33"; function = "hdmi_ddc"; drive-strength = <2>; bias-pull-up; }; - mdss_hdmi_ddc_suspend: mdss_hdmi-ddc-suspend-state { + hdmi_ddc_suspend: hdmi-ddc-suspend-state { pins = "gpio32", "gpio33"; function = "hdmi_ddc"; drive-strength = <2>; @@ -1043,7 +1043,7 @@ }; }; - mdss_hdmi-dai-link { + hdmi-dai-link { link-name = "HDMI"; cpu { sound-dai = <&q6afedai HDMI_RX>; @@ -1054,7 +1054,7 @@ }; codec { - sound-dai = <&mdss_hdmi 0>; + sound-dai = <&hdmi 0>; }; }; diff --git a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts index ac6471d1db1f..ed2e2f6c6775 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts @@ -92,15 +92,15 @@ status = "okay"; }; -&mdss { +&hdmi { status = "okay"; }; -&mdss_hdmi { +&hdmi_phy { status = "okay"; }; -&mdss_hdmi_phy { +&mdss { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996-mtp.dts b/arch/arm64/boot/dts/qcom/msm8996-mtp.dts index 495d45a16e63..596ad4c896f5 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-mtp.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-mtp.dts @@ -24,10 +24,10 @@ status = "okay"; }; -&mdss_hdmi { +&hdmi { status = "okay"; }; -&mdss_hdmi_phy { +&hdmi_phy { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 0cb2d4f08c3a..3855366ca89f 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -895,7 +895,7 @@ <&mdss_dsi0_phy 0>, <&mdss_dsi1_phy 1>, <&mdss_dsi1_phy 0>, - <&mdss_hdmi_phy>; + <&hdmi_phy>; clock-names = "xo", "gpll0", "gcc_mmss_noc_cfg_ahb_clk", @@ -980,7 +980,7 @@ port@0 { reg = <0>; mdp5_intf3_out: endpoint { - remote-endpoint = <&mdss_hdmi_in>; + remote-endpoint = <&hdmi_in>; }; }; @@ -1136,8 +1136,8 @@ status = "disabled"; }; - mdss_hdmi: mdss_hdmi-tx@9a0000 { - compatible = "qcom,mdss_hdmi-tx-8996"; + hdmi: hdmi-tx@9a0000 { + compatible = "qcom,hdmi-tx-8996"; reg = <0x009a0000 0x50c>, <0x00070000 0x6158>, <0x009e0000 0xfff>; @@ -1160,7 +1160,7 @@ "alt_iface", "extp"; - phys = <&mdss_hdmi_phy>; + phys = <&hdmi_phy>; #sound-dai-cells = <1>; status = "disabled"; @@ -1171,16 +1171,16 @@ port@0 { reg = <0>; - mdss_hdmi_in: endpoint { + hdmi_in: endpoint { remote-endpoint = <&mdp5_intf3_out>; }; }; }; }; - mdss_hdmi_phy: phy@9a0600 { + hdmi_phy: phy@9a0600 { #phy-cells = <0>; - compatible = "qcom,mdss_hdmi-phy-8996"; + compatible = "qcom,hdmi-phy-8996"; reg = <0x009a0600 0x1c4>, <0x009a0a00 0x124>, <0x009a0c00 0x124>, -- cgit v1.2.3-59-g8ed1b From 1770394e68942f48d9b111694fccfef337905632 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 15 Jun 2023 11:34:22 +0300 Subject: arm64: dts: qcom: msm8996: rename labels for HDMI nodes In board files MDSS and HDMI nodes do not come next to each other, because labels for HDMI nodes do not have the common mdss_ prefix. Follow the DSI example and enable such grouping by changing the prefix for HDMI labels to mdss_hdmi_*. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230615083422.350297-3-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 40 ++++++++++++++-------------- arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts | 6 ++--- arch/arm64/boot/dts/qcom/msm8996-mtp.dts | 4 +-- arch/arm64/boot/dts/qcom/msm8996.dtsi | 12 ++++----- 4 files changed, 31 insertions(+), 31 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index b599909c4463..39170c18c693 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -208,25 +208,6 @@ status = "okay"; }; -&hdmi { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>; - pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>; - - core-vdda-supply = <&vreg_l12a_1p8>; - core-vcc-supply = <&vreg_s4a_1p8>; -}; - -&hdmi_phy { - status = "okay"; - - vddio-supply = <&vreg_l12a_1p8>; - vcca-supply = <&vreg_l28a_0p925>; - #phy-cells = <0>; -}; - &hsusb_phy1 { status = "okay"; @@ -251,6 +232,25 @@ status = "okay"; }; +&mdss_hdmi { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>; + pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>; + + core-vdda-supply = <&vreg_l12a_1p8>; + core-vcc-supply = <&vreg_s4a_1p8>; +}; + +&mdss_hdmi_phy { + status = "okay"; + + vddio-supply = <&vreg_l12a_1p8>; + vcca-supply = <&vreg_l28a_0p925>; + #phy-cells = <0>; +}; + &mmcc { vdd-gfx-supply = <&vdd_gfx>; }; @@ -1054,7 +1054,7 @@ }; codec { - sound-dai = <&hdmi 0>; + sound-dai = <&mdss_hdmi 0>; }; }; diff --git a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts index ed2e2f6c6775..ac6471d1db1f 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts @@ -92,15 +92,15 @@ status = "okay"; }; -&hdmi { +&mdss { status = "okay"; }; -&hdmi_phy { +&mdss_hdmi { status = "okay"; }; -&mdss { +&mdss_hdmi_phy { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996-mtp.dts b/arch/arm64/boot/dts/qcom/msm8996-mtp.dts index 596ad4c896f5..495d45a16e63 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-mtp.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-mtp.dts @@ -24,10 +24,10 @@ status = "okay"; }; -&hdmi { +&mdss_hdmi { status = "okay"; }; -&hdmi_phy { +&mdss_hdmi_phy { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 3855366ca89f..40ac0a784a4a 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -895,7 +895,7 @@ <&mdss_dsi0_phy 0>, <&mdss_dsi1_phy 1>, <&mdss_dsi1_phy 0>, - <&hdmi_phy>; + <&mdss_hdmi_phy>; clock-names = "xo", "gpll0", "gcc_mmss_noc_cfg_ahb_clk", @@ -980,7 +980,7 @@ port@0 { reg = <0>; mdp5_intf3_out: endpoint { - remote-endpoint = <&hdmi_in>; + remote-endpoint = <&mdss_hdmi_in>; }; }; @@ -1136,7 +1136,7 @@ status = "disabled"; }; - hdmi: hdmi-tx@9a0000 { + mdss_hdmi: hdmi-tx@9a0000 { compatible = "qcom,hdmi-tx-8996"; reg = <0x009a0000 0x50c>, <0x00070000 0x6158>, @@ -1160,7 +1160,7 @@ "alt_iface", "extp"; - phys = <&hdmi_phy>; + phys = <&mdss_hdmi_phy>; #sound-dai-cells = <1>; status = "disabled"; @@ -1171,14 +1171,14 @@ port@0 { reg = <0>; - hdmi_in: endpoint { + mdss_hdmi_in: endpoint { remote-endpoint = <&mdp5_intf3_out>; }; }; }; }; - hdmi_phy: phy@9a0600 { + mdss_hdmi_phy: phy@9a0600 { #phy-cells = <0>; compatible = "qcom,hdmi-phy-8996"; reg = <0x009a0600 0x1c4>, -- cgit v1.2.3-59-g8ed1b From 775a5283c25d160b2a1359018c447bc518096547 Mon Sep 17 00:00:00 2001 From: Vincent Guittot Date: Thu, 15 Jun 2023 17:48:52 +0200 Subject: arm64: dts: qcom: sm8250: correct dynamic power coefficients sm8250 faces the same problem with its Energy Model as sdm845. The energy cost of LITTLE cores is reported to be higher than medium or big cores EM computes the energy with formula: energy = OPP's cost / maximum cpu capacity * utilization On v6.4-rc6 we have: max capacity of CPU0 = 284 capacity of CPU0's OPP(1612800 Hz) = 253 cost of CPU0's OPP(1612800 Hz) = 191704 max capacity of CPU4 = 871 capacity of CPU4's OPP(710400 Hz) = 255 cost of CPU4's OPP(710400 Hz) = 343217 Both OPPs have almost the same compute capacity but the estimated energy per unit of utilization will be estimated to: energy CPU0 = 191704 / 284 * 1 = 675 energy CPU4 = 343217 / 871 * 1 = 394 EM estimates that little CPU0 will consume 71% more than medium CPU4 for the same compute capacity. According to [1], little consumes 25% less than medium core for Coremark benchmark at those OPPs for the same duration. Set the dynamic-power-coefficient of CPU0-3 to 105 to fix the energy model for little CPUs. [1] https://github.com/kdrag0n/freqbench/tree/master/results/sm8250/k30s Fixes: 6aabed5526ee ("arm64: dts: qcom: sm8250: Add CPU capacities and energy model") Signed-off-by: Vincent Guittot Link: https://lore.kernel.org/r/20230615154852.130076-1-vincent.guittot@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 83ab6de459bc..dd817ec200f1 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -100,7 +100,7 @@ clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <448>; - dynamic-power-coefficient = <205>; + dynamic-power-coefficient = <105>; next-level-cache = <&L2_0>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; @@ -131,7 +131,7 @@ clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <448>; - dynamic-power-coefficient = <205>; + dynamic-power-coefficient = <105>; next-level-cache = <&L2_100>; power-domains = <&CPU_PD1>; power-domain-names = "psci"; @@ -156,7 +156,7 @@ clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <448>; - dynamic-power-coefficient = <205>; + dynamic-power-coefficient = <105>; next-level-cache = <&L2_200>; power-domains = <&CPU_PD2>; power-domain-names = "psci"; @@ -181,7 +181,7 @@ clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <448>; - dynamic-power-coefficient = <205>; + dynamic-power-coefficient = <105>; next-level-cache = <&L2_300>; power-domains = <&CPU_PD3>; power-domain-names = "psci"; -- cgit v1.2.3-59-g8ed1b From adc16b84e1ea12fe527fba463db05452c9f06993 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 16 Jun 2023 01:46:10 +0200 Subject: arm64: dts: qcom: sc7180: Hook up BWMONs Hook up 2 out of 4 (the rest are for NPU) BWMONs exposed on the SC7180. This allows for scaling DDR and LLCC independently from cpufreq. Signed-off-by: Konrad Dybcio Tested-by: Nikita Travkin # Aspire 1 Link: https://lore.kernel.org/r/20230616-topic-sc7180_bwmons-v1-2-4ddb96f9a6cd@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-lite.dtsi | 10 +- arch/arm64/boot/dts/qcom/sc7180.dtsi | 161 ++++++++++++++++++++++-------- 2 files changed, 124 insertions(+), 47 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-lite.dtsi b/arch/arm64/boot/dts/qcom/sc7180-lite.dtsi index 4b306a59d9be..975d4422f27b 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-lite.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-lite.dtsi @@ -6,21 +6,21 @@ */ &cpu6_opp10 { - opp-peak-kBps = <7216000 22425600>; + opp-peak-kBps = <22425600>; }; &cpu6_opp11 { - opp-peak-kBps = <7216000 22425600>; + opp-peak-kBps = <22425600>; }; &cpu6_opp12 { - opp-peak-kBps = <8532000 23347200>; + opp-peak-kBps = <23347200>; }; &cpu6_opp13 { - opp-peak-kBps = <8532000 23347200>; + opp-peak-kBps = <23347200>; }; &cpu6_opp14 { - opp-peak-kBps = <8532000 23347200>; + opp-peak-kBps = <23347200>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index e25dc2bb52a7..31381e78edd7 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -84,8 +85,7 @@ capacity-dmips-mhz = <415>; dynamic-power-coefficient = <137>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnects = <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; next-level-cache = <&L2_0>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -115,8 +115,7 @@ dynamic-power-coefficient = <137>; next-level-cache = <&L2_100>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnects = <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; L2_100: l2-cache { @@ -140,8 +139,7 @@ dynamic-power-coefficient = <137>; next-level-cache = <&L2_200>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnects = <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; L2_200: l2-cache { @@ -165,8 +163,7 @@ dynamic-power-coefficient = <137>; next-level-cache = <&L2_300>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnects = <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; L2_300: l2-cache { @@ -190,8 +187,7 @@ dynamic-power-coefficient = <137>; next-level-cache = <&L2_400>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnects = <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; L2_400: l2-cache { @@ -215,8 +211,7 @@ dynamic-power-coefficient = <137>; next-level-cache = <&L2_500>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnects = <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; L2_500: l2-cache { @@ -240,8 +235,7 @@ dynamic-power-coefficient = <480>; next-level-cache = <&L2_600>; operating-points-v2 = <&cpu6_opp_table>; - interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnects = <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 1>; L2_600: l2-cache { @@ -265,8 +259,7 @@ dynamic-power-coefficient = <480>; next-level-cache = <&L2_700>; operating-points-v2 = <&cpu6_opp_table>; - interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, - <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnects = <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 1>; L2_700: l2-cache { @@ -386,52 +379,52 @@ cpu0_opp1: opp-300000000 { opp-hz = /bits/ 64 <300000000>; - opp-peak-kBps = <1200000 4800000>; + opp-peak-kBps = <4800000>; }; cpu0_opp2: opp-576000000 { opp-hz = /bits/ 64 <576000000>; - opp-peak-kBps = <1200000 4800000>; + opp-peak-kBps = <4800000>; }; cpu0_opp3: opp-768000000 { opp-hz = /bits/ 64 <768000000>; - opp-peak-kBps = <1200000 4800000>; + opp-peak-kBps = <4800000>; }; cpu0_opp4: opp-1017600000 { opp-hz = /bits/ 64 <1017600000>; - opp-peak-kBps = <1804000 8908800>; + opp-peak-kBps = <8908800>; }; cpu0_opp5: opp-1248000000 { opp-hz = /bits/ 64 <1248000000>; - opp-peak-kBps = <2188000 12902400>; + opp-peak-kBps = <12902400>; }; cpu0_opp6: opp-1324800000 { opp-hz = /bits/ 64 <1324800000>; - opp-peak-kBps = <2188000 12902400>; + opp-peak-kBps = <12902400>; }; cpu0_opp7: opp-1516800000 { opp-hz = /bits/ 64 <1516800000>; - opp-peak-kBps = <3072000 15052800>; + opp-peak-kBps = <15052800>; }; cpu0_opp8: opp-1612800000 { opp-hz = /bits/ 64 <1612800000>; - opp-peak-kBps = <3072000 15052800>; + opp-peak-kBps = <15052800>; }; cpu0_opp9: opp-1708800000 { opp-hz = /bits/ 64 <1708800000>; - opp-peak-kBps = <3072000 15052800>; + opp-peak-kBps = <15052800>; }; cpu0_opp10: opp-1804800000 { opp-hz = /bits/ 64 <1804800000>; - opp-peak-kBps = <4068000 22425600>; + opp-peak-kBps = <22425600>; }; }; @@ -441,82 +434,82 @@ cpu6_opp1: opp-300000000 { opp-hz = /bits/ 64 <300000000>; - opp-peak-kBps = <2188000 8908800>; + opp-peak-kBps = <8908800>; }; cpu6_opp2: opp-652800000 { opp-hz = /bits/ 64 <652800000>; - opp-peak-kBps = <2188000 8908800>; + opp-peak-kBps = <8908800>; }; cpu6_opp3: opp-825600000 { opp-hz = /bits/ 64 <825600000>; - opp-peak-kBps = <2188000 8908800>; + opp-peak-kBps = <8908800>; }; cpu6_opp4: opp-979200000 { opp-hz = /bits/ 64 <979200000>; - opp-peak-kBps = <2188000 8908800>; + opp-peak-kBps = <8908800>; }; cpu6_opp5: opp-1113600000 { opp-hz = /bits/ 64 <1113600000>; - opp-peak-kBps = <2188000 8908800>; + opp-peak-kBps = <8908800>; }; cpu6_opp6: opp-1267200000 { opp-hz = /bits/ 64 <1267200000>; - opp-peak-kBps = <4068000 12902400>; + opp-peak-kBps = <12902400>; }; cpu6_opp7: opp-1555200000 { opp-hz = /bits/ 64 <1555200000>; - opp-peak-kBps = <4068000 15052800>; + opp-peak-kBps = <15052800>; }; cpu6_opp8: opp-1708800000 { opp-hz = /bits/ 64 <1708800000>; - opp-peak-kBps = <6220000 19353600>; + opp-peak-kBps = <19353600>; }; cpu6_opp9: opp-1843200000 { opp-hz = /bits/ 64 <1843200000>; - opp-peak-kBps = <6220000 19353600>; + opp-peak-kBps = <19353600>; }; cpu6_opp10: opp-1900800000 { opp-hz = /bits/ 64 <1900800000>; - opp-peak-kBps = <6220000 22425600>; + opp-peak-kBps = <22425600>; }; cpu6_opp11: opp-1996800000 { opp-hz = /bits/ 64 <1996800000>; - opp-peak-kBps = <6220000 22425600>; + opp-peak-kBps = <22425600>; }; cpu6_opp12: opp-2112000000 { opp-hz = /bits/ 64 <2112000000>; - opp-peak-kBps = <6220000 22425600>; + opp-peak-kBps = <22425600>; }; cpu6_opp13: opp-2208000000 { opp-hz = /bits/ 64 <2208000000>; - opp-peak-kBps = <7216000 22425600>; + opp-peak-kBps = <22425600>; }; cpu6_opp14: opp-2323200000 { opp-hz = /bits/ 64 <2323200000>; - opp-peak-kBps = <7216000 22425600>; + opp-peak-kBps = <22425600>; }; cpu6_opp15: opp-2400000000 { opp-hz = /bits/ 64 <2400000000>; - opp-peak-kBps = <8532000 23347200>; + opp-peak-kBps = <23347200>; }; cpu6_opp16: opp-2553600000 { opp-hz = /bits/ 64 <2553600000>; - opp-peak-kBps = <8532000 23347200>; + opp-peak-kBps = <23347200>; }; }; @@ -2773,6 +2766,90 @@ }; }; + pmu@90b6300 { + compatible = "qcom,sc7180-cpu-bwmon", "qcom,sdm845-bwmon"; + reg = <0 0x090b6300 0 0x600>; + interrupts = ; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; + operating-points-v2 = <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <2288000>; + }; + + opp-1 { + opp-peak-kBps = <4577000>; + }; + + opp-2 { + opp-peak-kBps = <7110000>; + }; + + opp-3 { + opp-peak-kBps = <9155000>; + }; + + opp-4 { + opp-peak-kBps = <12298000>; + }; + + opp-5 { + opp-peak-kBps = <14236000>; + }; + }; + }; + + pmu@90cd000 { + compatible = "qcom,sc7180-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; + reg = <0 0x090cd000 0 0x1000>; + interrupts = ; + + interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + operating-points-v2 = <&llcc_bwmon_opp_table>; + + llcc_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <1144000>; + }; + + opp-1 { + opp-peak-kBps = <1720000>; + }; + + opp-2 { + opp-peak-kBps = <2086000>; + }; + + opp-3 { + opp-peak-kBps = <2929000>; + }; + + opp-4 { + opp-peak-kBps = <3879000>; + }; + + opp-5 { + opp-peak-kBps = <5931000>; + }; + + opp-6 { + opp-peak-kBps = <6881000>; + }; + + opp-7 { + opp-peak-kBps = <8137000>; + }; + }; + }; + dc_noc: interconnect@9160000 { compatible = "qcom,sc7180-dc-noc"; reg = <0 0x09160000 0 0x03200>; -- cgit v1.2.3-59-g8ed1b From b02966f8689795406ac210189924a8cb02a71bbe Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 16 Jun 2023 19:49:55 +0200 Subject: arm64: dts: qcom: sm8450: correct crypto unit address Crypto node unit address should match reg. Fixes: b92b0d2f7582 ("arm64: dts: qcom: sm8450: add crypto nodes") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230616174955.1783652-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 5cd7296c7660..1c71c0a2cd81 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -4212,7 +4212,7 @@ <&apps_smmu 0x59f 0x0>; }; - crypto: crypto@1de0000 { + crypto: crypto@1dfa000 { compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce"; reg = <0 0x01dfa000 0 0x6000>; dmas = <&cryptobam 4>, <&cryptobam 5>; -- cgit v1.2.3-59-g8ed1b From 9e3a0c7acba5e1ec7b0730bac904ba820b70b5cf Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 17 Jun 2023 13:21:14 +0200 Subject: arm64: dts: qcom: apq8039-t2: remove superfluous "input-enable" Pin configuration property "input-enable" was used with the intention to disable the output, but this is done by default by Linux drivers. Since commit c4a48b0df8bf ("dt-bindings: pinctrl: qcom: tlmm should use output-disable, not input-enable") the property is not accepted anymore. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230617112115.130024-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8039-t2.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/apq8039-t2.dts b/arch/arm64/boot/dts/qcom/apq8039-t2.dts index 40644c242fb7..43686bbd87f4 100644 --- a/arch/arm64/boot/dts/qcom/apq8039-t2.dts +++ b/arch/arm64/boot/dts/qcom/apq8039-t2.dts @@ -366,7 +366,6 @@ function = "gpio"; pins = "gpio107"; bias-pull-up; - input-enable; }; }; -- cgit v1.2.3-59-g8ed1b From ba492bea16e2c036ef5725f166f1d20835b6e114 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 17 Jun 2023 13:21:15 +0200 Subject: arm64: dts: qcom: sc8180x-flex-5g: remove superfluous "input-enable" Pin configuration property "input-enable" was used with the intention to disable the output, but this is done by default by Linux drivers. Since commit c4a48b0df8bf ("dt-bindings: pinctrl: qcom: tlmm should use output-disable, not input-enable") the property is not accepted anymore. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230617112115.130024-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index fe3b366e1435..b12e0a61b3c0 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -497,7 +497,6 @@ pins = "gpio121"; function = "gpio"; - input-enable; bias-disable; }; @@ -513,7 +512,6 @@ pins = "gpio122"; function = "gpio"; - input-enable; bias-pull-up; drive-strength = <2>; }; @@ -530,7 +528,6 @@ pins = "gpio37", "gpio24"; function = "gpio"; - input-enable; bias-pull-up; drive-strength = <2>; }; -- cgit v1.2.3-59-g8ed1b From c756d233715a899dd1cce4b1db4cbd50b0f55a9e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 17 Jun 2023 19:15:27 +0200 Subject: arm64: dts: qcom: msm8916-gt5: drop incorrect accelerometer interrupt-names st,lis2hh12 accelerometer binding does not allow interrupt-names: msm8916-samsung-gt58.dtb: accelerometer@1d: 'interrupt-names' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Nikita Travkin Link: https://lore.kernel.org/r/20230617171541.286957-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi index 7943bb619116..54d648972d35 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi @@ -101,7 +101,6 @@ interrupt-parent = <&tlmm>; interrupts = <115 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "INT1"; st,drdy-int-pin = <1>; mount-matrix = "0", "1", "0", -- cgit v1.2.3-59-g8ed1b From 6a541eaa6e8e5283efb993ae7a947bede8d01fa5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 17 Jun 2023 19:15:28 +0200 Subject: arm64: dts: qcom: msm8916-l8150: correct light sensor VDDIO supply liteon,ltr559 light sensor takes VDDIO, not VIO, supply: msm8916-longcheer-l8150.dtb: light-sensor@23: 'vio-supply' does not match any of the regexes: 'pinctrl-[0-9]+' Fixes: 3016af34ef8d ("arm64: dts: qcom: msm8916-longcheer-l8150: Add light and proximity sensor") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Nikita Travkin Link: https://lore.kernel.org/r/20230617171541.286957-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index 97262b8519b3..3892ad4f639a 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -165,7 +165,7 @@ pinctrl-0 = <&light_int_default>; vdd-supply = <&pm8916_l17>; - vio-supply = <&pm8916_l6>; + vddio-supply = <&pm8916_l6>; }; gyroscope@68 { -- cgit v1.2.3-59-g8ed1b From 031df8e650a8584d24c91fa64465e0660accd339 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 17 Jun 2023 19:15:29 +0200 Subject: arm64: dts: qcom: apq8016-sbc: drop label from I2C and SPI I2C and SPI controller bindings do not allow label property: apq8016-sbc.dtb: spi@78b7000: Unevaluated properties are not allowed ('label' was unexpected) apq8016-sbc.dtb: i2c@78b6000: Unevaluated properties are not allowed ('label' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230617171541.286957-3-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index f3d65a606194..e0993e32ee38 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -172,15 +172,13 @@ }; &blsp_i2c2 { - /* On Low speed expansion */ + /* On Low speed expansion: LS-I2C0 */ status = "okay"; - label = "LS-I2C0"; }; &blsp_i2c4 { - /* On High speed expansion */ + /* On High speed expansion: HS-I2C2 */ status = "okay"; - label = "HS-I2C2"; adv_bridge: bridge@39 { status = "okay"; @@ -228,21 +226,18 @@ }; &blsp_i2c6 { - /* On Low speed expansion */ + /* On Low speed expansion: LS-I2C1 */ status = "okay"; - label = "LS-I2C1"; }; &blsp_spi3 { - /* On High speed expansion */ + /* On High speed expansion: HS-SPI1 */ status = "okay"; - label = "HS-SPI1"; }; &blsp_spi5 { - /* On Low speed expansion */ + /* On Low speed expansion: LS-SPI0 */ status = "okay"; - label = "LS-SPI0"; }; &blsp_uart1 { -- cgit v1.2.3-59-g8ed1b From d4bbcf50baa9d7f70e97a3fd3b0d5e4f599a6217 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 17 Jun 2023 19:15:30 +0200 Subject: arm64: dts: qcom: apq8096-db820c: drop label from I2C I2C controller bindings do not allow label property: apq8096-db820c.dtb: i2c@7577000: Unevaluated properties are not allowed ('label' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230617171541.286957-4-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index 39170c18c693..16353e3b7fab 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -138,8 +138,7 @@ }; &blsp1_i2c3 { - /* On Low speed expansion */ - label = "LS-I2C0"; + /* On Low speed expansion: LS-I2C0 */ status = "okay"; }; @@ -168,14 +167,12 @@ }; &blsp2_i2c1 { - /* On High speed expansion */ - label = "HS-I2C2"; + /* On High speed expansion: HS-I2C2 */ status = "okay"; }; &blsp2_i2c1 { - /* On Low speed expansion */ - label = "LS-I2C1"; + /* On Low speed expansion: LS-I2C1 */ status = "okay"; }; -- cgit v1.2.3-59-g8ed1b From 35cda57217adceee2f6bc738a1d98a2cccab709e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 17 Jun 2023 19:15:31 +0200 Subject: arm64: dts: qcom: msm8939: drop incorrect smp2p Hexagon properties The children of qcom,smp2p do not need address/size-cells: msm8939-sony-xperia-kanuti-tulip.dtb: smp2p-hexagon: slave-kernel: '#address-cells', '#size-cells' do not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230617171541.286957-5-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8939.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi index 895cafc11480..05d8abbbc840 100644 --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -386,8 +386,6 @@ interrupt-controller; #interrupt-cells = <2>; - #address-cells = <0>; - #size-cells = <0>; }; }; -- cgit v1.2.3-59-g8ed1b From 368f8d196976e691af9cb8e61c9c852d574759fb Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 17 Jun 2023 19:15:32 +0200 Subject: arm64: dts: qcom: msm8996-xiaomi: drop label from I2C I2C controller bindings do not allow label property: msm8996-xiaomi-gemini.dtb: i2c@75b6000: Unevaluated properties are not allowed ('label' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230617171541.286957-6-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index 47f55c7311e9..8c2d6e9e851b 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -187,7 +187,6 @@ &blsp2_i2c2 { status = "okay"; - label = "NFC_I2C"; clock-frequency = <400000>; nfc: pn548@28 { @@ -208,7 +207,6 @@ &blsp2_i2c3 { status = "okay"; - label = "TYPEC_I2C"; typec: tusb320l@47 { compatible = "ti,tusb320l"; @@ -220,7 +218,7 @@ &blsp2_i2c6 { status = "okay"; - label = "MSM_TS_I2C"; + /* MSM_TS */ }; &blsp1_uart2 { -- cgit v1.2.3-59-g8ed1b From f7eb45427af670e48a9d28e6bbe7c6b8f68c3bfe Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 17 Jun 2023 19:15:33 +0200 Subject: arm64: dts: qcom: msm8996-xiaomi: use generic node names Use generic node names for I2C devices. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230617171541.286957-7-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index 8c2d6e9e851b..bcd2397eb373 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -189,7 +189,7 @@ status = "okay"; clock-frequency = <400000>; - nfc: pn548@28 { + nfc: nfc@28 { compatible = "nxp,nxp-nci-i2c"; reg = <0x28>; @@ -208,7 +208,7 @@ &blsp2_i2c3 { status = "okay"; - typec: tusb320l@47 { + typec: typec@47 { compatible = "ti,tusb320l"; reg = <0x47>; interrupt-parent = <&tlmm>; -- cgit v1.2.3-59-g8ed1b From 0ec3a3e1b84bc27d482a6cab4e7ab7e2dd26ecf6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 17 Jun 2023 19:15:34 +0200 Subject: arm64: dts: qcom: sc7180-aspire1: use generic ADC channel node names ADC channel node names were changed to require generic 'channel'. The user-visible part is defined via label. sc7180-acer-aspire1.dtb: adc@3100: 'charger-thermistor@4f', 'thermistor@4e' do not match any of the regexes: '^channel@[0-9a-f]+$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Reviewed-by: Nikita Travkin Link: https://lore.kernel.org/r/20230617171541.286957-8-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts index b637b4270f88..dbb48934d499 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts @@ -314,16 +314,18 @@ }; &pm6150_adc { - thermistor@4e { + channel@4e { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "thermistor"; }; - charger-thermistor@4f { + channel@4f { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "charger_thermistor"; }; }; -- cgit v1.2.3-59-g8ed1b From 978869867216e669b6bed11aa669317a11e0dc7a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 17 Jun 2023 19:15:36 +0200 Subject: arm64: dts: qcom: sc8180x: use generic ADC channel node names ADC channel node names were changed to require generic 'channel'. The user-visible part is defined via label. sc8180x-lenovo-flex-5g.dtb: adc@3100: 'die-temp@6', 'ref-gnd@0', 'vref-1p25@1' do not match any of the regexes: '^channel@[0-9a-f]+$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230617171541.286957-10-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi index 8247af01c84a..4556af6cd103 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi @@ -105,19 +105,19 @@ #io-channel-cells = <1>; interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - ref-gnd@0 { + channel@0 { reg = ; qcom,pre-scaling = <1 1>; label = "ref_gnd"; }; - vref-1p25@1 { + channel@1 { reg = ; qcom,pre-scaling = <1 1>; label = "vref_1p25"; }; - die-temp@6 { + channel@6 { reg = ; qcom,pre-scaling = <1 1>; label = "die_temp"; @@ -172,19 +172,19 @@ #io-channel-cells = <1>; interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - ref-gnd@0 { + channel@0 { reg = ; qcom,pre-scaling = <1 1>; label = "ref_gnd"; }; - vref-1p25@1 { + channel@1 { reg = ; qcom,pre-scaling = <1 1>; label = "vref_1p25"; }; - vcoin@85 { + channel@85 { reg = <0x85>; qcom,pre-scaling = <1 1>; label = "vcoin2"; @@ -220,19 +220,19 @@ #io-channel-cells = <1>; interrupts = <0xa 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - ref-gnd@0 { + channel@0 { reg = ; qcom,pre-scaling = <1 1>; label = "ref_gnd"; }; - vref-1p25@1 { + channel@1 { reg = ; qcom,pre-scaling = <1 1>; label = "vref_1p25"; }; - vcoin@85 { + channel@85 { reg = <0x85>; qcom,pre-scaling = <1 1>; label = "vcoin"; @@ -270,19 +270,19 @@ #io-channel-cells = <1>; interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - ref-gnd@0 { + channel@0 { reg = ; qcom,pre-scaling = <1 1>; label = "ref_gnd"; }; - vref-1p25@1 { + channel@1 { reg = ; qcom,pre-scaling = <1 1>; label = "vref_1p25"; }; - die-temp@6 { + channel@6 { reg = ; qcom,pre-scaling = <1 1>; label = "die_temp"; -- cgit v1.2.3-59-g8ed1b From 9ca4673201cc08df152a4ec054d81ae6a6895938 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 17 Jun 2023 19:15:37 +0200 Subject: arm64: dts: qcom: sc8180x: align thermal node name with bindings Bindings expect thermal node names to end with 'thermal': sc8180x-lenovo-flex-5g.dtb: thermal-zones: 'gpu-thermal-bottom', 'gpu-thermal-top' do not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230617171541.286957-11-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index d3ae18535636..576180451491 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -3856,7 +3856,7 @@ }; }; - gpu-thermal-top { + gpu-top-thermal { polling-delay-passive = <250>; polling-delay = <1000>; @@ -4006,7 +4006,7 @@ }; }; - gpu-thermal-bottom { + gpu-bottom-thermal { polling-delay-passive = <250>; polling-delay = <1000>; -- cgit v1.2.3-59-g8ed1b From bee2dea5be813eafc7979c09854b447abd75dfd0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 17 Jun 2023 19:15:38 +0200 Subject: arm64: dts: qcom: sc8180x-flex-5g: correct panel ports Panel takes only one port: sc8180x-lenovo-flex-5g.dtb: panel: 'ports' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230617171541.286957-12-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index b12e0a61b3c0..39c6ef0802aa 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -298,11 +298,9 @@ backlight = <&backlight>; - ports { - port { - auo_b140han06_in: endpoint { - remote-endpoint = <&mdss_edp_out>; - }; + port { + auo_b140han06_in: endpoint { + remote-endpoint = <&mdss_edp_out>; }; }; }; -- cgit v1.2.3-59-g8ed1b From 0f06e8cbd18e7f0e016f21c870f7d7af20ffd47e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 17 Jun 2023 19:15:39 +0200 Subject: arm64: dts: qcom: sc8180x-primus: correct panel ports Panel takes only one port: sc8180x-primus.dtb: panel: 'ports' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230617171541.286957-13-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts index fc038474cb71..9b8695b92c48 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts @@ -377,11 +377,9 @@ backlight = <&backlight>; - ports { - port { - auo_b133han05_in: endpoint { - remote-endpoint = <&mdss_edp_out>; - }; + port { + auo_b133han05_in: endpoint { + remote-endpoint = <&mdss_edp_out>; }; }; }; -- cgit v1.2.3-59-g8ed1b From adc2ee325806e805f9d729f28dd1ac77dd82932a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 17 Jun 2023 19:15:40 +0200 Subject: arm64: dts: qcom: sc8180x-flex-5g: align gpio-keys node name with bindings Bindings except certain pattern for gpio-keys children: sc8180x-lenovo-flex-5g.dtb: gpio-keys: 'lid' does not match any of the regexes: '^(button|event|key|switch|(button|event|key|switch)-[a-z0-9-]+|[a-z0-9-]+-(button|event|key|switch))$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230617171541.286957-14-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index 39c6ef0802aa..fca08db89769 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -36,7 +36,7 @@ pinctrl-0 = <&hall_int_active_state>; pinctrl-names = "default"; - lid { + lid-switch { gpios = <&tlmm 121 GPIO_ACTIVE_LOW>; linux,input-type = ; linux,code = ; -- cgit v1.2.3-59-g8ed1b From c8df0c62cb6a21b98845c44c3539aa727874cd08 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 17 Jun 2023 19:15:41 +0200 Subject: arm64: dts: qcom: sm6115-pro1x: fix incorrect gpio-key,wakeup Use 'wakeup-source' instead of 'gpio-key,wakeup' to indicate key can wake-up the device: sm6115-fxtec-pro1x.dtb: gpio-keys: key-volume-up: Unevaluated properties are not allowed ('gpio-key,wakeup' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230617171541.286957-15-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts index 3ce9875e932c..9b70a87906dc 100644 --- a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts +++ b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts @@ -44,7 +44,7 @@ gpios = <&pm6125_gpios 5 GPIO_ACTIVE_LOW>; debounce-interval = <15>; linux,can-disable; - gpio-key,wakeup; + wakeup-source; }; }; }; -- cgit v1.2.3-59-g8ed1b From 44f2f74df42910ae3a2289f1020788a348089718 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 18 Jun 2023 13:44:36 +0200 Subject: arm64: dts: qcom: sm8350-hdk: correct FSA4480 port FSA4480 has only one port according to bindings: sm8350-hdk.dtb: typec-mux@42: 'port' is a required property Signed-off-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20230618114442.140185-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index b182f4cf06cc..95a2a42ccb9e 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -349,16 +349,9 @@ mode-switch; orientation-switch; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - fsa4480_sbu_mux: endpoint { - remote-endpoint = <&pmic_glink_sbu>; - }; + port { + fsa4480_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_sbu>; }; }; }; -- cgit v1.2.3-59-g8ed1b From dea98746f90ab368ec51dc7a070090165560a5de Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 18 Jun 2023 13:44:37 +0200 Subject: arm64: dts: qcom: sm8450-hdk: correct FSA4480 port FSA4480 has only one port according to bindings: sm8450-hdk.dtb: typec-mux@42: 'port' is a required property Signed-off-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20230618114442.140185-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index d7975b3cf064..e5cbea92e07a 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -518,16 +518,9 @@ mode-switch; orientation-switch; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - fsa4480_sbu_mux: endpoint { - remote-endpoint = <&pmic_glink_sbu>; - }; + port { + fsa4480_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_sbu>; }; }; }; -- cgit v1.2.3-59-g8ed1b From c42f5452de6ad2599c6e5e2a64c180a4ac835d27 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 18 Jun 2023 13:44:38 +0200 Subject: arm64: dts: qcom: sm6125-pdx201: correct ramoops pmsg-size There is no 'msg-size' property in ramoops, so assume intention was for 'pmsg-size': sm6125-sony-xperia-seine-pdx201.dtb: ramoops@ffc00000: Unevaluated properties are not allowed ('msg-size' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230618114442.140185-3-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts index 9f8a9ef398a2..de85086c65ad 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts +++ b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts @@ -79,7 +79,7 @@ reg = <0x0 0xffc40000 0x0 0xc0000>; record-size = <0x1000>; console-size = <0x40000>; - msg-size = <0x20000 0x20000>; + pmsg-size = <0x20000>; }; cmdline_mem: memory@ffd00000 { -- cgit v1.2.3-59-g8ed1b From 2951e7e7611a3ea04de98d0f1bfc4e7ec609ef29 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 18 Jun 2023 13:44:39 +0200 Subject: arm64: dts: qcom: sm6125-sprout: correct ramoops pmsg-size There is no 'msg-size' property in ramoops, so assume intention was for 'pmsg-size': sm6125-xiaomi-laurel-sprout.dtb: ramoops@ffc00000: Unevaluated properties are not allowed ('msg-size' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230618114442.140185-4-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts index a7f4aeae9c1a..7c58d1299a60 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts +++ b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts @@ -52,7 +52,7 @@ reg = <0x0 0xffc40000 0x0 0xc0000>; record-size = <0x1000>; console-size = <0x40000>; - msg-size = <0x20000 0x20000>; + pmsg-size = <0x20000>; }; cmdline_mem: memory@ffd00000 { -- cgit v1.2.3-59-g8ed1b From c86b97a72065e06eacb993dc71fa9febc93422af Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 18 Jun 2023 13:44:40 +0200 Subject: arm64: dts: qcom: sm6350: correct ramoops pmsg-size There is no 'msg-size' property in ramoops, so assume intention was for 'pmsg-size': sm6350-sony-xperia-lena-pdx213.dtb: ramoops@ffc00000: Unevaluated properties are not allowed ('msg-size' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230618114442.140185-5-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 7af6278d6b23..c2b5d56ba242 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -675,7 +675,7 @@ reg = <0 0xffc00000 0 0x100000>; record-size = <0x1000>; console-size = <0x40000>; - msg-size = <0x20000 0x20000>; + pmsg-size = <0x20000>; ecc-size = <16>; no-map; }; -- cgit v1.2.3-59-g8ed1b From 4e6b942f092653ebcdbbc0819b2d1f08ab415bdc Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 18 Jun 2023 13:44:41 +0200 Subject: arm64: dts: qcom: sm8150-kumano: correct ramoops pmsg-size There is no 'msg-size' property in ramoops, so assume intention was for 'pmsg-size': sm8150-sony-xperia-kumano-griffin.dtb: ramoops@ffc00000: Unevaluated properties are not allowed ('msg-size' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230618114442.140185-6-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi index baafea53770b..ae0ca48b89a5 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi @@ -222,7 +222,7 @@ reg = <0x0 0xffc00000 0x0 0x100000>; record-size = <0x1000>; console-size = <0x40000>; - msg-size = <0x20000 0x20000>; + pmsg-size = <0x20000>; ecc-size = <16>; no-map; }; -- cgit v1.2.3-59-g8ed1b From 7dc3606f91427414d00a2fb09e6e0e32c14c2093 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 18 Jun 2023 13:44:42 +0200 Subject: arm64: dts: qcom: sm8250-edo: correct ramoops pmsg-size There is no 'msg-size' property in ramoops, so assume intention was for 'pmsg-size': sm8250-sony-xperia-edo-pdx206.dtb: ramoops@ffc00000: Unevaluated properties are not allowed ('msg-size' was unexpected) Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230618114442.140185-7-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index 8ab82bacba81..9f3ea8d8d798 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -112,7 +112,7 @@ reg = <0x0 0xffc00000 0x0 0x100000>; record-size = <0x1000>; console-size = <0x40000>; - msg-size = <0x20000 0x20000>; + pmsg-size = <0x20000>; ecc-size = <16>; no-map; }; -- cgit v1.2.3-59-g8ed1b From 404d7f65767dde3a0eb3d6127b458b61ed7d7118 Mon Sep 17 00:00:00 2001 From: Jakob Hauser Date: Mon, 19 Jun 2023 22:37:43 +0200 Subject: arm64: dts: qcom: msm8916-samsung-serranove: Add RT5033 PMIC with charger For the regulators, apply the same settings as in the downstream devicetree [1], including the "regulator-always-on" for the SAFE_LDO. For the voltage of SAFE_LDO, however, there is only one voltage of 4.9 V available in the mainline driver [2][3]. The values of the battery data evolve from following sources: - precharge current: 450 mA corresponds to the default value of the chip. It doesn't get changed by the downstream Android driver. Therefore let's stick to this value. - constant charge current: The 1000 mA are taken from the downstream devicetree of the serranove battery. It's not easy to spot. The value is in the line "input_current_limit" [4]. The rows are according to the power supply type, the 4th value stands for "main supply" [5]. That's the value used by the Android driver when a charging cable is plugged into the device. - charge termination current: In the downstream devicetree of the battery that's the line "full_check_current_1st", which contains the 150 mA [6]. - precharge voltage: This one doesn't get set in the downstream Android driver. The chip's default is 2.8 V. That seemed too low to have a notable effect of handling the battery gentle. The chosen value of 3.5 V is a bit arbitrary and possibly rather high. As the device is already several years old and therefore most batteries too, a value on the safe side seems reasonable. - constant charge voltage: The value of 4.35 V is set in the line "chg_float_voltage" of the downstream battery devicetree [7]. The "connector" sub-node in the extcon node, the "battery" node in the general section and the line "power-supplies" in the fuel-gauge node result from the way of implementation documented in the dt-bindings of rt5033-charger [8] and mfd rt5033 [9]. [1] https://github.com/msm8916-mainline/linux-downstream/blob/GT-I9195I/arch/arm/boot/dts/samsung/msm8916/msm8916-sec-serranovelte-eur-r03.dtsi#L135-L181 [2] https://github.com/torvalds/linux/blob/v6.3/include/linux/mfd/rt5033-private.h#L211-L212 [3] https://github.com/torvalds/linux/blob/v6.3/drivers/regulator/rt5033-regulator.c#L83 [4] https://github.com/msm8916-mainline/linux-downstream/blob/GT-I9195I/arch/arm/boot/dts/samsung/msm8916/msm8916-sec-serranovelte-battery-r01.dtsi#L100 [5] https://github.com/msm8916-mainline/linux-downstream/blob/GT-I9195I/include/linux/power_supply.h#L173-L177 [6] https://github.com/msm8916-mainline/linux-downstream/blob/GT-I9195I/arch/arm/boot/dts/samsung/msm8916/msm8916-sec-serranovelte-battery-r01.dtsi#L102 [7] https://github.com/msm8916-mainline/linux-downstream/blob/GT-I9195I/arch/arm/boot/dts/samsung/msm8916/msm8916-sec-serranovelte-battery-r01.dtsi#L95 [8] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/power/supply/richtek,rt5033-charger.yaml?h=next-20230616 [9] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/mfd/richtek,rt5033.yaml?h=next-20230616 Signed-off-by: Jakob Hauser Link: https://lore.kernel.org/r/20230619203743.8136-1-jahau@rocketmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/msm8916-samsung-serranove.dts | 64 +++++++++++++++++++++- 1 file changed, 63 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts index 15dc246e84e2..cbda25f2ad19 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts @@ -142,6 +142,12 @@ pinctrl-names = "default"; pinctrl-0 = <&muic_irq_default>; + + usb_con: connector { + compatible = "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + }; }; }; @@ -199,6 +205,15 @@ pinctrl-0 = <&nfc_default>; }; }; + + battery: battery { + compatible = "simple-battery"; + precharge-current-microamp = <450000>; + constant-charge-current-max-microamp = <1000000>; + charge-term-current-microamp = <150000>; + precharge-upper-limit-microvolt = <3500000>; + constant-charge-voltage-max-microvolt = <4350000>; + }; }; &blsp_i2c2 { @@ -228,7 +243,7 @@ &blsp_i2c4 { status = "okay"; - battery@35 { + fuel-gauge@35 { compatible = "richtek,rt5033-battery"; reg = <0x35>; @@ -237,6 +252,8 @@ pinctrl-names = "default"; pinctrl-0 = <&fg_alert_default>; + + power-supplies = <&rt5033_charger>; }; }; @@ -261,6 +278,43 @@ }; }; +&blsp_i2c6 { + status = "okay"; + + pmic@34 { + compatible = "richtek,rt5033"; + reg = <0x34>; + + interrupt-parent = <&tlmm>; + interrupts = <62 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_default>; + + regulators { + rt5033_reg_safe_ldo: SAFE_LDO { + regulator-min-microvolt = <4900000>; + regulator-max-microvolt = <4900000>; + regulator-always-on; + }; + rt5033_reg_ldo: LDO { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + rt5033_reg_buck: BUCK { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + }; + + rt5033_charger: charger { + compatible = "richtek,rt5033-charger"; + monitored-battery = <&battery>; + richtek,usb-connector = <&usb_con>; + }; + }; +}; + &blsp_uart2 { status = "okay"; }; @@ -387,6 +441,14 @@ bias-disable; }; + pmic_int_default: pmic-int-default-state { + pins = "gpio62"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + tkey_default: tkey-default-state { pins = "gpio98"; function = "gpio"; -- cgit v1.2.3-59-g8ed1b From 40b398beabdfe0e9088b13976e56b1dc706fe851 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 20 Jun 2023 13:05:34 +0200 Subject: arm64: dts: qcom: sm8250-edo: Add gpio line names for TLMM Sony ever so graciously provides GPIO line names in their downstream kernel (though sometimes they are not 100% accurate and you can judge that by simply looking at them and with what drivers they are used). Add these to the PDX203&206 DTSIs to better document the hardware. Diff between 203 and 206: < "CAM_PWR_A_CS", > "FRONTC_PWR_EN", < "CAM4_MCLK", < "TOF_RST_N", > "NC", > "NC", < "WLC_I2C_SDA", < "WLC_I2C_SCL", /* GPIO_120 */ > "NC", > "NC", < "WLC_INT_N", > "NC", Which makes sense, as 203 has a 3D iToF, slightly different camera power wiring and WLC (WireLess Charging). Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230614-topic-edo_pinsgpiopmic-v2-1-6f90bba54c53@linaro.org Signed-off-by: Bjorn Andersson --- .../dts/qcom/sm8250-sony-xperia-edo-pdx203.dts | 183 +++++++++++++++++++++ .../dts/qcom/sm8250-sony-xperia-edo-pdx206.dts | 183 +++++++++++++++++++++ 2 files changed, 366 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dts b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dts index 356a81698731..84104d2b2010 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dts @@ -14,3 +14,186 @@ }; /delete-node/ &vreg_l7f_1p8; + +&tlmm { + gpio-line-names = "AP_CTI_IN", /* GPIO_0 */ + "MDM2AP_ERR_FATAL", + "AP_CTI_OUT", + "MDM2AP_STATUS", + "NFC_I2C_SDA", + "NFC_I2C_SCL", + "NFC_EN", + "NFC_CLK_REQ", + "NFC_ESE_PWR_REQ", + "DVDT_WRT_DET_AND", + "SPK_AMP_RESET_N", /* GPIO_10 */ + "SPK_AMP_INT_N", + "APPS_I2C_1_SDA", + "APPS_I2C_1_SCL", + "NC", + "TX_GTR_THRES_IN", + "HST_BT_UART_CTS", + "HST_BT_UART_RFR", + "HST_BT_UART_TX", + "HST_BT_UART_RX", + "HST_WLAN_EN", /* GPIO_20 */ + "HST_BT_EN", + "RGBC_IR_PWR_EN", + "FP_INT_N", + "NC", + "NC", + "NC", + "NC", + "NFC_ESE_SPI_MISO", + "NFC_ESE_SPI_MOSI", + "NFC_ESE_SPI_SCLK", /* GPIO_30 */ + "NFC_ESE_SPI_CS_N", + "WCD_RST_N", + "NC", + "SDM_DEBUG_UART_TX", + "SDM_DEBUG_UART_RX", + "TS_I2C_SDA", + "TS_I2C_SCL", + "TS_INT_N", + "FP_SPI_MISO", /* GPIO_40 */ + "FP_SPI_MOSI", + "FP_SPI_SCLK", + "FP_SPI_CS_N", + "APPS_I2C_0_SDA", + "APPS_I2C_0_SCL", + "DISP_ERR_FG", + "UIM2_DETECT_EN", + "NC", + "NC", + "NC", /* GPIO_50 */ + "NC", + "MDM_UART_CTS", + "MDM_UART_RFR", + "MDM_UART_TX", + "MDM_UART_RX", + "AP2MDM_STATUS", + "AP2MDM_ERR_FATAL", + "MDM_IPC_HS_UART_TX", + "MDM_IPC_HS_UART_RX", + "NC", /* GPIO_60 */ + "NC", + "NC", + "NC", + "NC", + "USB_CC_DIR", + "DISP_VSYNC", + "NC", + "NC", + "CAM_PWR_B_CS", + "NC", /* GPIO_70 */ + "CAM_PWR_A_CS", + "SBU_SW_SEL", + "SBU_SW_OE", + "FP_RESET_N", + "FP_RESET_N", + "DISP_RESET_N", + "DEBUG_GPIO0", + "TRAY_DET", + "CAM2_RST_N", + "PCIE0_RST_N", + "PCIE0_CLK_REQ_N", /* GPIO_80 */ + "PCIE0_WAKE_N", + "DVDT_ENABLE", + "DVDT_WRT_DET_OR", + "NC", + "PCIE2_RST_N", + "PCIE2_CLK_REQ_N", + "PCIE2_WAKE_N", + "MDM_VFR_IRQ0", + "MDM_VFR_IRQ1", + "SW_SERVICE", /* GPIO_90 */ + "CAM_SOF", + "CAM1_RST_N", + "CAM0_RST_N", + "CAM0_MCLK", + "CAM1_MCLK", + "CAM2_MCLK", + "CAM3_MCLK", + "CAM4_MCLK", + "TOF_RST_N", + "NC", /* GPIO_100 */ + "CCI0_I2C_SDA", + "CCI0_I2C_SCL", + "CCI1_I2C_SDA", + "CCI1_I2C_SCL_", + "CCI2_I2C_SDA", + "CCI2_I2C_SCL", + "CCI3_I2C_SDA", + "CCI3_I2C_SCL", + "CAM3_RST_N", + "NFC_DWL_REQ", /* GPIO_110 */ + "NFC_IRQ", + "XVS", + "NC", + "RF_ID_EXTENSION", + "SPK_AMP_I2C_SDA", + "SPK_AMP_I2C_SCL", + "NC", + "NC", + "WLC_I2C_SDA", + "WLC_I2C_SCL", /* GPIO_120 */ + "ACC_COVER_OPEN", + "ALS_PROX_INT_N", + "ACCEL_INT", + "WLAN_SW_CTRL", + "CAMSENSOR_I2C_SDA", + "CAMSENSOR_I2C_SCL", + "UDON_SWITCH_SEL", + "WDOG_DISABLE", + "BAROMETER_INT", + "NC", /* GPIO_130 */ + "NC", + "FORCED_USB_BOOT", + "NC", + "NC", + "WLC_INT_N", + "NC", + "NC", + "RGBC_IR_INT", + "NC", + "NC", /* GPIO_140 */ + "NC", + "BT_SLIMBUS_CLK", + "BT_SLIMBUS_DATA", + "HW_ID_0", + "HW_ID_1", + "WCD_SWR_TX_CLK", + "WCD_SWR_TX_DATA0", + "WCD_SWR_TX_DATA1", + "WCD_SWR_RX_CLK", + "WCD_SWR_RX_DATA0", /* GPIO_150 */ + "WCD_SWR_RX_DATA1", + "SDM_DMIC_CLK1", + "SDM_DMIC_DATA1", + "SDM_DMIC_CLK2", + "SDM_DMIC_DATA2", + "SPK_AMP_I2S_CLK", + "SPK_AMP_I2S_WS", + "SPK_AMP_I2S_ASP_DIN", + "SPK_AMP_I2S_ASP_DOUT", + "COMPASS_I2C_SDA", /* GPIO_160 */ + "COMPASS_I2C_SCL", + "NC", + "NC", + "SSC_SPI_1_MISO", + "SSC_SPI_1_MOSI", + "SSC_SPI_1_CLK", + "SSC_SPI_1_CS_N", + "NC", + "NC", + "SSC_SENSOR_I2C_SDA", /* GPIO_170 */ + "SSC_SENSOR_I2C_SCL", + "NC", + "NC", + "NC", + "NC", + "HST_BLE_SNS_UART6_TX", + "HST_BLE_SNS_UART6_RX", + "HST_WLAN_UART_TX", + "HST_WLAN_UART_RX"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts index 01fe3974ee72..fae6568cb79e 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts @@ -30,6 +30,189 @@ }; }; +&tlmm { + gpio-line-names = "AP_CTI_IN", /* GPIO_0 */ + "MDM2AP_ERR_FATAL", + "AP_CTI_OUT", + "MDM2AP_STATUS", + "NFC_I2C_SDA", + "NFC_I2C_SCL", + "NFC_EN", + "NFC_CLK_REQ", + "NFC_ESE_PWR_REQ", + "DVDT_WRT_DET_AND", + "SPK_AMP_RESET_N", /* GPIO_10 */ + "SPK_AMP_INT_N", + "APPS_I2C_1_SDA", + "APPS_I2C_1_SCL", + "NC", + "TX_GTR_THRES_IN", + "HST_BT_UART_CTS", + "HST_BT_UART_RFR", + "HST_BT_UART_TX", + "HST_BT_UART_RX", + "HST_WLAN_EN", /* GPIO_20 */ + "HST_BT_EN", + "RGBC_IR_PWR_EN", + "FP_INT_N", + "NC", + "NC", + "NC", + "NC", + "NFC_ESE_SPI_MISO", + "NFC_ESE_SPI_MOSI", + "NFC_ESE_SPI_SCLK", /* GPIO_30 */ + "NFC_ESE_SPI_CS_N", + "WCD_RST_N", + "NC", + "SDM_DEBUG_UART_TX", + "SDM_DEBUG_UART_RX", + "TS_I2C_SDA", + "TS_I2C_SCL", + "TS_INT_N", + "FP_SPI_MISO", /* GPIO_40 */ + "FP_SPI_MOSI", + "FP_SPI_SCLK", + "FP_SPI_CS_N", + "APPS_I2C_0_SDA", + "APPS_I2C_0_SCL", + "DISP_ERR_FG", + "UIM2_DETECT_EN", + "NC", + "NC", + "NC", /* GPIO_50 */ + "NC", + "MDM_UART_CTS", + "MDM_UART_RFR", + "MDM_UART_TX", + "MDM_UART_RX", + "AP2MDM_STATUS", + "AP2MDM_ERR_FATAL", + "MDM_IPC_HS_UART_TX", + "MDM_IPC_HS_UART_RX", + "NC", /* GPIO_60 */ + "NC", + "NC", + "NC", + "NC", + "USB_CC_DIR", + "DISP_VSYNC", + "NC", + "NC", + "CAM_PWR_B_CS", + "NC", /* GPIO_70 */ + "FRONTC_PWR_EN", + "SBU_SW_SEL", + "SBU_SW_OE", + "FP_RESET_N", + "FP_RESET_N", + "DISP_RESET_N", + "DEBUG_GPIO0", + "TRAY_DET", + "CAM2_RST_N", + "PCIE0_RST_N", + "PCIE0_CLK_REQ_N", /* GPIO_80 */ + "PCIE0_WAKE_N", + "DVDT_ENABLE", + "DVDT_WRT_DET_OR", + "NC", + "PCIE2_RST_N", + "PCIE2_CLK_REQ_N", + "PCIE2_WAKE_N", + "MDM_VFR_IRQ0", + "MDM_VFR_IRQ1", + "SW_SERVICE", /* GPIO_90 */ + "CAM_SOF", + "CAM1_RST_N", + "CAM0_RST_N", + "CAM0_MCLK", + "CAM1_MCLK", + "CAM2_MCLK", + "CAM3_MCLK", + "NC", + "NC", + "NC", /* GPIO_100 */ + "CCI0_I2C_SDA", + "CCI0_I2C_SCL", + "CCI1_I2C_SDA", + "CCI1_I2C_SCL_", + "CCI2_I2C_SDA", + "CCI2_I2C_SCL", + "CCI3_I2C_SDA", + "CCI3_I2C_SCL", + "CAM3_RST_N", + "NFC_DWL_REQ", /* GPIO_110 */ + "NFC_IRQ", + "XVS", + "NC", + "RF_ID_EXTENSION", + "SPK_AMP_I2C_SDA", + "SPK_AMP_I2C_SCL", + "NC", + "NC", + "NC", + "NC", + "ACC_COVER_OPEN", + "ALS_PROX_INT_N", + "ACCEL_INT", + "WLAN_SW_CTRL", + "CAMSENSOR_I2C_SDA", + "CAMSENSOR_I2C_SCL", + "UDON_SWITCH_SEL", + "WDOG_DISABLE", + "BAROMETER_INT", + "NC", /* GPIO_130 */ + "NC", + "FORCED_USB_BOOT", + "NC", + "NC", + "NC", + "NC", + "NC", + "RGBC_IR_INT", + "NC", + "NC", /* GPIO_140 */ + "NC", + "BT_SLIMBUS_CLK", + "BT_SLIMBUS_DATA", + "HW_ID_0", + "HW_ID_1", + "WCD_SWR_TX_CLK", + "WCD_SWR_TX_DATA0", + "WCD_SWR_TX_DATA1", + "WCD_SWR_RX_CLK", + "WCD_SWR_RX_DATA0", /* GPIO_150 */ + "WCD_SWR_RX_DATA1", + "SDM_DMIC_CLK1", + "SDM_DMIC_DATA1", + "SDM_DMIC_CLK2", + "SDM_DMIC_DATA2", + "SPK_AMP_I2S_CLK", + "SPK_AMP_I2S_WS", + "SPK_AMP_I2S_ASP_DIN", + "SPK_AMP_I2S_ASP_DOUT", + "COMPASS_I2C_SDA", /* GPIO_160 */ + "COMPASS_I2C_SCL", + "NC", + "NC", + "SSC_SPI_1_MISO", + "SSC_SPI_1_MOSI", + "SSC_SPI_1_CLK", + "SSC_SPI_1_CS_N", + "NC", + "NC", + "SSC_SENSOR_I2C_SDA", /* GPIO_170 */ + "SSC_SENSOR_I2C_SCL", + "NC", + "NC", + "NC", + "NC", + "HST_BLE_SNS_UART6_TX", + "HST_BLE_SNS_UART6_RX", + "HST_WLAN_UART_TX", + "HST_WLAN_UART_RX"; +}; + &vreg_l2f_1p3 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; -- cgit v1.2.3-59-g8ed1b From 6b8a63350752c6a5e4b54f2de6174084652cd3cd Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 20 Jun 2023 13:05:35 +0200 Subject: arm64: dts: qcom: sm8250-edo: Add GPIO line names for PMIC GPIOs Sony ever so graciously provides GPIO line names in their downstream kernel (though sometimes they are not 100% accurate and you can judge that by simply looking at them and with what drivers they are used). Add these to the PDX203&206 DTSIs to better document the hardware. Diff between 203 and 206: pm8009_gpios < "CAM_PWR_LD_EN", > "NC", pm8150_gpios < "NC", > "G_ASSIST_N", < "WLC_EN_N", /* GPIO_10 */ > "NC", /* GPIO_10 */ Which is due to 5 II having an additional Google Assistant hardware button and 1 II having a wireless charger & different camera wiring to accommodate the additional 3D iToF sensor. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230614-topic-edo_pinsgpiopmic-v2-2-6f90bba54c53@linaro.org Signed-off-by: Bjorn Andersson --- .../dts/qcom/sm8250-sony-xperia-edo-pdx203.dts | 50 ++++++++++++++++++++++ .../dts/qcom/sm8250-sony-xperia-edo-pdx206.dts | 50 ++++++++++++++++++++++ 2 files changed, 100 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dts b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dts index 84104d2b2010..62590c6bd306 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dts @@ -15,6 +15,56 @@ /delete-node/ &vreg_l7f_1p8; +&pm8009_gpios { + gpio-line-names = "NC", /* GPIO_1 */ + "CAM_PWR_LD_EN", + "WIDEC_PWR_EN", + "NC"; +}; + +&pm8150_gpios { + gpio-line-names = "VOL_DOWN_N", /* GPIO_1 */ + "OPTION_2", + "NC", + "PM_SLP_CLK_IN", + "OPTION_1", + "NC", + "NC", + "SP_ARI_PWR_ALARM", + "NC", + "NC"; /* GPIO_10 */ +}; + +&pm8150b_gpios { + gpio-line-names = "SNAPSHOT_N", /* GPIO_1 */ + "FOCUS_N", + "NC", + "NC", + "RF_LCD_ID_EN", + "NC", + "NC", + "LCD_ID", + "NC", + "WLC_EN_N", /* GPIO_10 */ + "NC", + "RF_ID"; +}; + +&pm8150l_gpios { + gpio-line-names = "NC", /* GPIO_1 */ + "PM3003A_EN", + "NC", + "NC", + "NC", + "AUX2_THERM", + "BB_HP_EN", + "FP_LDO_EN", + "PMX_RESET_N", + "AUX3_THERM", /* GPIO_10 */ + "DTV_PWR_EN", + "PM3003A_MODE"; +}; + &tlmm { gpio-line-names = "AP_CTI_IN", /* GPIO_0 */ "MDM2AP_ERR_FATAL", diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts index fae6568cb79e..ea4571bf4fbf 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts @@ -30,6 +30,56 @@ }; }; +&pm8009_gpios { + gpio-line-names = "NC", /* GPIO_1 */ + "NC", + "WIDEC_PWR_EN", + "NC"; +}; + +&pm8150_gpios { + gpio-line-names = "VOL_DOWN_N", /* GPIO_1 */ + "OPTION_2", + "NC", + "PM_SLP_CLK_IN", + "OPTION_1", + "G_ASSIST_N", + "NC", + "SP_ARI_PWR_ALARM", + "NC", + "NC"; /* GPIO_10 */ +}; + +&pm8150b_gpios { + gpio-line-names = "SNAPSHOT_N", /* GPIO_1 */ + "FOCUS_N", + "NC", + "NC", + "RF_LCD_ID_EN", + "NC", + "NC", + "LCD_ID", + "NC", + "NC", /* GPIO_10 */ + "NC", + "RF_ID"; +}; + +&pm8150l_gpios { + gpio-line-names = "NC", /* GPIO_1 */ + "PM3003A_EN", + "NC", + "NC", + "NC", + "AUX2_THERM", + "BB_HP_EN", + "FP_LDO_EN", + "PMX_RESET_N", + "NC", /* GPIO_10 */ + "NC", + "PM3003A_MODE"; +}; + &tlmm { gpio-line-names = "AP_CTI_IN", /* GPIO_0 */ "MDM2AP_ERR_FATAL", -- cgit v1.2.3-59-g8ed1b From 2de55db6bca0856ecbff5c288dc330af94c8e5b1 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 20 Jun 2023 13:05:36 +0200 Subject: arm64: dts: qcom: sm8250-pdx203: Configure SLG51000 PMIC Xperia 1 II / PRO use the Dialog SLG51000 PMIC for powering some camera sensors. Add the required nodes to support it and remove its remnants from -edo.dtsi, as it's absent on 5 II. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230614-topic-edo_pinsgpiopmic-v2-3-6f90bba54c53@linaro.org Signed-off-by: Bjorn Andersson --- .../dts/qcom/sm8250-sony-xperia-edo-pdx203.dts | 131 +++++++++++++++++++++ .../boot/dts/qcom/sm8250-sony-xperia-edo.dtsi | 7 -- 2 files changed, 131 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dts b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dts index 62590c6bd306..f4c4575eb03b 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dts @@ -15,6 +15,123 @@ /delete-node/ &vreg_l7f_1p8; +&i2c5 { + clock-frequency = <400000>; + status = "okay"; + + pmic@75 { + compatible = "dlg,slg51000"; + reg = <0x75>; + dlg,cs-gpios = <&tlmm 69 GPIO_ACTIVE_HIGH>; + vin5-supply = <&vreg_s1f_1p2>; + vin6-supply = <&vreg_s1f_1p2>; + + pinctrl-0 = <&cam_pwr_b_cs>; + pinctrl-names = "default"; + + regulators { + slg51000_1_ldo1: ldo1 { + regulator-name = "slg51000_b_ldo1"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + }; + + slg51000_1_ldo2: ldo2 { + regulator-name = "slg51000_b_ldo2"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + }; + + slg51000_1_ldo3: ldo3 { + regulator-name = "slg51000_b_ldo3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + + slg51000_1_ldo4: ldo4 { + regulator-name = "slg51000_b_ldo4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + + slg51000_1_ldo5: ldo5 { + regulator-name = "slg51000_b_ldo5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1200000>; + }; + + slg51000_1_ldo6: ldo6 { + regulator-name = "slg51000_b_ldo6"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1200000>; + }; + + slg51000_1_ldo7: ldo7 { + regulator-name = "slg51000_b_ldo7"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + }; + }; +}; + +&i2c15 { + pmic@75 { + compatible = "dlg,slg51000"; + reg = <0x75>; + dlg,cs-gpios = <&tlmm 71 GPIO_ACTIVE_HIGH>; + vin5-supply = <&vreg_l2f_1p3>; + vin6-supply = <&vreg_l2f_1p3>; + + pinctrl-0 = <&cam_pwr_a_cs>; + pinctrl-names = "default"; + + regulators { + slg51000_0_ldo1: ldo1 { + regulator-name = "slg51000_a_ldo1"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + }; + + slg51000_0_ldo2: ldo2 { + regulator-name = "slg51000_a_ldo2"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + }; + + slg51000_0_ldo3: ldo3 { + regulator-name = "slg51000_a_ldo3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + + slg51000_0_ldo4: ldo4 { + regulator-name = "slg51000_a_ldo4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + + slg51000_0_ldo5: ldo5 { + regulator-name = "slg51000_a_ldo5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1200000>; + }; + + slg51000_0_ldo6: ldo6 { + regulator-name = "slg51000_a_ldo6"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1200000>; + }; + + slg51000_0_ldo7: ldo7 { + regulator-name = "slg51000_a_ldo7"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + }; + }; +}; + &pm8009_gpios { gpio-line-names = "NC", /* GPIO_1 */ "CAM_PWR_LD_EN", @@ -246,4 +363,18 @@ "HST_BLE_SNS_UART6_RX", "HST_WLAN_UART_TX", "HST_WLAN_UART_RX"; + + cam_pwr_b_cs: cam-pwr-b-state { + pins = "gpio69"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + cam_pwr_a_cs: cam-pwr-a-state { + pins = "gpio71"; + drive-strength = <2>; + bias-disable; + output-low; + }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index 9f3ea8d8d798..c88d125f5285 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -486,13 +486,6 @@ }; }; -&i2c5 { - status = "okay"; - clock-frequency = <400000>; - - /* Dialog SLG51000 CMIC @ 75 */ -}; - &i2c9 { status = "okay"; clock-frequency = <400000>; -- cgit v1.2.3-59-g8ed1b From a422c6a91a667b309ca1a6c08b30dbfcf7d4e866 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 20 Jun 2023 13:05:37 +0200 Subject: arm64: dts: qcom: sm8250-edo: Rectify gpio-keys Set up the corresponding GPIOs properly and add the leftover hardware buttons to mark this piece of the puzzle complete. Fixes: 46e14907c716 ("arm64: dts: qcom: sm8250-edo: Add hardware keys") Reviewed-by: Marijn Suijten Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230614-topic-edo_pinsgpiopmic-v2-4-6f90bba54c53@linaro.org Signed-off-by: Bjorn Andersson --- .../dts/qcom/sm8250-sony-xperia-edo-pdx206.dts | 10 ++++ .../boot/dts/qcom/sm8250-sony-xperia-edo.dtsi | 54 +++++++++++++++++++--- 2 files changed, 58 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts index ea4571bf4fbf..58a521046f5f 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts @@ -20,6 +20,8 @@ }; &gpio_keys { + pinctrl-0 = <&focus_n &snapshot_n &vol_down_n &g_assist_n>; + g-assist-key { label = "Google Assistant Key"; linux,code = ; @@ -48,6 +50,14 @@ "SP_ARI_PWR_ALARM", "NC", "NC"; /* GPIO_10 */ + + g_assist_n: g-assist-n-state { + pins = "gpio6"; + function = "normal"; + power-source = <1>; + bias-pull-up; + input-enable; + }; }; &pm8150b_gpios { diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index c88d125f5285..cd27794739a5 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -51,12 +51,26 @@ gpio_keys: gpio-keys { compatible = "gpio-keys"; - /* - * Camera focus (light press) and camera snapshot (full press) - * seem not to work properly.. Adding the former one stalls the CPU - * and the latter kills the volume down key for whatever reason. In any - * case, they are both on &pm8150b_gpios: camera focus(2), camera snapshot(1). - */ + pinctrl-0 = <&focus_n &snapshot_n &vol_down_n>; + pinctrl-names = "default"; + + key-camera-focus { + label = "Camera Focus"; + linux,code = ; + gpios = <&pm8150b_gpios 2 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + gpio-key,wakeup; + }; + + key-camera-snapshot { + label = "Camera Snapshot"; + linux,code = ; + gpios = <&pm8150b_gpios 1 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + gpio-key,wakeup; + }; key-vol-down { label = "Volume Down"; @@ -544,6 +558,34 @@ vdda-pll-supply = <&vreg_l9a_1p2>; }; +&pm8150_gpios { + vol_down_n: vol-down-n-state { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + bias-pull-up; + input-enable; + }; +}; + +&pm8150b_gpios { + snapshot_n: snapshot-n-state { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + bias-pull-up; + input-enable; + }; + + focus_n: focus-n-state { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + bias-pull-up; + input-enable; + }; +}; + &pon_pwrkey { status = "okay"; }; -- cgit v1.2.3-59-g8ed1b From 9566b5271f68bdf6e69b7c511850e3fb75cd18be Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 20 Jun 2023 13:39:14 -0700 Subject: arm64: dts: qcom: sc8280xp-crd: Correct vreg_misc_3p3 GPIO The vreg_misc_3p3 regulator is controlled by PMC8280_1 GPIO 2, not 1, on the CRD. Fixes: ccd3517faf18 ("arm64: dts: qcom: sc8280xp: Add reference device") Signed-off-by: Bjorn Andersson Reviewed-by: Johan Hovold Tested-by: Johan Hovold Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230620203915.141337-1-quic_bjorande@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index 4fb5e240275d..d5ae8957c986 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -167,7 +167,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&pmc8280_1_gpios 1 GPIO_ACTIVE_HIGH>; + gpio = <&pmc8280_1_gpios 2 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-names = "default"; @@ -755,7 +755,7 @@ }; misc_3p3_reg_en: misc-3p3-reg-en-state { - pins = "gpio1"; + pins = "gpio2"; function = "normal"; }; }; -- cgit v1.2.3-59-g8ed1b From 8882ae076344f8b4e9f1e5a116e1a83c4292b790 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 20 Jun 2023 13:39:15 -0700 Subject: arm64: dts: qcom: sc8280xp-crd: Fix naming of regulators The external regulators in the CRD seems to have inherited their names from the X13s DeviceTree, correct them. Signed-off-by: Bjorn Andersson Reviewed-by: Johan Hovold Link: https://lore.kernel.org/r/20230620203915.141337-2-quic_bjorande@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index d5ae8957c986..e4861c61a65b 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -133,7 +133,7 @@ vreg_edp_bl: regulator-edp-bl { compatible = "regulator-fixed"; - regulator-name = "VBL9"; + regulator-name = "VREG_EDP_BL"; regulator-min-microvolt = <3600000>; regulator-max-microvolt = <3600000>; @@ -149,7 +149,7 @@ vreg_nvme: regulator-nvme { compatible = "regulator-fixed"; - regulator-name = "VCC3_SSD"; + regulator-name = "VREG_NVME_3P3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -163,7 +163,7 @@ vreg_misc_3p3: regulator-misc-3p3 { compatible = "regulator-fixed"; - regulator-name = "VCC3B"; + regulator-name = "VREG_MISC_3P3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -180,7 +180,7 @@ vreg_wlan: regulator-wlan { compatible = "regulator-fixed"; - regulator-name = "VCC_WLAN_3R9"; + regulator-name = "VPH_PWR_WLAN"; regulator-min-microvolt = <3900000>; regulator-max-microvolt = <3900000>; @@ -196,7 +196,7 @@ vreg_wwan: regulator-wwan { compatible = "regulator-fixed"; - regulator-name = "VCC3B_WAN"; + regulator-name = "SDX_VPH_PWR"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; -- cgit v1.2.3-59-g8ed1b From 11750af256f8287f853daed0424eac726dcc5b9f Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 21 Jun 2023 13:21:52 +0200 Subject: arm64: dts: qcom: sm6115: Add GPU nodes Introduce nodes for the A610 GPU and its GMU wrapper along with the speedbin fuse entry in QFPROM. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230620-topic-gpu_tablet_disp-v2-1-0538ea1beb0b@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 103 +++++++++++++++++++++++++++++++++++ 1 file changed, 103 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 55118577bf92..424b4f3c909b 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -865,6 +865,11 @@ reg = <0x25b 0x1>; bits = <1 4>; }; + + gpu_speed_bin: gpu-speed-bin@6006 { + reg = <0x6006 0x2>; + bits = <5 8>; + }; }; rng: rng@1b53000 { @@ -1316,6 +1321,104 @@ }; }; + gpu: gpu@5900000 { + compatible = "qcom,adreno-610.0", "qcom,adreno"; + reg = <0x0 0x05900000 0x0 0x40000>; + reg-names = "kgsl_3d0_reg_memory"; + + /* There's no (real) GMU, so we have to handle quite a bunch of clocks! */ + clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gcc GCC_BIMC_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>; + clock-names = "core", + "iface", + "mem_iface", + "alt_mem_iface", + "gmu", + "xo"; + + interrupts = ; + + iommus = <&adreno_smmu 0 1>; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&rpmpd SM6115_VDDCX>; + qcom,gmu = <&gmu_wrapper>; + + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + + status = "disabled"; + + zap-shader { + memory-region = <&pil_gpu_mem>; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-320000000 { + opp-hz = /bits/ 64 <320000000>; + required-opps = <&rpmpd_opp_low_svs>; + opp-supported-hw = <0x1f>; + }; + + opp-465000000 { + opp-hz = /bits/ 64 <465000000>; + required-opps = <&rpmpd_opp_svs>; + opp-supported-hw = <0x1f>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmpd_opp_svs_plus>; + opp-supported-hw = <0x1f>; + }; + + opp-745000000 { + opp-hz = /bits/ 64 <745000000>; + required-opps = <&rpmpd_opp_nom>; + opp-supported-hw = <0xf>; + }; + + opp-820000000 { + opp-hz = /bits/ 64 <820000000>; + required-opps = <&rpmpd_opp_nom_plus>; + opp-supported-hw = <0x7>; + }; + + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + required-opps = <&rpmpd_opp_turbo>; + opp-supported-hw = <0x7>; + }; + + /* Speed bin 2 can reach 950 Mhz instead of 980 like the rest. */ + opp-950000000 { + opp-hz = /bits/ 64 <950000000>; + required-opps = <&rpmpd_opp_turbo_plus>; + opp-supported-hw = <0x4>; + }; + + opp-980000000 { + opp-hz = /bits/ 64 <980000000>; + required-opps = <&rpmpd_opp_turbo_plus>; + opp-supported-hw = <0x3>; + }; + }; + }; + + gmu_wrapper: gmu@596a000 { + compatible = "qcom,adreno-gmu-wrapper"; + reg = <0x0 0x0596a000 0x0 0x30000>; + reg-names = "gmu"; + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", "gx"; + }; + gpucc: clock-controller@5990000 { compatible = "qcom,sm6115-gpucc"; reg = <0x0 0x05990000 0x0 0x9000>; -- cgit v1.2.3-59-g8ed1b From e3dc814d8ca0fb3c8e2760d004ea048e502887a4 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 21 Jun 2023 13:21:53 +0200 Subject: arm64: dts: qcom: sm6115p-j606f: Hook up display Enable the required nodes, add the required pins and tweak a regulator to enable non-simplefb display on the Tab P11. Do note that there exists a second SKU with a different panel+touch combo, but due to insufficient information, that will need to be handled separately. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20230620-topic-gpu_tablet_disp-v2-2-0538ea1beb0b@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts | 57 +++++++++++++++++++++-- 1 file changed, 52 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts index 81fdcaf48926..667273ae0553 100644 --- a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts +++ b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts @@ -65,9 +65,41 @@ }; }; -&dispcc { - /* HACK: disable until a panel driver is ready to retain simplefb */ - status = "disabled"; +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&pm6125_l18>; + status = "okay"; + + panel: panel@0 { + compatible = "lenovo,j606f-boe-nt36523w", "novatek,nt36523w"; + reg = <0>; + + reset-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; + vddio-supply = <&pm6125_l9>; + + pinctrl-names = "default"; + pinctrl-0 = <&te_active &mdss_dsi_active>; + + rotation = <180>; /* Yep, it's mounted upside down! */ + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&panel_in>; +}; + +&mdss_dsi0_phy { + status = "okay"; }; &pm6125_gpios { @@ -212,8 +244,9 @@ }; pm6125_l18: l18 { - regulator-min-microvolt = <1104000>; - regulator-max-microvolt = <1312000>; + /* 1.104V-1.312V fixed @ 1.232V for DSIPHY */ + regulator-min-microvolt = <1232000>; + regulator-max-microvolt = <1232000>; }; pm6125_l19: l19 { @@ -282,6 +315,20 @@ bias-pull-up; output-high; }; + + te_active: te-active-state { + pins = "gpio81"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + mdss_dsi_active: dsi-active-state { + pins = "gpio82"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; }; &ufs_mem_hc { -- cgit v1.2.3-59-g8ed1b From be9f88abf8695b59f17ac0ef365cd2d2a9baae78 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 21 Jun 2023 13:21:54 +0200 Subject: arm64: dts: qcom: sm6115p-j606f: Enable GPU Enable the A610 GPU and provide a firmware path to the ZAP blob. Reviewed-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230620-topic-gpu_tablet_disp-v2-3-0538ea1beb0b@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts index 667273ae0553..c2d15fc6c96b 100644 --- a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts +++ b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts @@ -65,6 +65,14 @@ }; }; +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/sm6115/LENOVO/J606F/a610_zap.mbn"; + }; +}; + &mdss { status = "okay"; }; -- cgit v1.2.3-59-g8ed1b From d368279dfa02c6c1eb5eb91126613769527d450b Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 21 Jun 2023 13:21:55 +0200 Subject: arm64: dts: qcom: qrb4210-rb2: Enable GPU Enable the A610 GPU and provide a firmware path to the ZAP blob. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230620-topic-gpu_tablet_disp-v2-4-0538ea1beb0b@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb4210-rb2.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index e23a0406eacc..a7278a9472ed 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -179,6 +179,14 @@ status = "okay"; }; +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/qrb4210/a610_zap.mbn"; + }; +}; + &i2c2 { clock-frequency = <400000>; status = "okay"; -- cgit v1.2.3-59-g8ed1b From 38c6fe604bc21530b3df16c79a7a96bdc42a0e93 Mon Sep 17 00:00:00 2001 From: Raymond Hackley Date: Thu, 22 Jun 2023 02:11:14 +0000 Subject: arm64: dts: qcom: msm8939-sony-xperia-kanuti-tulip: Add missing 'chassis-type' Sony Xperia M4 Aqua is a handset. Add the chassis-type = "handset"; to it. Signed-off-by: Raymond Hackley Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230622021105.66015-1-raymondhackley@protonmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts b/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts index 8613cf93dac5..0633e3006f17 100644 --- a/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts +++ b/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts @@ -16,6 +16,7 @@ / { model = "Sony Xperia M4 Aqua"; compatible = "sony,kanuti-tulip", "qcom,msm8939"; + chassis-type = "handset"; qcom,board-id = ; qcom,msm-id = , ; -- cgit v1.2.3-59-g8ed1b From 46b17dfd0154b3720b22a4056c0f060ba0c7ec66 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 22 Jun 2023 10:57:18 +0200 Subject: arm64: dts: qcom: sm8[1235]50-mtp: add chassis-type property Qualcomm's Mobile Test Platforms devices are handsets, set the chassis-type property to 'handset'. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230622-topic-sm8x50-upstream-chassis-type-v1-1-13f676eb71f3@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 1 + arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 1 + arch/arm64/boot/dts/qcom/sm8350-mtp.dts | 1 + arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 1 + 4 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts index 34ec84916bdd..286350ac7751 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts @@ -16,6 +16,7 @@ / { model = "Qualcomm Technologies, Inc. SM8150 MTP"; compatible = "qcom,sm8150-mtp", "qcom,sm8150"; + chassis-type = "handset"; aliases { serial0 = &uart2; diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index 4c9de236676d..ad2b60e281eb 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -18,6 +18,7 @@ / { model = "Qualcomm Technologies, Inc. SM8250 MTP"; compatible = "qcom,sm8250-mtp", "qcom,sm8250"; + chassis-type = "handset"; aliases { serial0 = &uart12; diff --git a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts index d21d2aacf201..c5a6c8745606 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts @@ -17,6 +17,7 @@ / { model = "Qualcomm Technologies, Inc. sm8350 MTP"; compatible = "qcom,sm8350-mtp", "qcom,sm8350"; + chassis-type = "handset"; aliases { serial0 = &uart2; diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index ec86c5f38045..00c7e1704a8c 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -18,6 +18,7 @@ / { model = "Qualcomm Technologies, Inc. SM8550 MTP"; compatible = "qcom,sm8550-mtp", "qcom,sm8550"; + chassis-type = "handset"; aliases { serial0 = &uart7; -- cgit v1.2.3-59-g8ed1b From b047b90261791fd439dfd0d885e1a3e995c05985 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 22 Jun 2023 10:57:19 +0200 Subject: arm64: dts: qcom: sm8[45]50-qrd: add chassis-type property Qualcomm's Reference Devices are handsets, set the chassis-type property to 'handset'. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230622-topic-sm8x50-upstream-chassis-type-v1-2-13f676eb71f3@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 1 + arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index 65a94dfaf5ae..37479327707f 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -18,6 +18,7 @@ / { model = "Qualcomm Technologies, Inc. SM8450 QRD"; compatible = "qcom,sm8450-qrd", "qcom,sm8450"; + chassis-type = "handset"; aliases { serial0 = &uart7; diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index ec4feee6837d..3bf4121e36ce 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -19,6 +19,7 @@ / { model = "Qualcomm Technologies, Inc. SM8550 QRD"; compatible = "qcom,sm8550-qrd", "qcom,sm8550"; + chassis-type = "handset"; aliases { serial0 = &uart7; -- cgit v1.2.3-59-g8ed1b From 8fef2422f53a84ec32f9d7ac8d6af1fa9426e835 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 22 Jun 2023 10:57:20 +0200 Subject: arm64: dts: qcom: sm8[1234]50-hdk: add chassis-type property Qualcomm's Hardware Development Kits devices are embedded platforms, set the chassis-type property to 'embedded'. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230622-topic-sm8x50-upstream-chassis-type-v1-3-13f676eb71f3@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150-hdk.dts | 1 + arch/arm64/boot/dts/qcom/sm8250-hdk.dts | 1 + arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 1 + arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 1 + 4 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts index c0200e7f3f74..bb161b536da4 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts @@ -15,6 +15,7 @@ / { model = "Qualcomm Technologies, Inc. SM8150 HDK"; compatible = "qcom,sm8150-hdk", "qcom,sm8150"; + chassis-type = "embedded"; aliases { serial0 = &uart2; diff --git a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts index 0aee7f8658b4..1bbb71e1a4fc 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts @@ -14,6 +14,7 @@ / { model = "Qualcomm Technologies, Inc. SM8250 HDK"; compatible = "qcom,sm8250-hdk", "qcom,sm8250"; + chassis-type = "embedded"; aliases { serial0 = &uart12; diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index 95a2a42ccb9e..939e169b703a 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -11,6 +11,7 @@ / { model = "Qualcomm Technologies, Inc. SM8350 HDK"; compatible = "qcom,sm8350-hdk", "qcom,sm8350"; + chassis-type = "embedded"; aliases { serial0 = &uart2; diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index e5cbea92e07a..7e6564a112ee 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -19,6 +19,7 @@ / { model = "Qualcomm Technologies, Inc. SM8450 HDK"; compatible = "qcom,sm8450-hdk", "qcom,sm8450"; + chassis-type = "embedded"; aliases { serial0 = &uart7; -- cgit v1.2.3-59-g8ed1b From d8d1d994246f7d44241c5332817c8e850e1b2e73 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 22 Jun 2023 10:57:21 +0200 Subject: arm64: dts: qcom: msm89xx-mtp: add chassis-type property Qualcomm's Mobile Test Platforms devices are handsets, set the chassis-type property to 'handset'. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230622-topic-sm8x50-upstream-chassis-type-v1-4-13f676eb71f3@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916-mtp.dts | 1 + arch/arm64/boot/dts/qcom/msm8996-mtp.dts | 1 + arch/arm64/boot/dts/qcom/msm8998-mtp.dts | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-mtp.dts b/arch/arm64/boot/dts/qcom/msm8916-mtp.dts index 438eb1faee1d..ac527a3a0826 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-mtp.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-mtp.dts @@ -10,6 +10,7 @@ / { model = "Qualcomm Technologies, Inc. MSM 8916 MTP"; compatible = "qcom,msm8916-mtp", "qcom,msm8916-mtp/1", "qcom,msm8916"; + chassis-type = "handset"; aliases { serial0 = &blsp_uart2; diff --git a/arch/arm64/boot/dts/qcom/msm8996-mtp.dts b/arch/arm64/boot/dts/qcom/msm8996-mtp.dts index 495d45a16e63..6e9c9caf25b1 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-mtp.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-mtp.dts @@ -10,6 +10,7 @@ / { model = "Qualcomm Technologies, Inc. MSM 8996 MTP"; compatible = "qcom,msm8996-mtp", "qcom,msm8996"; + chassis-type = "handset"; aliases { serial0 = &blsp2_uart2; diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dts b/arch/arm64/boot/dts/qcom/msm8998-mtp.dts index 453a1c9e9808..4319f4da8996 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-mtp.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-mtp.dts @@ -11,6 +11,7 @@ / { model = "Qualcomm Technologies, Inc. MSM8998 v1 MTP"; compatible = "qcom,msm8998-mtp", "qcom,msm8998"; + chassis-type = "handset"; qcom,board-id = <8 0>; -- cgit v1.2.3-59-g8ed1b From 2b08da0d791ff08e1c29ee3abd2563ce0a9da7b9 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 22 Jun 2023 10:57:22 +0200 Subject: arm64: dts: qcom: sdm845-mtp: add chassis-type property Qualcomm's Mobile Test Platforms devices are handsets, set the chassis-type property to 'handset'. Signed-off-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230622-topic-sm8x50-upstream-chassis-type-v1-5-13f676eb71f3@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index b2d4336e764b..41675a8de268 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -15,6 +15,7 @@ / { model = "Qualcomm Technologies, Inc. SDM845 MTP"; compatible = "qcom,sdm845-mtp", "qcom,sdm845"; + chassis-type = "handset"; aliases { serial0 = &uart9; -- cgit v1.2.3-59-g8ed1b From 683ef77158cbb56ede2a524751b150cec340128a Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 22 Jun 2023 14:01:38 +0200 Subject: arm64: dts: qcom: sa8775p: add the SGMII PHY node Add the internal SGMII/SerDes PHY node for sa8775p platforms. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Tested-by: Andrew Halaney Link: https://lore.kernel.org/r/20230622120142.218055-2-brgl@bgdev.pl Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index b130136acffe..b6d95813c98c 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -1837,6 +1837,15 @@ ; }; + serdes0: phy@8901000 { + compatible = "qcom,sa8775p-dwmac-sgmii-phy"; + reg = <0x0 0x08901000 0x0 0xe10>; + clocks = <&gcc GCC_SGMI_CLKREF_EN>; + clock-names = "sgmi_ref"; + #phy-cells = <0>; + status = "disabled"; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sa8775p-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x30000>, -- cgit v1.2.3-59-g8ed1b From ff499a0fbb2352bff15d75c13afe46decf90d7eb Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 22 Jun 2023 14:01:39 +0200 Subject: arm64: dts: qcom: sa8775p: add the first 1Gb ethernet interface Add the node for the first ethernet interface on sa8775p platforms. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Tested-by: Andrew Halaney Link: https://lore.kernel.org/r/20230622120142.218055-3-brgl@bgdev.pl Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index b6d95813c98c..59eedfc9c2cb 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -2315,6 +2315,39 @@ #freq-domain-cells = <1>; }; + + ethernet0: ethernet@23040000 { + compatible = "qcom,sa8775p-ethqos"; + reg = <0x0 0x23040000 0x0 0x10000>, + <0x0 0x23056000 0x0 0x100>; + reg-names = "stmmaceth", "rgmii"; + + interrupts = ; + interrupt-names = "macirq"; + + clocks = <&gcc GCC_EMAC0_AXI_CLK>, + <&gcc GCC_EMAC0_SLV_AHB_CLK>, + <&gcc GCC_EMAC0_PTP_CLK>, + <&gcc GCC_EMAC0_PHY_AUX_CLK>; + clock-names = "stmmaceth", + "pclk", + "ptp_ref", + "phyaux"; + + power-domains = <&gcc EMAC0_GDSC>; + + phys = <&serdes0>; + phy-names = "serdes"; + + iommus = <&apps_smmu 0x120 0xf>; + + snps,tso; + snps,pbl = <32>; + rx-fifo-depth = <16384>; + tx-fifo-depth = <16384>; + + status = "disabled"; + }; }; arch_timer: timer { -- cgit v1.2.3-59-g8ed1b From 5ef26fb8b3ed72cc5beb6461c258127e3a388247 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 22 Jun 2023 14:01:40 +0200 Subject: arm64: dts: qcom: sa8775p-ride: enable the SerDes PHY Enable the internal PHY on sa8775p-ride. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Tested-by: Andrew Halaney Link: https://lore.kernel.org/r/20230622120142.218055-4-brgl@bgdev.pl Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index ab767cfa51ff..9f39ab59c283 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -355,6 +355,11 @@ status = "okay"; }; +&serdes0 { + phy-supply = <&vreg_l5a>; + status = "okay"; +}; + &sleep_clk { clock-frequency = <32764>; }; -- cgit v1.2.3-59-g8ed1b From 48c99529998026e21a78f84261d24c0b93c1027e Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 22 Jun 2023 14:01:41 +0200 Subject: arm64: dts: qcom: sa8775p-ride: add pin functions for ethernet0 Add the MDC and MDIO pin functions for ethernet0 on sa8775p-ride. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Tested-by: Andrew Halaney Link: https://lore.kernel.org/r/20230622120142.218055-5-brgl@bgdev.pl Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index 9f39ab59c283..bf90f825ff67 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -371,6 +371,22 @@ }; &tlmm { + ethernet0_default: ethernet0-default-state { + ethernet0_mdc: ethernet0-mdc-pins { + pins = "gpio8"; + function = "emac0_mdc"; + drive-strength = <16>; + bias-pull-up; + }; + + ethernet0_mdio: ethernet0-mdio-pins { + pins = "gpio9"; + function = "emac0_mdio"; + drive-strength = <16>; + bias-pull-up; + }; + }; + qup_uart10_default: qup-uart10-state { pins = "gpio46", "gpio47"; function = "qup1_se3"; -- cgit v1.2.3-59-g8ed1b From 120ab6c06f69b39e54c949542fa85fd49ff51278 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 22 Jun 2023 14:01:42 +0200 Subject: arm64: dts: qcom: sa8775p-ride: enable ethernet0 Enable the first 1Gb ethernet port on sa8775p-ride development board. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Tested-by: Andrew Halaney Link: https://lore.kernel.org/r/20230622120142.218055-6-brgl@bgdev.pl Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 88 +++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index bf90f825ff67..b2aa16037707 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -261,6 +261,94 @@ }; }; +ðernet0 { + phy-mode = "sgmii"; + phy-handle = <&sgmii_phy>; + + pinctrl-0 = <ðernet0_default>; + pinctrl-names = "default"; + + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,ps-speed = <1000>; + + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>; + reset-delay-us = <11000>; + reset-post-delay-us = <70000>; + + sgmii_phy: phy@8 { + reg = <0x8>; + device_type = "ethernet-phy"; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xc>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <4>; + snps,tx-sched-sp; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + }; +}; + &i2c11 { clock-frequency = <400000>; pinctrl-0 = <&qup_i2c11_default>; -- cgit v1.2.3-59-g8ed1b From 0a69ccf20b0837db857abfc94d7e3bacf1cb771b Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 22 Jun 2023 17:56:16 +0200 Subject: arm64: dts: qcom: sc8280xp: Add missing SCM interconnect The SCM interconnect path was missing. Add it. Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by: Konrad Dybcio Reviewed-by: Johan Hovold Tested-by: Johan Hovold Link: https://lore.kernel.org/r/20230622-topic-8280scmicc-v1-2-6ef318919ea5@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index ac0596dfdbc4..0756b7c141ff 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -298,6 +298,7 @@ firmware { scm: scm { compatible = "qcom,scm-sc8280xp", "qcom,scm"; + interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; }; }; -- cgit v1.2.3-59-g8ed1b From 6d5872f2ccbe4ebd6aa926e3699a760356009dbb Mon Sep 17 00:00:00 2001 From: Sridharan S N Date: Fri, 23 Jun 2023 14:30:01 +0530 Subject: arm64: dts: qcom: ipq5332: Add common RDP dtsi file Add a dtsi file to include interfaces that are common across IPQ5332 RDPs. Signed-off-by: Sridharan S N Link: https://lore.kernel.org/r/20230623090001.27778-1-quic_sridsn@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi | 36 ++++++++++++++++++ arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | 26 +------------ arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts | 26 +------------ arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts | 24 +----------- arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts | 47 +----------------------- 5 files changed, 40 insertions(+), 119 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi new file mode 100644 index 000000000000..f13dea7d67fe --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * IPQ5332 RDP board common device tree source + * + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include +#include +#include "ipq5332.dtsi" + +/ { + aliases { + serial0 = &blsp1_uart0; + }; + + chosen { + stdout-path = "serial0"; + }; +}; + +&blsp1_uart0 { + pinctrl-0 = <&serial_0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&xo_board { + clock-frequency = <24000000>; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts index 3af1d5556950..e89e2e948603 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts @@ -7,25 +7,11 @@ /dts-v1/; -#include "ipq5332.dtsi" +#include "ipq5332-rdp-common.dtsi" / { model = "Qualcomm Technologies, Inc. IPQ5332 MI01.2"; compatible = "qcom,ipq5332-ap-mi01.2", "qcom,ipq5332"; - - aliases { - serial0 = &blsp1_uart0; - }; - - chosen { - stdout-path = "serial0"; - }; -}; - -&blsp1_uart0 { - pinctrl-0 = <&serial_0_pins>; - pinctrl-names = "default"; - status = "okay"; }; &blsp1_i2c1 { @@ -46,16 +32,6 @@ status = "okay"; }; -&sleep_clk { - clock-frequency = <32000>; -}; - -&xo_board { - clock-frequency = <24000000>; -}; - -/* PINCTRL */ - &tlmm { i2c_1_pins: i2c-1-state { pins = "gpio29", "gpio30"; diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts index bcf3b31c20e3..efd480a7afdf 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts @@ -7,25 +7,11 @@ /dts-v1/; -#include "ipq5332.dtsi" +#include "ipq5332-rdp-common.dtsi" / { model = "Qualcomm Technologies, Inc. IPQ5332 MI01.3"; compatible = "qcom,ipq5332-ap-mi01.3", "qcom,ipq5332"; - - aliases { - serial0 = &blsp1_uart0; - }; - - chosen { - stdout-path = "serial0"; - }; -}; - -&blsp1_uart0 { - pinctrl-0 = <&serial_0_pins>; - pinctrl-names = "default"; - status = "okay"; }; &blsp1_i2c1 { @@ -60,16 +46,6 @@ status = "okay"; }; -&sleep_clk { - clock-frequency = <32000>; -}; - -&xo_board { - clock-frequency = <24000000>; -}; - -/* PINCTRL */ - &tlmm { i2c_1_pins: i2c-1-state { pins = "gpio29", "gpio30"; diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts index 3b6a5cb8bf07..f96b0c8c908b 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts @@ -7,25 +7,11 @@ /dts-v1/; -#include "ipq5332.dtsi" +#include "ipq5332-rdp-common.dtsi" / { model = "Qualcomm Technologies, Inc. IPQ5332 MI01.6"; compatible = "qcom,ipq5332-ap-mi01.6", "qcom,ipq5332"; - - aliases { - serial0 = &blsp1_uart0; - }; - - chosen { - stdout-path = "serial0"; - }; -}; - -&blsp1_uart0 { - pinctrl-0 = <&serial_0_pins>; - pinctrl-names = "default"; - status = "okay"; }; &blsp1_spi0 { @@ -53,14 +39,6 @@ status = "okay"; }; -&sleep_clk { - clock-frequency = <32000>; -}; - -&xo_board { - clock-frequency = <24000000>; -}; - /* PINCTRL */ &tlmm { diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts index 53c68d8c5e5d..eb1fa33d6fe4 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts @@ -7,41 +7,11 @@ /dts-v1/; -#include -#include -#include "ipq5332.dtsi" +#include "ipq5332-rdp-common.dtsi" / { model = "Qualcomm Technologies, Inc. IPQ5332 MI01.9"; compatible = "qcom,ipq5332-ap-mi01.9", "qcom,ipq5332"; - - aliases { - serial0 = &blsp1_uart0; - }; - - chosen { - stdout-path = "serial0"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&gpio_keys_default_state>; - pinctrl-names = "default"; - - button-wps { - label = "wps"; - linux,code = ; - gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - debounce-interval = <60>; - }; - }; -}; - -&blsp1_uart0 { - pinctrl-0 = <&serial_0_pins>; - pinctrl-names = "default"; - status = "okay"; }; &blsp1_i2c1 { @@ -62,24 +32,9 @@ status = "okay"; }; -&sleep_clk { - clock-frequency = <32000>; -}; - -&xo_board { - clock-frequency = <24000000>; -}; - /* PINCTRL */ &tlmm { - gpio_keys_default_state: gpio-keys-default-state { - pins = "gpio35"; - function = "gpio"; - drive-strength = <8>; - bias-pull-up; - }; - i2c_1_pins: i2c-1-state { pins = "gpio29", "gpio30"; function = "blsp1_i2c0"; -- cgit v1.2.3-59-g8ed1b From 519c47acac28db7cec7ab5d929055a73001ac2d9 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Sun, 25 Jun 2023 13:13:05 +0200 Subject: arm64: dts: qcom: pm8953: Add thermal zone Define the themal zones using the temperature values found in the downstream 4.9 sources so that the spmi-temp-alarm driver becomes active. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230625-pm8953-thermal-v1-1-2b4247d2f769@z3ntu.xyz Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm8953.dtsi | 33 ++++++++++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pm8953.dtsi b/arch/arm64/boot/dts/qcom/pm8953.dtsi index 2268daf27fa7..d2dfc1699174 100644 --- a/arch/arm64/boot/dts/qcom/pm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8953.dtsi @@ -6,6 +6,37 @@ #include #include +/ { + thermal-zones { + pm8953-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&pm8953_temp>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + &spmi_bus { pmic@0 { compatible = "qcom,pm8953", "qcom,spmi-pmic"; @@ -36,7 +67,7 @@ }; }; - temp-alarm@2400 { + pm8953_temp: temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; reg = <0x2400>; interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; -- cgit v1.2.3-59-g8ed1b From 9eba4db02a88e7a810aabd70f7a6960f184f391f Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 26 Jun 2023 19:48:07 +0200 Subject: dt-bindings: clock: qcom,gcc-sc8280xp: Add missing GDSCs There are 10 more GDSCs that we've not been caring about, and by extension (and perhaps even more importantly), not putting to sleep. Add them. Fixes: a66a82f2a55e ("dt-bindings: clock: Add Qualcomm SC8280XP GCC bindings") Acked-by: Rob Herring Signed-off-by: Konrad Dybcio Acked-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20230620-topic-sc8280_gccgdsc-v2-2-562c1428c10d@linaro.org Signed-off-by: Bjorn Andersson --- include/dt-bindings/clock/qcom,gcc-sc8280xp.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/dt-bindings/clock/qcom,gcc-sc8280xp.h b/include/dt-bindings/clock/qcom,gcc-sc8280xp.h index 721105ea4fad..845491591784 100644 --- a/include/dt-bindings/clock/qcom,gcc-sc8280xp.h +++ b/include/dt-bindings/clock/qcom,gcc-sc8280xp.h @@ -494,5 +494,15 @@ #define USB30_SEC_GDSC 11 #define EMAC_0_GDSC 12 #define EMAC_1_GDSC 13 +#define USB4_1_GDSC 14 +#define USB4_GDSC 15 +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 16 +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 17 +#define HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC 18 +#define HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC 19 +#define HLOS1_VOTE_TURING_MMU_TBU0_GDSC 20 +#define HLOS1_VOTE_TURING_MMU_TBU1_GDSC 21 +#define HLOS1_VOTE_TURING_MMU_TBU2_GDSC 22 +#define HLOS1_VOTE_TURING_MMU_TBU3_GDSC 23 #endif -- cgit v1.2.3-59-g8ed1b From 55179c92c7346ab20991975195c3dc0ba7b74c50 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 26 Jun 2023 16:09:57 -0600 Subject: arm64: dts: qcom: Fix "status" value The defined value for "status" is "disabled", not "disable". Signed-off-by: Rob Herring Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230626220957.3945972-1-robh@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index cfbc4fc1eba9..c6914db7dc6d 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -779,5 +779,5 @@ &crypto { /* FIXME: qce_start triggers an SError */ - status = "disable"; + status = "disabled"; }; -- cgit v1.2.3-59-g8ed1b From 86b0aef435851dec9e5202d22dfbfff56da4440c Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Tue, 27 Jun 2023 10:28:05 +0200 Subject: arm64: dts: qcom: sm8450: Use standalone ICE node for UFS With the ICE driver now merged let's convert the ufs node to use the new style. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20221209-dt-binding-ufs-v5-5-c9a58c0a53f5@fairphone.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 1c71c0a2cd81..b97998c684b0 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -4120,9 +4120,7 @@ ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sm8450-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x3000>, - <0 0x01d88000 0 0x8000>; - reg-names = "std", "ice"; + reg = <0 0x01d84000 0 0x3000>; interrupts = ; phys = <&ufs_mem_phy_lanes>; phy-names = "ufsphy"; @@ -4147,8 +4145,7 @@ "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk", - "rx_lane1_sync_clk", - "ice_core_clk"; + "rx_lane1_sync_clk"; clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, @@ -4157,8 +4154,7 @@ <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, - <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; freq-table-hz = <75000000 300000000>, <0 0>, @@ -4167,8 +4163,9 @@ <75000000 300000000>, <0 0>, <0 0>, - <0 0>, - <75000000 300000000>; + <0 0>; + qcom,ice = <&ice>; + status = "disabled"; }; @@ -4198,6 +4195,13 @@ }; }; + ice: crypto@1d88000 { + compatible = "qcom,sm8450-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0 0x01d88000 0 0x8000>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + cryptobam: dma-controller@1dc4000 { compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; reg = <0 0x01dc4000 0 0x28000>; -- cgit v1.2.3-59-g8ed1b From 55c9b1bf29dad107b3871bbb250c00df80a68791 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 27 Jun 2023 10:53:06 +0200 Subject: arm64: dts: qcom: sc8280xp-pmics: add explicit rtc interrupt parent Unless explicitly specified the interrupt-parent property is inherited from the parent node on Linux even though this may not be in full compliance with the devicetree specification. Following commit 2d5cab9232ba ("arm64: dts: qcom: sc8280xp-pmics: Specify interrupt parent explicitly"), add an explicit interrupt parent also for the PMIC RTC node for the benefit of other operating systems which may be confused by this omission. Note that any such OS must still implement a fallback to the root interrupt domain as most devicetrees are written under the assumption that the interrupt parent is inherited. Reported-by: Patrick Wildt Signed-off-by: Johan Hovold Acked-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230627085306.6033-1-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi index a0ba535bb6c9..80ee12ded4f4 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi @@ -101,7 +101,7 @@ compatible = "qcom,pmk8350-rtc"; reg = <0x6100>, <0x6200>; reg-names = "rtc", "alarm"; - interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; + interrupts-extended = <&spmi_bus 0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; wakeup-source; status = "disabled"; }; -- cgit v1.2.3-59-g8ed1b From fdc3cf9fc3b266af2b23c82c616b6b87d37c97e0 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 27 Jun 2023 16:07:37 +0200 Subject: arm64: dts: qcom: sm6375: Set up L3 scaling Add the CPU OPP tables including core frequency and L3 bus frequency. The L3 throughput values were chosen by studying the frequencies available in HW LUT and picking the highest one that's less than the CPU frequency. They will be replaced with a dynamic, bwmon-style decision maker once support for MEMLAT is introduced upstream. Available values from the HW LUT: 300000 556800 652800 768000 844800 921600 1171200 1382400 1497600 This commit dramatically improves overall performance of the system. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230627-topic-6375_l3-v1-1-9cb03ef05150@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 127 +++++++++++++++++++++++++++++++++++ 1 file changed, 127 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 3dba34210a6d..927aa59d4a07 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -45,6 +46,8 @@ enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -69,6 +72,8 @@ enable-method = "psci"; next-level-cache = <&L2_100>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; power-domains = <&CPU_PD1>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -88,6 +93,8 @@ enable-method = "psci"; next-level-cache = <&L2_200>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; power-domains = <&CPU_PD2>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -107,6 +114,8 @@ enable-method = "psci"; next-level-cache = <&L2_300>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; power-domains = <&CPU_PD3>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -126,6 +135,8 @@ enable-method = "psci"; next-level-cache = <&L2_400>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; power-domains = <&CPU_PD4>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -145,6 +156,8 @@ enable-method = "psci"; next-level-cache = <&L2_500>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; power-domains = <&CPU_PD5>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -164,6 +177,8 @@ enable-method = "psci"; next-level-cache = <&L2_600>; qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu6_opp_table>; + interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; power-domains = <&CPU_PD6>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -183,6 +198,8 @@ enable-method = "psci"; next-level-cache = <&L2_700>; qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu6_opp_table>; + interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; power-domains = <&CPU_PD7>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -300,6 +317,116 @@ reg = <0x0 0x80000000 0x0 0x0>; }; + cpu0_opp_table: opp-table-cpu0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-peak-kBps = <(300000 * 32)>; + }; + + opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + opp-peak-kBps = <(556800 * 32)>; + }; + + opp-691200000 { + opp-hz = /bits/ 64 <691200000>; + opp-peak-kBps = <(652800 * 32)>; + }; + + opp-940800000 { + opp-hz = /bits/ 64 <940800000>; + opp-peak-kBps = <(921600 * 32)>; + }; + + opp-1113600000 { + opp-hz = /bits/ 64 <1113600000>; + opp-peak-kBps = <(921600 * 32)>; + }; + + opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + opp-peak-kBps = <(1171200 * 32)>; + }; + + opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + opp-peak-kBps = <(1497600 * 32)>; + }; + + opp-1651200000 { + opp-hz = /bits/ 64 <1651200000>; + opp-peak-kBps = <(1497600 * 32)>; + }; + + opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <(1497600 * 32)>; + }; + + opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + opp-peak-kBps = <(1497600 * 32)>; + }; + }; + + cpu6_opp_table: opp-table-cpu6 { + compatible = "operating-points-v2"; + opp-shared; + + opp-691200000 { + opp-hz = /bits/ 64 <691200000>; + opp-peak-kBps = <(556800 * 32)>; + }; + + opp-940800000 { + opp-hz = /bits/ 64 <940800000>; + opp-peak-kBps = <(921600 * 32)>; + }; + + opp-1228800000 { + opp-hz = /bits/ 64 <1228800000>; + opp-peak-kBps = <(1171200 * 32)>; + }; + + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + opp-peak-kBps = <(1382400 * 32)>; + }; + + opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + opp-peak-kBps = <(1497600 * 32)>; + }; + + opp-1651200000 { + opp-hz = /bits/ 64 <1651200000>; + opp-peak-kBps = <(1497600 * 32)>; + }; + + opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + opp-peak-kBps = <(1497600 * 32)>; + }; + + opp-1900800000 { + opp-hz = /bits/ 64 <1900800000>; + opp-peak-kBps = <(1497600 * 32)>; + }; + + opp-2054400000 { + opp-hz = /bits/ 64 <2054400000>; + opp-peak-kBps = <(1497600 * 32)>; + }; + + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-peak-kBps = <(1497600 * 32)>; + }; + }; + pmu { compatible = "arm,armv8-pmuv3"; interrupts = ; -- cgit v1.2.3-59-g8ed1b From afc19e3716c3bc32c31baac54e3a9057661979ad Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 27 Jun 2023 18:24:17 +0200 Subject: arm64: dts: qcom: sc7180: Fix DSI0_PHY reg-names Commit 2b616f86d51b ("arm64: dts: qcom: sc7180: rename labels for DSI nodes") broke reg-names, possibly with search-and-replace. Fix it. Fixes: 2b616f86d51b ("arm64: dts: qcom: sc7180: rename labels for DSI nodes") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230627-topic-more_bindings-v1-1-6b4b6cd081e5@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 31381e78edd7..179544ba12db 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -3197,8 +3197,8 @@ reg = <0 0x0ae94400 0 0x200>, <0 0x0ae94600 0 0x280>, <0 0x0ae94a00 0 0x1e0>; - reg-names = "dsi0_phy", - "dsi0_phy_lane", + reg-names = "dsi_phy", + "dsi_phy_lane", "dsi_pll"; #clock-cells = <1>; -- cgit v1.2.3-59-g8ed1b From 982f810fc196002808b6d4230ba8f431c993d264 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 27 Jun 2023 18:24:18 +0200 Subject: arm64: dts: qcom: msm8939: Drop "qcom,idle-state-spc" compatible As of today, the only cool and legal way to get ARM64 SMP going is via PSCI (or spin tables). Sadly, not all chip and device vendors were considerate of this in the early days of arm64. Qualcomm, for example reused their tried-and-true spin-up method from MSM8974 and their Krait/ arm32 Cortex designs. MSM8916 supports SMP with its arm32 dt overlay, as probably could 8939. But the arm64 DT should not define non-PSCI SMP or CPUidle stuff. Drop the qcom,idle-state-spc compatible (associated with Qualcomm-specific CPUIdle) to make the dt checker happy: apq8039-t2.dtb: idle-states: cpu-sleep-0:compatible: ['qcom,idle-state-spc', 'arm,idle-state'] is too long Fixes: 61550c6c156c ("arm64: dts: qcom: Add msm8939 SoC") Signed-off-by: Konrad Dybcio Reviewed-by: Benjamin Li Link: https://lore.kernel.org/r/20230627-topic-more_bindings-v1-2-6b4b6cd081e5@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8939.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi index 05d8abbbc840..38fc22e66bda 100644 --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -155,7 +155,7 @@ idle-states { CPU_SLEEP_0: cpu-sleep-0 { - compatible ="qcom,idle-state-spc", "arm,idle-state"; + compatible = "arm,idle-state"; entry-latency-us = <130>; exit-latency-us = <150>; min-residency-us = <2000>; -- cgit v1.2.3-59-g8ed1b From 68a59251f1c590ad567ff7fd799f6634fbab6e16 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 27 Jun 2023 18:24:19 +0200 Subject: arm64: dts: qcom: msm8939: Add missing 'cache-unified' to L2 Add the missing property to fix the dt checker warning: qcom/apq8039-t2.dtb: l2-cache: 'cache-unified' is a required property Fixes: 61550c6c156c ("arm64: dts: qcom: Add msm8939 SoC") Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Reviewed-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20230627-topic-more_bindings-v1-3-6b4b6cd081e5@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8939.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi index 38fc22e66bda..664ae303afae 100644 --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -55,6 +55,7 @@ L2_1: l2-cache { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; @@ -111,6 +112,7 @@ L2_0: l2-cache { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; -- cgit v1.2.3-59-g8ed1b From 9cc6dee9b3a8aea0af836d365793ffce47bc7a11 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 27 Jun 2023 18:24:20 +0200 Subject: arm64: dts: qcom: apq8039-t2: Drop inexistent property 'pin-switch-delay-us' is not used anywhere in the mainline kernel. Drop it. Signed-off-by: Konrad Dybcio Reviewed-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20230627-topic-more_bindings-v1-4-6b4b6cd081e5@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8039-t2.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/apq8039-t2.dts b/arch/arm64/boot/dts/qcom/apq8039-t2.dts index 43686bbd87f4..027d1da7e81d 100644 --- a/arch/arm64/boot/dts/qcom/apq8039-t2.dts +++ b/arch/arm64/boot/dts/qcom/apq8039-t2.dts @@ -374,7 +374,6 @@ pinctrl-0 = <&pinctrl_otg_default>; pinctrl-1 = <&pinctrl_otg_host>; pinctrl-2 = <&pinctrl_otg_device>; - pin-switch-delay-us = <100000>; usb-role-switch; status = "okay"; -- cgit v1.2.3-59-g8ed1b From 36541089c4733355ed844c67eebd0c3936953454 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 27 Jun 2023 18:24:27 +0200 Subject: arm64: dts: qcom: msm8996: Add missing interrupt to the USB2 controller The interrupt line was previously not described. Take care of that. Fixes: 1e39255ed29d ("arm64: dts: msm8996: Add device node for qcom,dwc3") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230627-topic-more_bindings-v1-11-6b4b6cd081e5@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 40ac0a784a4a..4eca552f359c 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -3336,6 +3336,9 @@ #size-cells = <1>; ranges; + interrupts = ; + interrupt-names = "hs_phy_irq"; + clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, <&gcc GCC_USB20_MASTER_CLK>, <&gcc GCC_USB20_MOCK_UTMI_CLK>, -- cgit v1.2.3-59-g8ed1b From 9acc60c3e2d449243e4c2126e3b56f1c4f7fd3bc Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 27 Jun 2023 19:27:50 +0200 Subject: arm64: dts: qcom: sdm845-tama: Set serial indices and stdout-path UART6 is used for debug (routed via uSD pins) and UART9 is connected to the bluetooth chip. Set indexed aliases to make the GENI UART driver happy and route serial traffic through the debug uart by default. Fixes: 30a7f99befc6 ("arm64: dts: qcom: Add support for SONY Xperia XZ2 / XZ2C / XZ3 (Tama platform)") Signed-off-by: Konrad Dybcio Reviewed-by: Marijn Suijten Link: https://lore.kernel.org/r/20230627-topic-tama_uart-v1-1-0fa790248db8@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi index 3bc187a066ae..7ee61b20452e 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi @@ -15,6 +15,15 @@ qcom,msm-id = <321 0x20001>; /* SDM845 v2.1 */ qcom,board-id = <8 0>; + aliases { + serial0 = &uart6; + serial1 = &uart9; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + gpio-keys { compatible = "gpio-keys"; -- cgit v1.2.3-59-g8ed1b From ddf66e4b16744b96db4bd1ddee9d19b5a834f94f Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 27 Jun 2023 19:28:52 +0200 Subject: arm64: dts: qcom: msm8998: Provide XO to RPMCC The RPMCC node should be fed a reference to the XO fixed clock. Do so. Signed-off-by: Konrad Dybcio Reviewed-by: Jeffrey Hugo Link: https://lore.kernel.org/r/20230627-topic-98_rpmcc-v1-1-4024e43ad0fc@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index f0e943ff0046..171f2e21d80a 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -334,6 +334,8 @@ rpmcc: clock-controller { compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc"; + clocks = <&xo>; + clock-names = "xo"; #clock-cells = <1>; }; -- cgit v1.2.3-59-g8ed1b From 934a3b4d5a2d4c265ca22d3cf471a72ec8d9ee65 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 2 Jul 2023 20:50:50 +0200 Subject: arm64: dts: qcom: minor whitespace cleanup around '=' The DTS code coding style expects exactly one space before and after '=' sign. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230702185051.43867-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 +- .../boot/dts/qcom/msm8916-samsung-serranove.dts | 6 +- arch/arm64/boot/dts/qcom/msm8939.dtsi | 12 +- arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts | 2 +- arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts | 2 +- arch/arm64/boot/dts/qcom/msm8996.dtsi | 6 +- .../boot/dts/qcom/msm8996pro-xiaomi-natrium.dts | 2 +- arch/arm64/boot/dts/qcom/msm8998.dtsi | 18 +- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 2 +- arch/arm64/boot/dts/qcom/qcs404.dtsi | 8 +- arch/arm64/boot/dts/qcom/sa8540p.dtsi | 2 +- .../qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi | 2 +- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdm630.dtsi | 10 +- .../boot/dts/qcom/sdm845-oneplus-enchilada.dts | 2 +- arch/arm64/boot/dts/qcom/sdx75.dtsi | 4 +- arch/arm64/boot/dts/qcom/sm6115.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8250.dtsi | 198 ++++++++++----------- arch/arm64/boot/dts/qcom/sm8350.dtsi | 196 ++++++++++---------- arch/arm64/boot/dts/qcom/sm8450.dtsi | 194 ++++++++++---------- arch/arm64/boot/dts/qcom/sm8550.dtsi | 196 ++++++++++---------- 22 files changed, 438 insertions(+), 438 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 68839acbd613..00ed71936b47 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -794,10 +794,10 @@ pcie1: pci@10000000 { compatible = "qcom,pcie-ipq8074"; - reg = <0x10000000 0xf1d>, - <0x10000f20 0xa8>, - <0x00088000 0x2000>, - <0x10100000 0x1000>; + reg = <0x10000000 0xf1d>, + <0x10000f20 0xa8>, + <0x00088000 0x2000>, + <0x10100000 0x1000>; reg-names = "dbi", "elbi", "parf", "config"; device_type = "pci"; linux,pci-domain = <1>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts index cbda25f2ad19..eaf877378937 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts @@ -234,9 +234,9 @@ compatible = "yamaha,yas537"; reg = <0x2e>; - mount-matrix = "0", "1", "0", - "1", "0", "0", - "0", "0", "-1"; + mount-matrix = "0", "1", "0", + "1", "0", "0", + "0", "0", "-1"; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi index 664ae303afae..b5936ae00bbd 100644 --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -1644,7 +1644,7 @@ clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; - clock-names = "iface", "core", "xo"; + clock-names = "iface", "core", "xo"; resets = <&gcc GCC_SDCC2_BCR>; pinctrl-0 = <&sdc2_default>; pinctrl-1 = <&sdc2_sleep>; @@ -1731,7 +1731,7 @@ interrupts = ; clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; + clock-names = "core", "iface"; dmas = <&blsp_dma 6>, <&blsp_dma 7>; dma-names = "tx", "rx"; pinctrl-0 = <&blsp_i2c2_default>; @@ -1765,7 +1765,7 @@ interrupts = ; clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; + clock-names = "core", "iface"; dmas = <&blsp_dma 8>, <&blsp_dma 9>; dma-names = "tx", "rx"; pinctrl-0 = <&blsp_i2c3_default>; @@ -1799,7 +1799,7 @@ interrupts = ; clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; + clock-names = "core", "iface"; dmas = <&blsp_dma 10>, <&blsp_dma 11>; dma-names = "tx", "rx"; pinctrl-0 = <&blsp_i2c4_default>; @@ -1833,7 +1833,7 @@ interrupts = ; clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; + clock-names = "core", "iface"; dmas = <&blsp_dma 12>, <&blsp_dma 13>; dma-names = "tx", "rx"; pinctrl-0 = <&blsp_i2c5_default>; @@ -1867,7 +1867,7 @@ interrupts = ; clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; + clock-names = "core", "iface"; dmas = <&blsp_dma 14>, <&blsp_dma 15>; dma-names = "tx", "rx"; pinctrl-0 = <&blsp_i2c6_default>; diff --git a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts index 1d672e608653..790d19c99af1 100644 --- a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts +++ b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts @@ -17,7 +17,7 @@ compatible = "xiaomi,daisy", "qcom,msm8953"; chassis-type = "handset"; qcom,msm-id = <293 0>; - qcom,board-id= <0x1000b 0x9>; + qcom,board-id = <0x1000b 0x9>; chosen { #address-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts index b5be55034fd3..0956c866d6cb 100644 --- a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts +++ b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts @@ -20,7 +20,7 @@ compatible = "xiaomi,vince", "qcom,msm8953"; chassis-type = "handset"; qcom,msm-id = <293 0>; - qcom,board-id= <0x1000b 0x08>; + qcom,board-id = <0x1000b 0x08>; gpio-keys { compatible = "gpio-keys"; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 4eca552f359c..de20e62284cc 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1138,9 +1138,9 @@ mdss_hdmi: hdmi-tx@9a0000 { compatible = "qcom,hdmi-tx-8996"; - reg = <0x009a0000 0x50c>, - <0x00070000 0x6158>, - <0x009e0000 0xfff>; + reg = <0x009a0000 0x50c>, + <0x00070000 0x6158>, + <0x009e0000 0xfff>; reg-names = "core_physical", "qfprom_physical", "hdcp_physical"; diff --git a/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts b/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts index 7957c8823f0d..5e3fd1637f44 100644 --- a/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts +++ b/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts @@ -106,7 +106,7 @@ &sound { compatible = "qcom,apq8096-sndcard"; model = "natrium"; - audio-routing = "RX_BIAS", "MCLK"; + audio-routing = "RX_BIAS", "MCLK"; mm1-dai-link { link-name = "MultiMedia1"; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 171f2e21d80a..78867cb00875 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -911,10 +911,10 @@ pcie0: pci@1c00000 { compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996"; - reg = <0x01c00000 0x2000>, - <0x1b000000 0xf1d>, - <0x1b000f20 0xa8>, - <0x1b100000 0x100000>; + reg = <0x01c00000 0x2000>, + <0x1b000000 0xf1d>, + <0x1b000f20 0xa8>, + <0x1b100000 0x100000>; reg-names = "parf", "dbi", "elbi", "config"; device_type = "pci"; linux,pci-domain = <0>; @@ -2076,11 +2076,11 @@ spmi_bus: spmi@800f000 { compatible = "qcom,spmi-pmic-arb"; - reg = <0x0800f000 0x1000>, - <0x08400000 0x1000000>, - <0x09400000 0x1000000>, - <0x0a400000 0x220000>, - <0x0800a000 0x3000>; + reg = <0x0800f000 0x1000>, + <0x08400000 0x1000000>, + <0x09400000 0x1000000>, + <0x0a400000 0x220000>, + <0x0800a000 0x3000>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; interrupts = ; diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index 53341dfb4204..cf995eefa11e 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -816,7 +816,7 @@ , , ; - dma-channels = <10>; + dma-channels = <10>; dma-channel-mask = <0x1f>; iommus = <&apps_smmu 0xf6 0x0>; #dma-cells = <3>; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 972f753847e1..f2568aff14c8 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -1459,10 +1459,10 @@ pcie: pci@10000000 { compatible = "qcom,pcie-qcs404"; - reg = <0x10000000 0xf1d>, - <0x10000f20 0xa8>, - <0x07780000 0x2000>, - <0x10001000 0x2000>; + reg = <0x10000000 0xf1d>, + <0x10000f20 0xa8>, + <0x07780000 0x2000>, + <0x10001000 0x2000>; reg-names = "dbi", "elbi", "parf", "config"; device_type = "pci"; linux,pci-domain = <0>; diff --git a/arch/arm64/boot/dts/qcom/sa8540p.dtsi b/arch/arm64/boot/dts/qcom/sa8540p.dtsi index bacbdec56281..96b2c59ad02b 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8540p.dtsi @@ -207,7 +207,7 @@ linux,pci-domain = <2>; - interrupts = ; + interrupts = ; interrupt-names = "msi"; interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi index 485f9942e128..a90c70b1b73e 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi @@ -13,7 +13,7 @@ compatible = "google,sc7280-herobrine"; model = "sc7280-rt5682-max98360a-3mic"; - audio-routing = "VA DMIC0", "vdd-micb", + audio-routing = "VA DMIC0", "vdd-micb", "VA DMIC1", "vdd-micb", "VA DMIC2", "vdd-micb", "VA DMIC3", "vdd-micb", diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index a0e8db8270e7..925428a5f6ae 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2449,7 +2449,7 @@ <&apps_smmu 0x1821 0>, <&apps_smmu 0x1832 0>; - power-domains = <&rpmhpd SC7280_LCX>; + power-domains = <&rpmhpd SC7280_LCX>; power-domain-names = "lcx"; required-opps = <&rpmhpd_opp_nom>; diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 576180451491..94cb59d2761c 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -2252,7 +2252,7 @@ }; gmu: gmu@2c6a000 { - compatible="qcom,adreno-gmu-680.1", "qcom,adreno-gmu"; + compatible = "qcom,adreno-gmu-680.1", "qcom,adreno-gmu"; reg = <0 0x02c6a000 0 0x30000>, <0 0x0b290000 0 0x10000>, diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index bba0f366ef03..759b3a5964cc 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1196,11 +1196,11 @@ spmi_bus: spmi@800f000 { compatible = "qcom,spmi-pmic-arb"; - reg = <0x0800f000 0x1000>, - <0x08400000 0x1000000>, - <0x09400000 0x1000000>, - <0x0a400000 0x220000>, - <0x0800a000 0x3000>; + reg = <0x0800f000 0x1000>, + <0x08400000 0x1000000>, + <0x09400000 0x1000000>, + <0x0a400000 0x220000>, + <0x0800a000 0x3000>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; interrupts = ; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts index 623a826b18a3..62fe72ff3763 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts @@ -57,7 +57,7 @@ &sound { model = "OnePlus 6"; - audio-routing = "RX_BIAS", "MCLK", + audio-routing = "RX_BIAS", "MCLK", "AMIC2", "MIC BIAS2", "AMIC3", "MIC BIAS4", "AMIC4", "MIC BIAS1", diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index 21d5d55da5eb..7d39a615f4f7 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -484,14 +484,14 @@ tx-pins { pins = "gpio12"; function = "qup_se1_l2_mira"; - drive-strength= <2>; + drive-strength = <2>; bias-disable; }; rx-pins { pins = "gpio13"; function = "qup_se1_l3_mira"; - drive-strength= <2>; + drive-strength = <2>; bias-disable; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 424b4f3c909b..9f2c968e3ad7 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -1057,7 +1057,7 @@ , , ; - dma-channels = <10>; + dma-channels = <10>; dma-channel-mask = <0xf>; iommus = <&apps_smmu 0xf6 0x0>; #dma-cells = <3>; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index dd817ec200f1..4c61f47ee9bd 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3059,7 +3059,7 @@ port@7 { reg = <7>; funnel_swao_in_funnel_merg: endpoint { - remote-endpoint= <&funnel_merg_out_funnel_swao>; + remote-endpoint = <&funnel_merg_out_funnel_swao>; }; }; }; @@ -5298,104 +5298,104 @@ reg = <0 0x15000000 0 0x100000>; #iommu-cells = <2>; #global-interrupts = <2>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; adsp: remoteproc@17300000 { diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 88ef478cb5cc..48d97e61162f 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -3073,104 +3073,104 @@ reg = <0 0x15000000 0 0x100000>; #iommu-cells = <2>; #global-interrupts = <2>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; adsp: remoteproc@17300000 { diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index b97998c684b0..1668d97ce459 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3810,103 +3810,103 @@ reg = <0 0x15000000 0 0x100000>; #iommu-cells = <2>; #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; intc: interrupt-controller@17100000 { diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 41d60af93692..6e8aba256931 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1600,7 +1600,7 @@ pinctrl-0 = <&qup_uart7_default>; interrupts = ; interconnect-names = "qup-core", "qup-config"; - interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; status = "disabled"; }; @@ -3517,103 +3517,103 @@ reg = <0 0x15000000 0 0x100000>; #iommu-cells = <2>; #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; intc: interrupt-controller@17100000 { -- cgit v1.2.3-59-g8ed1b From 5a89585fc880a56bdeed6132d0568d99a29e4231 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Wed, 5 Jul 2023 14:47:29 +0530 Subject: arm64: dts: qcom: qdu1000-idp: Add reserved gpio list Add reserve gpios for QDU1000 IDP platform. These gpios are needed for modem subsystem. Signed-off-by: Komal Bajaj Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230705091730.32087-2-quic_kbajaj@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts index 1d22f87fd238..0496e87ddfd5 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts +++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts @@ -471,6 +471,10 @@ status = "okay"; }; +&tlmm { + gpio-reserved-ranges = <28 2>; +}; + &uart7 { status = "okay"; }; -- cgit v1.2.3-59-g8ed1b From 301f7ca3574c05c3ae62d6d5ac1fa0c48cd4b080 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Wed, 5 Jul 2023 14:47:30 +0530 Subject: arm64: dts: qcom: qru1000-idp: Add reserved gpio list Add reserve gpios for QRU1000 IDP platform. These gpios are needed for modem subsystem. Signed-off-by: Komal Bajaj Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230705091730.32087-3-quic_kbajaj@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qru1000-idp.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qru1000-idp.dts b/arch/arm64/boot/dts/qcom/qru1000-idp.dts index 2cc893ae4d10..80dadd2f30a3 100644 --- a/arch/arm64/boot/dts/qcom/qru1000-idp.dts +++ b/arch/arm64/boot/dts/qcom/qru1000-idp.dts @@ -448,6 +448,10 @@ status = "okay"; }; +&tlmm { + gpio-reserved-ranges = <28 2>; +}; + &uart7 { status = "okay"; }; -- cgit v1.2.3-59-g8ed1b From 29a687c219e20fd4c6e8c47d214365f0d34e3d3d Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 5 Jul 2023 15:36:21 +0200 Subject: arm64: dts: qcom: sm8350: Add missing cluster sleep state SM8350's cores can be shut off, without engaging full-on SoC-wide power collapse. Add the missing idle state to allow for that. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230705-topic-sm8350_fixes-v1-1-0f69f70ccb6a@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 48d97e61162f..e3c930a8123b 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -264,7 +264,15 @@ }; domain-idle-states { - CLUSTER_SLEEP_0: cluster-sleep-0 { + CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <2752>; + exit-latency-us = <3048>; + min-residency-us = <6118>; + }; + + CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 { compatible = "domain-idle-state"; arm,psci-suspend-param = <0x4100c344>; entry-latency-us = <3263>; @@ -346,7 +354,7 @@ CLUSTER_PD: power-domain-cpu-cluster0 { #power-domain-cells = <0>; - domain-idle-states = <&CLUSTER_SLEEP_0>; + domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_AOSS_SLEEP>; }; }; -- cgit v1.2.3-59-g8ed1b From 91ce3693e2fb685f31d39605a5ad1fbd940804da Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 5 Jul 2023 15:36:22 +0200 Subject: arm64: dts: qcom: sm8350: Fix CPU idle state residency times The present values look to have been copypasted from 8150 or 8180. Fix that. Fixes: 07ddb302811e ("arm64: dts: qcom: sm8350: Add CPU topology and idle-states") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230705-topic-sm8350_fixes-v1-2-0f69f70ccb6a@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index e3c930a8123b..d5dcfc0deae5 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -246,8 +246,8 @@ compatible = "arm,idle-state"; idle-state-name = "silver-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <355>; - exit-latency-us = <909>; + entry-latency-us = <360>; + exit-latency-us = <531>; min-residency-us = <3934>; local-timer-stop; }; @@ -256,8 +256,8 @@ compatible = "arm,idle-state"; idle-state-name = "gold-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <241>; - exit-latency-us = <1461>; + entry-latency-us = <702>; + exit-latency-us = <1061>; min-residency-us = <4488>; local-timer-stop; }; -- cgit v1.2.3-59-g8ed1b From 951151c2bb548e0f6b2c40ab4c48675f5342c914 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 5 Jul 2023 15:36:23 +0200 Subject: arm64: dts: qcom: sm8350: Add missing LMH interrupts to cpufreq Add the missing interrupts that communicate the hardware-managed throttling to Linux. Fixes: ccbb3abb23a5 ("arm64: dts: qcom: sm8350: Add cpufreq node") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230705-topic-sm8350_fixes-v1-3-0f69f70ccb6a@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index d5dcfc0deae5..7f2e27e3296f 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -3403,6 +3403,13 @@ <0 0x18593000 0 0x1000>; reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; + interrupts = , + , + ; + interrupt-names = "dcvsh-irq-0", + "dcvsh-irq-1", + "dcvsh-irq-2"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; clock-names = "xo", "alternate"; -- cgit v1.2.3-59-g8ed1b From 068be6cb4b98a8a26426b603b23582b78630dd23 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 5 Jul 2023 16:42:26 +0200 Subject: arm64: dts: qcom: add missing space before { Add missing whitespace between node name/label and opening {. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230705144226.280490-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 94cb59d2761c..2420f44d87e3 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -3429,7 +3429,7 @@ #size-cells = <1>; ranges = <0 0 0 0x20000000>; - frame@17c21000{ + frame@17c21000 { reg = <0x17c21000 0x1000>, <0x17c22000 0x1000>; frame-number = <0>; diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi index b841ea9192ae..85e5cf3dc91e 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi @@ -565,7 +565,7 @@ }; }; - port@1{ + port@1 { reg = <1>; panel_in_1: endpoint { -- cgit v1.2.3-59-g8ed1b From 9c31a3f5abc9eeb6509d06041b1e5f12deb39c4d Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 5 Jul 2023 17:00:05 +0200 Subject: arm64: dts: qcom: sc8180x: Fix cluster PSCI suspend param The value was copypasted from 8150, but 8180 expects a different one. Confirmed with both downstream device tree and Windows DSDT, not tested on hardware (sorry, I don't have any). Fix it. Fixes: 8575f197b077 ("arm64: dts: qcom: Introduce the SC8180x platform") Signed-off-by: Konrad Dybcio Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230705-topic-8180_sleep-v1-1-c5dce117364e@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 2420f44d87e3..a65dfd136ca9 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -298,7 +298,7 @@ domain-idle-states { CLUSTER_SLEEP_0: cluster-sleep-0 { compatible = "domain-idle-state"; - arm,psci-suspend-param = <0x4100c244>; + arm,psci-suspend-param = <0x4100a344>; entry-latency-us = <3263>; exit-latency-us = <6562>; min-residency-us = <9987>; -- cgit v1.2.3-59-g8ed1b From 4390730cc12af25f7c997f477795f5f4200149c0 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 6 Jul 2023 18:35:37 +0200 Subject: arm64: dts: qcom: sm8350: Use proper CPU compatibles The Kryo names (once again) turned out to be fake. The CPUs report: 0x412fd050 (CA55 r2p0) (0 - 3) 0x411fd410 (CA78 r1p1) (4 - 6) 0x411fd440 (CX1 r1p1) (7) Use the compatibles that reflect that. Fixes: b7e8f433a673 ("arm64: dts: qcom: Add basic devicetree support for SM8350 SoC") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230706-topic-sm8350-cpu-compat-v1-1-f8d6a1869781@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 7f2e27e3296f..b1f9f447b78b 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -48,7 +48,7 @@ CPU0: cpu@0 { device_type = "cpu"; - compatible = "qcom,kryo685"; + compatible = "arm,cortex-a55"; reg = <0x0 0x0>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; @@ -72,7 +72,7 @@ CPU1: cpu@100 { device_type = "cpu"; - compatible = "qcom,kryo685"; + compatible = "arm,cortex-a55"; reg = <0x0 0x100>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; @@ -91,7 +91,7 @@ CPU2: cpu@200 { device_type = "cpu"; - compatible = "qcom,kryo685"; + compatible = "arm,cortex-a55"; reg = <0x0 0x200>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; @@ -110,7 +110,7 @@ CPU3: cpu@300 { device_type = "cpu"; - compatible = "qcom,kryo685"; + compatible = "arm,cortex-a55"; reg = <0x0 0x300>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; @@ -129,7 +129,7 @@ CPU4: cpu@400 { device_type = "cpu"; - compatible = "qcom,kryo685"; + compatible = "arm,cortex-a78"; reg = <0x0 0x400>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; @@ -148,7 +148,7 @@ CPU5: cpu@500 { device_type = "cpu"; - compatible = "qcom,kryo685"; + compatible = "arm,cortex-a78"; reg = <0x0 0x500>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; @@ -167,7 +167,7 @@ CPU6: cpu@600 { device_type = "cpu"; - compatible = "qcom,kryo685"; + compatible = "arm,cortex-a78"; reg = <0x0 0x600>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; @@ -186,7 +186,7 @@ CPU7: cpu@700 { device_type = "cpu"; - compatible = "qcom,kryo685"; + compatible = "arm,cortex-x1"; reg = <0x0 0x700>; clocks = <&cpufreq_hw 2>; enable-method = "psci"; -- cgit v1.2.3-59-g8ed1b From 64f19c06f704846db5e4885ca63c689d9bef5723 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 7 Jul 2023 15:30:21 +0300 Subject: arm64: dts: qcom: pm8350: fix thermal zone name The name of the thermal zone in pm8350.dtsi (pm8350c-thermal) conflicts with the thermal zone in pm8350c.dtsi. Rename the thermal zone according to the chip name. Fixes: 7a79b95f4288 ("arm64: dts: qcom: pm8350: add temp sensor and thermal zone config") Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20230707123027.1510723-3-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm8350.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pm8350.dtsi b/arch/arm64/boot/dts/qcom/pm8350.dtsi index 2dfeb99300d7..9ed9ba23e81e 100644 --- a/arch/arm64/boot/dts/qcom/pm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8350.dtsi @@ -8,7 +8,7 @@ / { thermal-zones { - pm8350_thermal: pm8350c-thermal { + pm8350_thermal: pm8350-thermal { polling-delay-passive = <100>; polling-delay = <0>; thermal-sensors = <&pm8350_temp_alarm>; -- cgit v1.2.3-59-g8ed1b From aad41d9e6c44dfe299cddab97528a5333f17bdfe Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 7 Jul 2023 15:30:22 +0300 Subject: arm64: dts: qcom: pm8350b: fix thermal zone name The name of the thermal zone in pm8350b.dtsi (pm8350c-thermal) conflicts with the thermal zone in pm8350c.dtsi. Rename the thermal zone according to the chip name. Fixes: 5c1399299d9d ("arm64: dts: qcom: pm8350b: add temp sensor and thermal zone config") Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20230707123027.1510723-4-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm8350b.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pm8350b.dtsi b/arch/arm64/boot/dts/qcom/pm8350b.dtsi index f1c7bd9d079c..05c105898892 100644 --- a/arch/arm64/boot/dts/qcom/pm8350b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8350b.dtsi @@ -8,7 +8,7 @@ / { thermal-zones { - pm8350b_thermal: pm8350c-thermal { + pm8350b_thermal: pm8350b-thermal { polling-delay-passive = <100>; polling-delay = <0>; thermal-sensors = <&pm8350b_temp_alarm>; -- cgit v1.2.3-59-g8ed1b From 99f8cf491d546cd668236f573c7d846d3e94f2d6 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 7 Jul 2023 15:30:23 +0300 Subject: arm64: dts: qcom: pmr735b: fix thermal zone name The name of the thermal zone in pmr735b.dtsi (pmr735a-thermal) conflicts with the thermal zone in pmr735a.dtsi. Rename the thermal zone according to the chip name. Fixes: 6f3426b3dea4 ("arm64: dts: qcom: pmr735b: add temp sensor and thermal zone config") Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20230707123027.1510723-5-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pmr735b.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pmr735b.dtsi b/arch/arm64/boot/dts/qcom/pmr735b.dtsi index ec24c4478005..f7473e247322 100644 --- a/arch/arm64/boot/dts/qcom/pmr735b.dtsi +++ b/arch/arm64/boot/dts/qcom/pmr735b.dtsi @@ -8,7 +8,7 @@ / { thermal-zones { - pmr735a_thermal: pmr735a-thermal { + pmr735b_thermal: pmr735b-thermal { polling-delay-passive = <100>; polling-delay = <0>; thermal-sensors = <&pmr735b_temp_alarm>; -- cgit v1.2.3-59-g8ed1b From 435a73d7377ceb29c1a22d2711dd85c831b40c45 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 7 Jul 2023 15:30:24 +0300 Subject: arm64: dts: qcom: pmk8350: fix ADC-TM compatible string The commit b2de43136058 ("arm64: dts: qcom: pmk8350: Add peripherals for pmk8350") for the ADC TM (thermal monitoring device) have used the compatible string from the vendor kernel ("qcom,adc-tm7"). Use the proper compatible string that is defined in the upstream kernel ("qcom,spmi-adc-tm5-gen2"). Fixes: b2de43136058 ("arm64: dts: qcom: pmk8350: Add peripherals for pmk8350") Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20230707123027.1510723-6-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pmk8350.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pmk8350.dtsi b/arch/arm64/boot/dts/qcom/pmk8350.dtsi index bc6297e7253e..1eb74017062d 100644 --- a/arch/arm64/boot/dts/qcom/pmk8350.dtsi +++ b/arch/arm64/boot/dts/qcom/pmk8350.dtsi @@ -59,7 +59,7 @@ }; pmk8350_adc_tm: adc-tm@3400 { - compatible = "qcom,adc-tm7"; + compatible = "qcom,spmi-adc-tm5-gen2"; reg = <0x3400>; interrupts = ; #address-cells = <1>; -- cgit v1.2.3-59-g8ed1b From 701b59db773730a914f1778cf2dd05e3a05c2c69 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 7 Jul 2023 15:30:25 +0300 Subject: arm64: dts: qcom: sm8450-hdk: remove pmr735b PMIC inclusion The 8450-HDK doesn't use PMR735B PMIC. Drop its inclusion to remove the warning during the HDK bootup. Fixes: 30464456a1ea ("arm64: dts: qcom: sm8450-hdk: add pmic files") Reviewed-by: Neil Armstrong Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20230707123027.1510723-7-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 7e6564a112ee..f44430a372cd 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -14,7 +14,6 @@ #include "pm8450.dtsi" #include "pmk8350.dtsi" #include "pmr735a.dtsi" -#include "pmr735b.dtsi" / { model = "Qualcomm Technologies, Inc. SM8450 HDK"; -- cgit v1.2.3-59-g8ed1b From 53ccae05c90fc9f961cc18945ab8d53c6ade7ca6 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 7 Jul 2023 15:30:26 +0300 Subject: arm64: dts: qcom: sm8450-hdk: define DIE_TEMP channels Declare the DIE_TEMP channels provided by PMICs. Use them to provide temperature reading for the spmi-temp-alarm thermal zones. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20230707123027.1510723-8-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 43 +++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index f44430a372cd..50094b2704c2 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -6,6 +6,10 @@ /dts-v1/; #include +#include +#include +#include +#include #include #include "sm8450.dtsi" #include "pm8350.dtsi" @@ -581,6 +585,45 @@ vdda-pll-supply = <&vreg_l6b_1p2>; }; +&pm8350_temp_alarm { + io-channels = <&pmk8350_vadc PM8350_ADC7_DIE_TEMP(1)>; + io-channel-names = "thermal"; +}; + +&pm8350b_temp_alarm { + io-channels = <&pmk8350_vadc PM8350B_ADC7_DIE_TEMP>; + io-channel-names = "thermal"; +}; + +&pmr735a_temp_alarm { + io-channels = <&pmk8350_vadc PMR735A_ADC7_DIE_TEMP>; + io-channel-names = "thermal"; +}; + +&pmk8350_vadc { + status = "okay"; + + channel@3 { + reg = ; + label = "pmk8350_die_temp"; + }; + + channel@103 { + reg = ; + label = "pm8350_die_temp"; + }; + + channel@303 { + reg = ; + label = "pm8350b_die_temp"; + }; + + channel@403 { + reg = ; + label = "pmr735a_die_temp"; + }; +}; + &remoteproc_adsp { status = "okay"; firmware-name = "qcom/sm8450/adsp.mbn"; -- cgit v1.2.3-59-g8ed1b From 10848179ae9778d624a124f72a8f22c7c1687a7d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 7 Jul 2023 15:30:27 +0300 Subject: arm64: dts: qcom: sm8450-hdk: add ADC-TM thermal zones Add thermal zones controlled through the ADC-TM (ADC thermal monitoring) PMIC interface. This includes several onboard sensors and the XO thermal sensor. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20230707123027.1510723-9-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 244 ++++++++++++++++++++++++++++++++ 1 file changed, 244 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 50094b2704c2..bd5e8181f2aa 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -134,6 +134,120 @@ }; }; + thermal-zones { + camera-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 2>; + + trips { + active-config0 { + temperature = <75000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + }; + + rear-tof-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 5>; + + trips { + active-config0 { + temperature = <75000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + }; + + skin-msm-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 1>; + + trips { + active-config0 { + temperature = <75000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + }; + + therm1-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 3>; + + trips { + active-config0 { + temperature = <75000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + }; + + therm2-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 6>; + + trips { + active-config0 { + temperature = <75000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + }; + + usb-conn-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 7>; + + trips { + active-config0 { + temperature = <75000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + }; + + wide-rfc-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 4>; + + trips { + active-config0 { + temperature = <75000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + }; + + xo-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 0>; + + trips { + active-config0 { + temperature = <50000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -600,6 +714,66 @@ io-channel-names = "thermal"; }; +&pmk8350_adc_tm { + status = "okay"; + + xo-therm@0 { + reg = <0>; + io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + skin-msm-therm@1 { + reg = <1>; + io-channels = <&pmk8350_vadc PM8350_ADC7_AMUX_THM1_100K_PU(1)>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + camera-therm@2 { + reg = <2>; + io-channels = <&pmk8350_vadc PM8350_ADC7_AMUX_THM2_100K_PU(1)>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + therm1-therm@3 { + reg = <3>; + io-channels = <&pmk8350_vadc PM8350_ADC7_AMUX_THM3_100K_PU(1)>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + wide-rfc-therm@4 { + reg = <4>; + io-channels = <&pmk8350_vadc PM8350_ADC7_AMUX_THM4_100K_PU(1)>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + rear-tof-therm@5 { + reg = <5>; + io-channels = <&pmk8350_vadc PM8350_ADC7_AMUX_THM5_100K_PU(1)>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + therm2-therm@6 { + reg = <6>; + io-channels = <&pmk8350_vadc PM8350_ADC7_GPIO3_100K_PU(1)>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + usb-conn-therm@7 { + reg = <7>; + io-channels = <&pmk8350_vadc PM8350B_ADC7_AMUX_THM5_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + &pmk8350_vadc { status = "okay"; @@ -608,20 +782,90 @@ label = "pmk8350_die_temp"; }; + channel@44 { + reg = ; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + label = "pmk8350_xo_therm"; + }; + channel@103 { reg = ; label = "pm8350_die_temp"; }; + channel@144 { + reg = ; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + label = "skin_msm_temp"; + }; + + channel@145 { + reg = ; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + label = "camera_temp"; + }; + + channel@146 { + reg = ; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + label = "therm1_temp"; + }; + + channel@147 { + reg = ; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + label = "wide_rfc_temp"; + }; + + channel@148 { + reg = ; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + label = "rear_tof_temp"; + }; + + channel@14c { + reg = ; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + label = "therm2_temp"; + }; + channel@303 { reg = ; label = "pm8350b_die_temp"; }; + channel@348 { + reg = ; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + label = "usb_conn_temp"; + }; + channel@403 { reg = ; label = "pmr735a_die_temp"; }; + + channel@44a { + reg = ; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + label = "qtm_w_temp"; + }; + + channel@44b { + reg = ; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + label = "qtm_n_temp"; + }; }; &remoteproc_adsp { -- cgit v1.2.3-59-g8ed1b From 339d38a436f30d0f874815eafc7de2257346bf26 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 4 Jul 2023 14:23:17 +0200 Subject: arm64: dts: qcom: sm8250: Mark PCIe hosts as DMA coherent The PCIe hosts on SM8250 are cache-coherent. Mark them as such. Fixes: e53bdfc00977 ("arm64: dts: qcom: sm8250: Add PCIe support") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230704-topic-8250_pcie_dmac-v1-1-799603a980b0@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 4c61f47ee9bd..d0b21c48ea9b 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1905,6 +1905,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; + dma-coherent; status = "disabled"; }; @@ -2011,6 +2012,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; + dma-coherent; status = "disabled"; }; @@ -2119,6 +2121,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pcie2_default_state>; + dma-coherent; status = "disabled"; }; -- cgit v1.2.3-59-g8ed1b From 4cb19bd7c6329c4702f92c6dd4e7c02eb903ca13 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 4 Jul 2023 14:23:18 +0200 Subject: arm64: dts: qcom: sm8250: Mark SMMUs as DMA coherent The SMMUs on SM8250 are cache-coherent. Mark them as such. Fixes: a89441fcd09d ("arm64: dts: qcom: sm8250: add apps_smmu node") Fixes: 04a3605b184e ("arm64: dts: qcom: add sm8250 GPU nodes") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230704-topic-8250_pcie_dmac-v1-2-799603a980b0@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index d0b21c48ea9b..6359e5d09544 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2729,6 +2729,7 @@ clock-names = "ahb", "bus", "iface"; power-domains = <&gpucc GPU_CX_GDSC>; + dma-coherent; }; slpi: remoteproc@5c00000 { @@ -5399,6 +5400,7 @@ , , ; + dma-coherent; }; adsp: remoteproc@17300000 { -- cgit v1.2.3-59-g8ed1b From 8bb8688c1d73f21f413e4ea2a37fbbb90997f2bd Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 12 May 2023 03:13:34 +0300 Subject: arm64: dts: qcom: msm8996: scale CBF clock according to the CPUfreq Turn CBF into the interconnect provider. Scale CBF frequency (bandwidth) according to CPU frequencies. Reviewed-by: Konrad Dybcio Tested-by: Yassine Oudjana Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20230512001334.2983048-5-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 51 +++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index de20e62284cc..b5866b111061 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -49,6 +50,7 @@ cpu-idle-states = <&CPU_SLEEP_0>; capacity-dmips-mhz = <1024>; clocks = <&kryocc 0>; + interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; operating-points-v2 = <&cluster0_opp>; #cooling-cells = <2>; next-level-cache = <&L2_0>; @@ -67,6 +69,7 @@ cpu-idle-states = <&CPU_SLEEP_0>; capacity-dmips-mhz = <1024>; clocks = <&kryocc 0>; + interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; operating-points-v2 = <&cluster0_opp>; #cooling-cells = <2>; next-level-cache = <&L2_0>; @@ -80,6 +83,7 @@ cpu-idle-states = <&CPU_SLEEP_0>; capacity-dmips-mhz = <1024>; clocks = <&kryocc 1>; + interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; operating-points-v2 = <&cluster1_opp>; #cooling-cells = <2>; next-level-cache = <&L2_1>; @@ -98,6 +102,7 @@ cpu-idle-states = <&CPU_SLEEP_0>; capacity-dmips-mhz = <1024>; clocks = <&kryocc 1>; + interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; operating-points-v2 = <&cluster1_opp>; #cooling-cells = <2>; next-level-cache = <&L2_1>; @@ -149,91 +154,109 @@ opp-hz = /bits/ 64 <307200000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; }; opp-422400000 { opp-hz = /bits/ 64 <422400000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; }; opp-480000000 { opp-hz = /bits/ 64 <480000000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; }; opp-556800000 { opp-hz = /bits/ 64 <556800000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; }; opp-652800000 { opp-hz = /bits/ 64 <652800000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <384000>; }; opp-729600000 { opp-hz = /bits/ 64 <729600000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <460800>; }; opp-844800000 { opp-hz = /bits/ 64 <844800000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <537600>; }; opp-960000000 { opp-hz = /bits/ 64 <960000000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <672000>; }; opp-1036800000 { opp-hz = /bits/ 64 <1036800000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <672000>; }; opp-1113600000 { opp-hz = /bits/ 64 <1113600000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <825600>; }; opp-1190400000 { opp-hz = /bits/ 64 <1190400000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <825600>; }; opp-1228800000 { opp-hz = /bits/ 64 <1228800000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <902400>; }; opp-1324800000 { opp-hz = /bits/ 64 <1324800000>; opp-supported-hw = <0xd>; clock-latency-ns = <200000>; + opp-peak-kBps = <1056000>; }; opp-1363200000 { opp-hz = /bits/ 64 <1363200000>; opp-supported-hw = <0x2>; clock-latency-ns = <200000>; + opp-peak-kBps = <1132800>; }; opp-1401600000 { opp-hz = /bits/ 64 <1401600000>; opp-supported-hw = <0xd>; clock-latency-ns = <200000>; + opp-peak-kBps = <1132800>; }; opp-1478400000 { opp-hz = /bits/ 64 <1478400000>; opp-supported-hw = <0x9>; clock-latency-ns = <200000>; + opp-peak-kBps = <1190400>; }; opp-1497600000 { opp-hz = /bits/ 64 <1497600000>; opp-supported-hw = <0x04>; clock-latency-ns = <200000>; + opp-peak-kBps = <1305600>; }; opp-1593600000 { opp-hz = /bits/ 64 <1593600000>; opp-supported-hw = <0x9>; clock-latency-ns = <200000>; + opp-peak-kBps = <1382400>; }; }; @@ -247,136 +270,163 @@ opp-hz = /bits/ 64 <307200000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; }; opp-403200000 { opp-hz = /bits/ 64 <403200000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; }; opp-480000000 { opp-hz = /bits/ 64 <480000000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; }; opp-556800000 { opp-hz = /bits/ 64 <556800000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; }; opp-652800000 { opp-hz = /bits/ 64 <652800000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; }; opp-729600000 { opp-hz = /bits/ 64 <729600000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; }; opp-806400000 { opp-hz = /bits/ 64 <806400000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <384000>; }; opp-883200000 { opp-hz = /bits/ 64 <883200000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <460800>; }; opp-940800000 { opp-hz = /bits/ 64 <940800000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <537600>; }; opp-1036800000 { opp-hz = /bits/ 64 <1036800000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <595200>; }; opp-1113600000 { opp-hz = /bits/ 64 <1113600000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <672000>; }; opp-1190400000 { opp-hz = /bits/ 64 <1190400000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <672000>; }; opp-1248000000 { opp-hz = /bits/ 64 <1248000000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <748800>; }; opp-1324800000 { opp-hz = /bits/ 64 <1324800000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <825600>; }; opp-1401600000 { opp-hz = /bits/ 64 <1401600000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <902400>; }; opp-1478400000 { opp-hz = /bits/ 64 <1478400000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <979200>; }; opp-1555200000 { opp-hz = /bits/ 64 <1555200000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <1056000>; }; opp-1632000000 { opp-hz = /bits/ 64 <1632000000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <1190400>; }; opp-1708800000 { opp-hz = /bits/ 64 <1708800000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <1228800>; }; opp-1785600000 { opp-hz = /bits/ 64 <1785600000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <1305600>; }; opp-1804800000 { opp-hz = /bits/ 64 <1804800000>; opp-supported-hw = <0xe>; clock-latency-ns = <200000>; + opp-peak-kBps = <1305600>; }; opp-1824000000 { opp-hz = /bits/ 64 <1824000000>; opp-supported-hw = <0x1>; clock-latency-ns = <200000>; + opp-peak-kBps = <1382400>; }; opp-1900800000 { opp-hz = /bits/ 64 <1900800000>; opp-supported-hw = <0x4>; clock-latency-ns = <200000>; + opp-peak-kBps = <1305600>; }; opp-1920000000 { opp-hz = /bits/ 64 <1920000000>; opp-supported-hw = <0x1>; clock-latency-ns = <200000>; + opp-peak-kBps = <1459200>; }; opp-1996800000 { opp-hz = /bits/ 64 <1996800000>; opp-supported-hw = <0x1>; clock-latency-ns = <200000>; + opp-peak-kBps = <1593600>; }; opp-2073600000 { opp-hz = /bits/ 64 <2073600000>; opp-supported-hw = <0x1>; clock-latency-ns = <200000>; + opp-peak-kBps = <1593600>; }; opp-2150400000 { opp-hz = /bits/ 64 <2150400000>; opp-supported-hw = <0x1>; clock-latency-ns = <200000>; + opp-peak-kBps = <1593600>; }; }; @@ -3554,6 +3604,7 @@ reg = <0x09a11000 0x10000>; clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>; #clock-cells = <0>; + #interconnect-cells = <1>; }; intc: interrupt-controller@9bc0000 { -- cgit v1.2.3-59-g8ed1b From 2a2bd124d4c01c53833a4f0c7fef4faf18351c51 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 11 Jul 2023 16:35:15 +0200 Subject: arm64: dts: qcom: sm8250: Add BWMONs Add the CPU and LLC BWMONs (skip the NPU ones for now) on sm8250. LPDDR4X levels are skipped, as LPDDR5 seems more popular with SM8250 and voting for inexistent levels doesn't uptick the bus frequency, which results in no increased bandwidth, which results in bwmon deciding we shouldn't go higher.. you see the point! Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230711-topic-sm638250_bwmon-v1-3-bd4bb96b0673@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 122 +++++++++++++++++++++++++++++++++++ 1 file changed, 122 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 6359e5d09544..c4e4f75e3941 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3694,6 +3694,128 @@ }; }; + pmu@9091000 { + compatible = "qcom,sm8250-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; + reg = <0 0x09091000 0 0x1000>; + + interrupts = ; + + interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI_CH0 3>; + + operating-points-v2 = <&llcc_bwmon_opp_table>; + + llcc_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-800000 { + opp-peak-kBps = <(200 * 4 * 1000)>; + }; + + opp-1200000 { + opp-peak-kBps = <(300 * 4 * 1000)>; + }; + + opp-1804000 { + opp-peak-kBps = <(451 * 4 * 1000)>; + }; + + opp-2188000 { + opp-peak-kBps = <(547 * 4 * 1000)>; + }; + + opp-2724000 { + opp-peak-kBps = <(681 * 4 * 1000)>; + }; + + opp-3072000 { + opp-peak-kBps = <(768 * 4 * 1000)>; + }; + + opp-4068000 { + opp-peak-kBps = <(1017 * 4 * 1000)>; + }; + + /* 1353 MHz, LPDDR4X */ + + opp-6220000 { + opp-peak-kBps = <(1555 * 4 * 1000)>; + }; + + opp-7216000 { + opp-peak-kBps = <(1804 * 4 * 1000)>; + }; + + opp-8368000 { + opp-peak-kBps = <(2092 * 4 * 1000)>; + }; + + /* LPDDR5 */ + opp-10944000 { + opp-peak-kBps = <(2736 * 4 * 1000)>; + }; + }; + }; + + pmu@90b6400 { + compatible = "qcom,sm8250-cpu-bwmon", "qcom,sdm845-bwmon"; + reg = <0 0x090b6400 0 0x600>; + + interrupts = ; + + interconnects = <&gem_noc MASTER_AMPSS_M0 3 &gem_noc SLAVE_LLCC 3>; + operating-points-v2 = <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-800000 { + opp-peak-kBps = <(200 * 4 * 1000)>; + }; + + opp-1804000 { + opp-peak-kBps = <(451 * 4 * 1000)>; + }; + + opp-2188000 { + opp-peak-kBps = <(547 * 4 * 1000)>; + }; + + opp-2724000 { + opp-peak-kBps = <(681 * 4 * 1000)>; + }; + + opp-3072000 { + opp-peak-kBps = <(768 * 4 * 1000)>; + }; + + /* 1017MHz, 1353 MHz, LPDDR4X */ + + opp-6220000 { + opp-peak-kBps = <(1555 * 4 * 1000)>; + }; + + opp-6832000 { + opp-peak-kBps = <(1708 * 4 * 1000)>; + }; + + opp-8368000 { + opp-peak-kBps = <(2092 * 4 * 1000)>; + }; + + /* 2133MHz, LPDDR4X */ + + /* LPDDR5 */ + opp-10944000 { + opp-peak-kBps = <(2736 * 4 * 1000)>; + }; + + /* LPDDR5 */ + opp-12784000 { + opp-peak-kBps = <(3196 * 4 * 1000)>; + }; + }; + }; + dc_noc: interconnect@90c0000 { compatible = "qcom,sm8250-dc-noc"; reg = <0 0x090c0000 0 0x4200>; -- cgit v1.2.3-59-g8ed1b From 1df6b32e3819dc1de5ccd49982686153ab9e158c Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 11 Jul 2023 16:35:16 +0200 Subject: arm64: dts: qcom: sm6350: Add BWMONs Add the CPU and LLC BWMONs (skip the NPU ones for now) on sm6350. There are 3 more NPU BWMONs, but these are skipped for now. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230711-topic-sm638250_bwmon-v1-4-bd4bb96b0673@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 97 ++++++++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index c2b5d56ba242..8f66306d1de3 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1723,6 +1723,103 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + pmu@90b6300 { + compatible = "qcom,sm6350-llcc-bwmon", "qcom,sdm845-bwmon"; + reg = <0x0 0x090b6300 0x0 0x600>; + interrupts = ; + + operating-points-v2 = <&llcc_bwmon_opp_table>; + interconnects = <&clk_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>; + + llcc_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <2288000>; + }; + + opp-1 { + opp-peak-kBps = <4577000>; + }; + + opp-2 { + opp-peak-kBps = <7110000>; + }; + + opp-3 { + opp-peak-kBps = <9155000>; + }; + + opp-4 { + opp-peak-kBps = <12298000>; + }; + + opp-5 { + opp-peak-kBps = <14236000>; + }; + + }; + }; + + pmu@90cd000 { + compatible = "qcom,sm6350-cpu-bwmon", "qcom,sc7280-llcc-bwmon"; + reg = <0x0 0x090cd000 0x0 0x1000>; + interrupts = ; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>; + + cpu_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <762000>; + }; + + opp-1 { + opp-peak-kBps = <1144000>; + }; + + opp-2 { + opp-peak-kBps = <1720000>; + }; + + opp-3 { + opp-peak-kBps = <2086000>; + }; + + opp-4 { + opp-peak-kBps = <2597000>; + }; + + opp-5 { + opp-peak-kBps = <2929000>; + }; + + opp-6 { + opp-peak-kBps = <3879000>; + }; + + opp-7 { + opp-peak-kBps = <5161000>; + }; + + opp-8 { + opp-peak-kBps = <5931000>; + }; + + opp-9 { + opp-peak-kBps = <6881000>; + }; + + opp-10 { + opp-peak-kBps = <7980000>; + }; + }; + }; + usb_1: usb@a6f8800 { compatible = "qcom,sm6350-dwc3", "qcom,dwc3"; reg = <0 0x0a6f8800 0 0x400>; -- cgit v1.2.3-59-g8ed1b From 5e6d88815c2f8ec5e30101de7de5f6de72576a61 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 11 Jul 2023 13:00:53 +0200 Subject: arm64: dts: qcom: sc7180: Bring back cpufreq-based DDR votes ChromeOS folks reported that bwmon is too slow and getting rid of statically defined CPUFREQ-based votes (effectively floor votes because of how opp-peak-kBps is interpreted), has a major performance impact in some common applications. Bring them back until MEMLAT support is introduced. This is a partial revert of the commit referenced in the fixes tag. Fixes: adc16b84e1ea ("arm64: dts: qcom: sc7180: Hook up BWMONs") Reported-by: Douglas Anderson Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230711-topic-7180ddr-v1-1-56e4f13afe9b@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-lite.dtsi | 10 ++-- arch/arm64/boot/dts/qcom/sc7180.dtsi | 76 +++++++++++++++++-------------- 2 files changed, 47 insertions(+), 39 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-lite.dtsi b/arch/arm64/boot/dts/qcom/sc7180-lite.dtsi index 975d4422f27b..4b306a59d9be 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-lite.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-lite.dtsi @@ -6,21 +6,21 @@ */ &cpu6_opp10 { - opp-peak-kBps = <22425600>; + opp-peak-kBps = <7216000 22425600>; }; &cpu6_opp11 { - opp-peak-kBps = <22425600>; + opp-peak-kBps = <7216000 22425600>; }; &cpu6_opp12 { - opp-peak-kBps = <23347200>; + opp-peak-kBps = <8532000 23347200>; }; &cpu6_opp13 { - opp-peak-kBps = <23347200>; + opp-peak-kBps = <8532000 23347200>; }; &cpu6_opp14 { - opp-peak-kBps = <23347200>; + opp-peak-kBps = <8532000 23347200>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 179544ba12db..9af94e267f84 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -85,7 +85,8 @@ capacity-dmips-mhz = <415>; dynamic-power-coefficient = <137>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; next-level-cache = <&L2_0>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; @@ -115,7 +116,8 @@ dynamic-power-coefficient = <137>; next-level-cache = <&L2_100>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; L2_100: l2-cache { @@ -139,7 +141,8 @@ dynamic-power-coefficient = <137>; next-level-cache = <&L2_200>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; L2_200: l2-cache { @@ -163,7 +166,8 @@ dynamic-power-coefficient = <137>; next-level-cache = <&L2_300>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; L2_300: l2-cache { @@ -187,7 +191,8 @@ dynamic-power-coefficient = <137>; next-level-cache = <&L2_400>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; L2_400: l2-cache { @@ -211,7 +216,8 @@ dynamic-power-coefficient = <137>; next-level-cache = <&L2_500>; operating-points-v2 = <&cpu0_opp_table>; - interconnects = <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 0>; L2_500: l2-cache { @@ -235,7 +241,8 @@ dynamic-power-coefficient = <480>; next-level-cache = <&L2_600>; operating-points-v2 = <&cpu6_opp_table>; - interconnects = <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 1>; L2_600: l2-cache { @@ -259,7 +266,8 @@ dynamic-power-coefficient = <480>; next-level-cache = <&L2_700>; operating-points-v2 = <&cpu6_opp_table>; - interconnects = <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; #cooling-cells = <2>; qcom,freq-domain = <&cpufreq_hw 1>; L2_700: l2-cache { @@ -379,52 +387,52 @@ cpu0_opp1: opp-300000000 { opp-hz = /bits/ 64 <300000000>; - opp-peak-kBps = <4800000>; + opp-peak-kBps = <1200000 4800000>; }; cpu0_opp2: opp-576000000 { opp-hz = /bits/ 64 <576000000>; - opp-peak-kBps = <4800000>; + opp-peak-kBps = <1200000 4800000>; }; cpu0_opp3: opp-768000000 { opp-hz = /bits/ 64 <768000000>; - opp-peak-kBps = <4800000>; + opp-peak-kBps = <1200000 4800000>; }; cpu0_opp4: opp-1017600000 { opp-hz = /bits/ 64 <1017600000>; - opp-peak-kBps = <8908800>; + opp-peak-kBps = <1804000 8908800>; }; cpu0_opp5: opp-1248000000 { opp-hz = /bits/ 64 <1248000000>; - opp-peak-kBps = <12902400>; + opp-peak-kBps = <2188000 12902400>; }; cpu0_opp6: opp-1324800000 { opp-hz = /bits/ 64 <1324800000>; - opp-peak-kBps = <12902400>; + opp-peak-kBps = <2188000 12902400>; }; cpu0_opp7: opp-1516800000 { opp-hz = /bits/ 64 <1516800000>; - opp-peak-kBps = <15052800>; + opp-peak-kBps = <3072000 15052800>; }; cpu0_opp8: opp-1612800000 { opp-hz = /bits/ 64 <1612800000>; - opp-peak-kBps = <15052800>; + opp-peak-kBps = <3072000 15052800>; }; cpu0_opp9: opp-1708800000 { opp-hz = /bits/ 64 <1708800000>; - opp-peak-kBps = <15052800>; + opp-peak-kBps = <3072000 15052800>; }; cpu0_opp10: opp-1804800000 { opp-hz = /bits/ 64 <1804800000>; - opp-peak-kBps = <22425600>; + opp-peak-kBps = <4068000 22425600>; }; }; @@ -434,82 +442,82 @@ cpu6_opp1: opp-300000000 { opp-hz = /bits/ 64 <300000000>; - opp-peak-kBps = <8908800>; + opp-peak-kBps = <2188000 8908800>; }; cpu6_opp2: opp-652800000 { opp-hz = /bits/ 64 <652800000>; - opp-peak-kBps = <8908800>; + opp-peak-kBps = <2188000 8908800>; }; cpu6_opp3: opp-825600000 { opp-hz = /bits/ 64 <825600000>; - opp-peak-kBps = <8908800>; + opp-peak-kBps = <2188000 8908800>; }; cpu6_opp4: opp-979200000 { opp-hz = /bits/ 64 <979200000>; - opp-peak-kBps = <8908800>; + opp-peak-kBps = <2188000 8908800>; }; cpu6_opp5: opp-1113600000 { opp-hz = /bits/ 64 <1113600000>; - opp-peak-kBps = <8908800>; + opp-peak-kBps = <2188000 8908800>; }; cpu6_opp6: opp-1267200000 { opp-hz = /bits/ 64 <1267200000>; - opp-peak-kBps = <12902400>; + opp-peak-kBps = <4068000 12902400>; }; cpu6_opp7: opp-1555200000 { opp-hz = /bits/ 64 <1555200000>; - opp-peak-kBps = <15052800>; + opp-peak-kBps = <4068000 15052800>; }; cpu6_opp8: opp-1708800000 { opp-hz = /bits/ 64 <1708800000>; - opp-peak-kBps = <19353600>; + opp-peak-kBps = <6220000 19353600>; }; cpu6_opp9: opp-1843200000 { opp-hz = /bits/ 64 <1843200000>; - opp-peak-kBps = <19353600>; + opp-peak-kBps = <6220000 19353600>; }; cpu6_opp10: opp-1900800000 { opp-hz = /bits/ 64 <1900800000>; - opp-peak-kBps = <22425600>; + opp-peak-kBps = <6220000 22425600>; }; cpu6_opp11: opp-1996800000 { opp-hz = /bits/ 64 <1996800000>; - opp-peak-kBps = <22425600>; + opp-peak-kBps = <6220000 22425600>; }; cpu6_opp12: opp-2112000000 { opp-hz = /bits/ 64 <2112000000>; - opp-peak-kBps = <22425600>; + opp-peak-kBps = <6220000 22425600>; }; cpu6_opp13: opp-2208000000 { opp-hz = /bits/ 64 <2208000000>; - opp-peak-kBps = <22425600>; + opp-peak-kBps = <7216000 22425600>; }; cpu6_opp14: opp-2323200000 { opp-hz = /bits/ 64 <2323200000>; - opp-peak-kBps = <22425600>; + opp-peak-kBps = <7216000 22425600>; }; cpu6_opp15: opp-2400000000 { opp-hz = /bits/ 64 <2400000000>; - opp-peak-kBps = <23347200>; + opp-peak-kBps = <8532000 23347200>; }; cpu6_opp16: opp-2553600000 { opp-hz = /bits/ 64 <2553600000>; - opp-peak-kBps = <23347200>; + opp-peak-kBps = <8532000 23347200>; }; }; -- cgit v1.2.3-59-g8ed1b From b4fe47d12f1f8ee82ab18803d1ab074ff3d4b368 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 11 Jul 2023 12:28:17 +0200 Subject: arm64: dts: qcom: qrb2210-rb1: Add regulators Add and assign RPM regulators coming from PM2250. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20230711-topic-rb1_regulator-v1-1-bc4398c35800@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qrb2210-rb1.dts | 266 +++++++++++++++++++++++++++++++ 1 file changed, 266 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts index ef3616093289..eadba066972e 100644 --- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts @@ -38,6 +38,91 @@ wakeup-source; }; }; + + vreg_hdmi_out_1p2: regulator-hdmi-out-1p2 { + compatible = "regulator-fixed"; + regulator-name = "VREG_HDMI_OUT_1P2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vdc_1v2>; + regulator-always-on; + regulator-boot-on; + }; + + lt9611_3v3: regulator-lt9611-3v3 { + compatible = "regulator-fixed"; + regulator-name = "LT9611_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdc_3v3>; + regulator-always-on; + regulator-boot-on; + }; + + /* Main barrel jack input */ + vdc_12v: regulator-vdc-12v { + compatible = "regulator-fixed"; + regulator-name = "DC_12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + /* 1.2V supply stepped down from the barrel jack input */ + vdc_1v2: regulator-vdc-1v2 { + compatible = "regulator-fixed"; + regulator-name = "VDC_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vdc_12v>; + regulator-always-on; + regulator-boot-on; + }; + + /* 3.3V supply stepped down from the barrel jack input */ + vdc_3v3: regulator-vdc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdc_12v>; + regulator-always-on; + regulator-boot-on; + }; + + /* 5V supply stepped down from the barrel jack input */ + vdc_5v: regulator-vdc-5v { + compatible = "regulator-fixed"; + regulator-name = "VDC_5V"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + /* "Battery" voltage for the SoM, stepped down from the barrel jack input */ + vdc_vbat_som: regulator-vdc-vbat { + compatible = "regulator-fixed"; + regulator-name = "VBAT_SOM"; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + regulator-always-on; + regulator-boot-on; + }; + + /* PM2250 charger out, supplied by VBAT */ + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + vin-supply = <&vdc_vbat_som>; + + regulator-always-on; + regulator-boot-on; + }; }; &pm2250_resin { @@ -49,7 +134,183 @@ status = "okay"; }; +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm2250-regulators"; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12-supply = <&pm2250_s3>; + vdd_l4_l17_l18_l19_l20_l21_l22-supply = <&vph_pwr>; + vdd_l13_l14_l15_l16-supply = <&pm2250_s4>; + + /* + * S1 - VDD_APC + * S2 - VDD_CX + */ + + pm2250_s3: s3 { + /* 0.4V-1.6625V -> 1.3V (Power tree requirements) */ + regulator-min-microvolts = <1350000>; + regulator-max-microvolts = <1350000>; + regulator-boot-on; + }; + + pm2250_s4: s4 { + /* 1.2V-2.35V -> 2.05V (Power tree requirements) */ + regulator-min-microvolts = <2072000>; + regulator-max-microvolts = <2072000>; + regulator-boot-on; + }; + + /* L1 - VDD_MX */ + + pm2250_l2: l2 { + /* LPDDR4X VDD2 */ + regulator-min-microvolts = <1136000>; + regulator-max-microvolts = <1136000>; + regulator-always-on; + regulator-boot-on; + }; + + pm2250_l3: l3 { + /* LPDDR4X VDDQ */ + regulator-min-microvolts = <616000>; + regulator-max-microvolts = <616000>; + regulator-always-on; + regulator-boot-on; + }; + + pm2250_l4: l4 { + /* max = 3.05V -> max = just below 3V (SDHCI2) */ + regulator-min-microvolts = <1648000>; + regulator-max-microvolts = <2992000>; + regulator-allow-set-load; + }; + + pm2250_l5: l5 { + /* CSI/DSI */ + regulator-min-microvolts = <1232000>; + regulator-max-microvolts = <1232000>; + regulator-allow-set-load; + regulator-boot-on; + }; + + pm2250_l6: l6 { + /* DRAM PLL */ + regulator-min-microvolts = <928000>; + regulator-max-microvolts = <928000>; + regulator-always-on; + regulator-boot-on; + }; + + pm2250_l7: l7 { + /* Wi-Fi CX/MX */ + regulator-min-microvolts = <664000>; + regulator-max-microvolts = <664000>; + }; + + /* + * L8 - VDD_LPI_CX + * L9 - VDD_LPI_MX + */ + + pm2250_l10: l10 { + /* Wi-Fi RFA */ + regulator-min-microvolts = <1300000>; + regulator-max-microvolts = <1300000>; + }; + + pm2250_l11: l11 { + /* GPS RF1 */ + regulator-min-microvolts = <1000000>; + regulator-max-microvolts = <1000000>; + regulator-boot-on; + }; + + pm2250_l12: l12 { + /* USB PHYs */ + regulator-min-microvolts = <928000>; + regulator-max-microvolts = <928000>; + regulator-allow-set-load; + regulator-boot-on; + }; + + pm2250_l13: l13 { + /* USB/QFPROM/PLLs */ + regulator-min-microvolts = <1800000>; + regulator-max-microvolts = <1800000>; + regulator-allow-set-load; + regulator-boot-on; + }; + + pm2250_l14: l14 { + /* SDHCI1 VQMMC */ + regulator-min-microvolts = <1800000>; + regulator-max-microvolts = <1800000>; + regulator-allow-set-load; + /* Broken hardware, never turn it off! */ + regulator-always-on; + }; + + pm2250_l15: l15 { + /* WCD/DSI/BT VDDIO */ + regulator-min-microvolts = <1800000>; + regulator-max-microvolts = <1800000>; + regulator-allow-set-load; + regulator-always-on; + regulator-boot-on; + }; + + pm2250_l16: l16 { + /* GPS RF2 */ + regulator-min-microvolts = <1800000>; + regulator-max-microvolts = <1800000>; + regulator-boot-on; + }; + + pm2250_l17: l17 { + regulator-min-microvolts = <3000000>; + regulator-max-microvolts = <3000000>; + }; + + pm2250_l18: l18 { + /* VDD_PXn */ + regulator-min-microvolts = <1800000>; + regulator-max-microvolts = <1800000>; + }; + + pm2250_l19: l19 { + /* VDD_PXn */ + regulator-min-microvolts = <1800000>; + regulator-max-microvolts = <1800000>; + }; + + pm2250_l20: l20 { + /* SDHCI1 VMMC */ + regulator-min-microvolts = <2856000>; + regulator-max-microvolts = <2856000>; + regulator-allow-set-load; + }; + + pm2250_l21: l21 { + /* SDHCI2 VMMC */ + regulator-min-microvolts = <2960000>; + regulator-max-microvolts = <3300000>; + regulator-allow-set-load; + regulator-boot-on; + }; + + pm2250_l22: l22 { + /* Wi-Fi */ + regulator-min-microvolts = <3312000>; + regulator-max-microvolts = <3312000>; + }; + }; +}; + &sdhc_1 { + vmmc-supply = <&pm2250_l20>; + vqmmc-supply = <&pm2250_l14>; pinctrl-0 = <&sdc1_state_on>; pinctrl-1 = <&sdc1_state_off>; pinctrl-names = "default", "sleep"; @@ -61,6 +322,8 @@ }; &sdhc_2 { + vmmc-supply = <&pm2250_l21>; + vqmmc-supply = <&pm2250_l4>; cd-gpios = <&tlmm 88 GPIO_ACTIVE_LOW>; pinctrl-0 = <&sdc2_state_on &sd_det_in_on>; pinctrl-1 = <&sdc2_state_off &sd_det_in_off>; @@ -104,6 +367,9 @@ }; &usb_hsphy { + vdd-supply = <&pm2250_l12>; + vdda-pll-supply = <&pm2250_l13>; + vdda-phy-dpdm-supply = <&pm2250_l21>; status = "okay"; }; -- cgit v1.2.3-59-g8ed1b From b8fbeea0253211d97c579eae787274633d3eaf0d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 11 Jul 2023 08:30:11 +0200 Subject: arm64: dts: qcom: sm8250-sony-xperia: correct GPIO keys wakeup again gpio-keys,wakeup is a deprecated property: m8250-sony-xperia-edo-pdx206.dtb: gpio-keys: key-camera-focus: Unevaluated properties are not allowed ('gpio-key,wakeup' was unexpected) Fixes: a422c6a91a66 ("arm64: dts: qcom: sm8250-edo: Rectify gpio-keys") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230711063011.16222-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index cd27794739a5..ecdc20bc10f5 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -60,7 +60,7 @@ gpios = <&pm8150b_gpios 2 GPIO_ACTIVE_LOW>; debounce-interval = <15>; linux,can-disable; - gpio-key,wakeup; + wakeup-source; }; key-camera-snapshot { @@ -69,7 +69,7 @@ gpios = <&pm8150b_gpios 1 GPIO_ACTIVE_LOW>; debounce-interval = <15>; linux,can-disable; - gpio-key,wakeup; + wakeup-source; }; key-vol-down { -- cgit v1.2.3-59-g8ed1b From 4e125191e6cb00d6c3f3a8e1b67fd242e639b3c3 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 12 Jul 2023 15:11:45 +0300 Subject: arm64: dts: qcom: sm8450: provide MDSS cfg interconnect Add support for the MDSS cfg-cpu bus vote on the SM8450 platform. Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20230712121145.1994830-9-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 1668d97ce459..1d003297a497 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -2720,8 +2721,12 @@ /* same path used twice */ interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, - <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>; - interconnect-names = "mdp0-mem", "mdp1-mem"; + <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "mdp1-mem", + "cpu-cfg"; resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; -- cgit v1.2.3-59-g8ed1b From 752f585805c559e7c990e7d23e49d03167065761 Mon Sep 17 00:00:00 2001 From: Praveenkumar I Date: Thu, 13 Jul 2023 14:01:01 +0530 Subject: arm64: dts: qcom: ipq9574: Add cpu cooling maps Add cpu cooling maps for passive trip points. The cpu cooling device states are mapped to cpufreq based scaling frequencies. Signed-off-by: Praveenkumar I Link: https://lore.kernel.org/r/20230713083101.971525-2-quic_ipkumar@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 61 ++++++++++++++++++++++++++++++----- 1 file changed, 53 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 2eadc84fba25..2ba9454ad86e 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -42,6 +43,7 @@ clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; cpu-supply = <&ipq9574_s1>; + #cooling-cells = <2>; }; CPU1: cpu@1 { @@ -54,6 +56,7 @@ clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; cpu-supply = <&ipq9574_s1>; + #cooling-cells = <2>; }; CPU2: cpu@2 { @@ -66,6 +69,7 @@ clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; cpu-supply = <&ipq9574_s1>; + #cooling-cells = <2>; }; CPU3: cpu@3 { @@ -78,6 +82,7 @@ clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; cpu-supply = <&ipq9574_s1>; + #cooling-cells = <2>; }; L2_0: l2-cache { @@ -812,18 +817,28 @@ thermal-sensors = <&tsens 10>; trips { - cpu-critical { + cpu0_crit: cpu-critical { temperature = <120000>; hysteresis = <10000>; type = "critical"; }; - cpu-passive { + cpu0_alert: cpu-passive { temperature = <110000>; hysteresis = <1000>; type = "passive"; }; }; + + cooling-maps { + map0 { + trip = <&cpu0_alert>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu1-thermal { @@ -832,18 +847,28 @@ thermal-sensors = <&tsens 11>; trips { - cpu-critical { + cpu1_crit: cpu-critical { temperature = <120000>; hysteresis = <10000>; type = "critical"; }; - cpu-passive { + cpu1_alert: cpu-passive { temperature = <110000>; hysteresis = <1000>; type = "passive"; }; }; + + cooling-maps { + map0 { + trip = <&cpu1_alert>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu2-thermal { @@ -852,18 +877,28 @@ thermal-sensors = <&tsens 12>; trips { - cpu-critical { + cpu2_crit: cpu-critical { temperature = <120000>; hysteresis = <10000>; type = "critical"; }; - cpu-passive { + cpu2_alert: cpu-passive { temperature = <110000>; hysteresis = <1000>; type = "passive"; }; }; + + cooling-maps { + map0 { + trip = <&cpu2_alert>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu3-thermal { @@ -872,18 +907,28 @@ thermal-sensors = <&tsens 13>; trips { - cpu-critical { + cpu3_crit: cpu-critical { temperature = <120000>; hysteresis = <10000>; type = "critical"; }; - cpu-passive { + cpu3_alert: cpu-passive { temperature = <110000>; hysteresis = <1000>; type = "passive"; }; }; + + cooling-maps { + map0 { + trip = <&cpu3_alert>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; wcss-phyb-thermal { -- cgit v1.2.3-59-g8ed1b From 091efd56330ff17f7fb45ca0c635338ab37e0a35 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Thu, 15 Jun 2023 18:50:43 +0200 Subject: arm64: dts: qcom: Add rpm-proc node for SMD platforms Rather than having the RPM SMD channels as the only child of a dummy SMD node, switch to representing the RPM as remoteproc like all the other remoteprocs (WCNSS, modem DSP). This allows assigning additional subdevices to it like the MPM interrupt-controller or rpm-master-stats. Reviewed-by: Konrad Dybcio Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20230531-rpm-rproc-v3-10-a07dcdefd918@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 6 +- arch/arm64/boot/dts/qcom/msm8939.dtsi | 112 ++++++++++++------------- arch/arm64/boot/dts/qcom/msm8953.dtsi | 136 +++++++++++++++--------------- arch/arm64/boot/dts/qcom/msm8976.dtsi | 152 +++++++++++++++++----------------- arch/arm64/boot/dts/qcom/msm8994.dtsi | 99 +++++++++++----------- 5 files changed, 253 insertions(+), 252 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 7582c7d748fe..c4d673904698 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -282,10 +282,10 @@ }; }; - smd { - compatible = "qcom,smd"; + rpm: remoteproc { + compatible = "qcom,msm8916-rpm-proc", "qcom,rpm-proc"; - rpm { + smd-edge { interrupts = ; qcom,ipc = <&apcs 8 0>; qcom,smd-edge = <15>; diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi index b5936ae00bbd..af6d644a5d38 100644 --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -242,6 +242,62 @@ interrupts = ; }; + rpm: remoteproc { + compatible = "qcom,msm8936-rpm-proc", "qcom,rpm-proc"; + + smd-edge { + interrupts = ; + qcom,ipc = <&apcs1_mbox 8 0>; + qcom,smd-edge = <15>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-msm8936"; + qcom,smd-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-msm8936", "qcom,rpmcc"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board>; + }; + + rpmpd: power-controller { + compatible = "qcom,msm8939-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = <1>; + }; + + rpmpd_opp_svs_krait: opp2 { + opp-level = <2>; + }; + + rpmpd_opp_svs_soc: opp3 { + opp-level = <3>; + }; + + rpmpd_opp_nom: opp4 { + opp-level = <4>; + }; + + rpmpd_opp_turbo: opp5 { + opp-level = <5>; + }; + + rpmpd_opp_super_turbo: opp6 { + opp-level = <6>; + }; + }; + }; + }; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -310,62 +366,6 @@ }; }; - smd { - compatible = "qcom,smd"; - - rpm { - interrupts = ; - qcom,ipc = <&apcs1_mbox 8 0>; - qcom,smd-edge = <15>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-msm8936"; - qcom,smd-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8936", "qcom,rpmcc"; - #clock-cells = <1>; - clock-names = "xo"; - clocks = <&xo_board>; - }; - - rpmpd: power-controller { - compatible = "qcom,msm8939-rpmpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmpd_opp_table>; - - rpmpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmpd_opp_ret: opp1 { - opp-level = <1>; - }; - - rpmpd_opp_svs_krait: opp2 { - opp-level = <2>; - }; - - rpmpd_opp_svs_soc: opp3 { - opp-level = <3>; - }; - - rpmpd_opp_nom: opp4 { - opp-level = <4>; - }; - - rpmpd_opp_turbo: opp5 { - opp-level = <5>; - }; - - rpmpd_opp_super_turbo: opp6 { - opp-level = <6>; - }; - }; - }; - }; - }; - }; - smp2p-hexagon { compatible = "qcom,smp2p"; qcom,smem = <435>, <428>; diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index b711cf9a6dc0..e7de7632669a 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -190,6 +190,74 @@ method = "smc"; }; + rpm: remoteproc { + compatible = "qcom,msm8953-rpm-proc", "qcom,rpm-proc"; + + smd-edge { + interrupts = ; + qcom,ipc = <&apcs 8 0>; + qcom,smd-edge = <15>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-msm8953"; + qcom,smd-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-msm8953", "qcom,rpmcc"; + clocks = <&xo_board>; + clock-names = "xo"; + #clock-cells = <1>; + }; + + rpmpd: power-controller { + compatible = "qcom,msm8953-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmpd_opp_ret_plus: opp2 { + opp-level = ; + }; + + rpmpd_opp_min_svs: opp3 { + opp-level = ; + }; + + rpmpd_opp_low_svs: opp4 { + opp-level = ; + }; + + rpmpd_opp_svs: opp5 { + opp-level = ; + }; + + rpmpd_opp_svs_plus: opp6 { + opp-level = ; + }; + + rpmpd_opp_nom: opp7 { + opp-level = ; + }; + + rpmpd_opp_nom_plus: opp8 { + opp-level = ; + }; + + rpmpd_opp_turbo: opp9 { + opp-level = ; + }; + }; + }; + }; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -263,74 +331,6 @@ }; }; - smd { - compatible = "qcom,smd"; - - rpm { - interrupts = ; - qcom,ipc = <&apcs 8 0>; - qcom,smd-edge = <15>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-msm8953"; - qcom,smd-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8953", "qcom,rpmcc"; - clocks = <&xo_board>; - clock-names = "xo"; - #clock-cells = <1>; - }; - - rpmpd: power-controller { - compatible = "qcom,msm8953-rpmpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmpd_opp_table>; - - rpmpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmpd_opp_ret: opp1 { - opp-level = ; - }; - - rpmpd_opp_ret_plus: opp2 { - opp-level = ; - }; - - rpmpd_opp_min_svs: opp3 { - opp-level = ; - }; - - rpmpd_opp_low_svs: opp4 { - opp-level = ; - }; - - rpmpd_opp_svs: opp5 { - opp-level = ; - }; - - rpmpd_opp_svs_plus: opp6 { - opp-level = ; - }; - - rpmpd_opp_nom: opp7 { - opp-level = ; - }; - - rpmpd_opp_nom_plus: opp8 { - opp-level = ; - }; - - rpmpd_opp_turbo: opp9 { - opp-level = ; - }; - }; - }; - }; - }; - }; - smp2p-adsp { compatible = "qcom,smp2p"; qcom,smem = <443>, <429>; diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index 753b9a2105ed..ab76806317a7 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -232,6 +232,82 @@ method = "smc"; }; + rpm: remoteproc { + compatible = "qcom,msm8976-rpm-proc", "qcom,rpm-proc"; + + smd-edge { + interrupts = ; + qcom,ipc = <&apcs 8 0>; + qcom,smd-edge = <15>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-msm8976"; + qcom,smd-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-msm8976", "qcom,rpmcc"; + clocks = <&xo_board>; + clock-names = "xo"; + #clock-cells = <1>; + }; + + rpmpd: power-controller { + compatible = "qcom,msm8976-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmpd_opp_ret_plus: opp2 { + opp-level = ; + }; + + rpmpd_opp_min_svs: opp3 { + opp-level = ; + }; + + rpmpd_opp_low_svs: opp4 { + opp-level = ; + }; + + rpmpd_opp_svs: opp5 { + opp-level = ; + }; + + rpmpd_opp_svs_plus: opp6 { + opp-level = ; + }; + + rpmpd_opp_nom: opp7 { + opp-level = ; + }; + + rpmpd_opp_nom_plus: opp8 { + opp-level = ; + }; + + rpmpd_opp_turbo: opp9 { + opp-level = ; + }; + + rpmpd_opp_turbo_no_cpr: opp10 { + opp-level = ; + }; + + rpmpd_opp_turbo_high: opp111 { + opp-level = ; + }; + }; + }; + }; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -346,82 +422,6 @@ }; }; - smd { - compatible = "qcom,smd"; - - rpm { - interrupts = ; - qcom,ipc = <&apcs 8 0>; - qcom,smd-edge = <15>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-msm8976"; - qcom,smd-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8976", "qcom,rpmcc"; - clocks = <&xo_board>; - clock-names = "xo"; - #clock-cells = <1>; - }; - - rpmpd: power-controller { - compatible = "qcom,msm8976-rpmpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmpd_opp_table>; - - rpmpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmpd_opp_ret: opp1 { - opp-level = ; - }; - - rpmpd_opp_ret_plus: opp2 { - opp-level = ; - }; - - rpmpd_opp_min_svs: opp3 { - opp-level = ; - }; - - rpmpd_opp_low_svs: opp4 { - opp-level = ; - }; - - rpmpd_opp_svs: opp5 { - opp-level = ; - }; - - rpmpd_opp_svs_plus: opp6 { - opp-level = ; - }; - - rpmpd_opp_nom: opp7 { - opp-level = ; - }; - - rpmpd_opp_nom_plus: opp8 { - opp-level = ; - }; - - rpmpd_opp_turbo: opp9 { - opp-level = ; - }; - - rpmpd_opp_turbo_no_cpr: opp10 { - opp-level = ; - }; - - rpmpd_opp_turbo_high: opp111 { - opp-level = ; - }; - }; - }; - }; - }; - }; - smsm { compatible = "qcom,smsm"; diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 5a7923d7c62a..c374fba5d8f9 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -178,6 +178,56 @@ method = "hvc"; }; + rpm: remoteproc { + compatible = "qcom,msm8994-rpm-proc", "qcom,rpm-proc"; + + smd-edge { + interrupts = ; + qcom,ipc = <&apcs 8 0>; + qcom,smd-edge = <15>; + qcom,remote-pid = <6>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-msm8994"; + qcom,smd-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-msm8994", "qcom,rpmcc"; + #clock-cells = <1>; + }; + + rpmpd: power-controller { + compatible = "qcom,msm8994-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = <1>; + }; + rpmpd_opp_svs_krait: opp2 { + opp-level = <2>; + }; + rpmpd_opp_svs_soc: opp3 { + opp-level = <3>; + }; + rpmpd_opp_nom: opp4 { + opp-level = <4>; + }; + rpmpd_opp_turbo: opp5 { + opp-level = <5>; + }; + rpmpd_opp_super_turbo: opp6 { + opp-level = <6>; + }; + }; + }; + }; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -237,55 +287,6 @@ }; }; - smd { - compatible = "qcom,smd"; - rpm { - interrupts = ; - qcom,ipc = <&apcs 8 0>; - qcom,smd-edge = <15>; - qcom,remote-pid = <6>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-msm8994"; - qcom,smd-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8994", "qcom,rpmcc"; - #clock-cells = <1>; - }; - - rpmpd: power-controller { - compatible = "qcom,msm8994-rpmpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmpd_opp_table>; - - rpmpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmpd_opp_ret: opp1 { - opp-level = <1>; - }; - rpmpd_opp_svs_krait: opp2 { - opp-level = <2>; - }; - rpmpd_opp_svs_soc: opp3 { - opp-level = <3>; - }; - rpmpd_opp_nom: opp4 { - opp-level = <4>; - }; - rpmpd_opp_turbo: opp5 { - opp-level = <5>; - }; - rpmpd_opp_super_turbo: opp6 { - opp-level = <6>; - }; - }; - }; - }; - }; - }; - smem { compatible = "qcom,smem"; memory-region = <&smem_mem>; -- cgit v1.2.3-59-g8ed1b From 7e1acc8b92a3b67db1e5255adae2851d58d74434 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Thu, 15 Jun 2023 18:50:44 +0200 Subject: arm64: dts: qcom: Add rpm-proc node for GLINK gplatforms Rather than having the RPM GLINK channels as the only child of a dummy top-level rpm-glink node, switch to representing the RPM as remoteproc like all the other remoteprocs (modem DSP, ...). This allows assigning additional subdevices to it like the MPM interrupt-controller or rpm-master-stats. Tested-by: Konrad Dybcio # SM6375 Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20230531-rpm-rproc-v3-11-a07dcdefd918@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 48 ++++++----- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 28 ++++--- arch/arm64/boot/dts/qcom/msm8996.dtsi | 113 ++++++++++++------------- arch/arm64/boot/dts/qcom/msm8998.dtsi | 102 ++++++++++++----------- arch/arm64/boot/dts/qcom/qcm2290.dtsi | 126 ++++++++++++++-------------- arch/arm64/boot/dts/qcom/qcs404.dtsi | 152 +++++++++++++++++----------------- arch/arm64/boot/dts/qcom/sdm630.dtsi | 132 +++++++++++++++-------------- arch/arm64/boot/dts/qcom/sm6115.dtsi | 128 ++++++++++++++-------------- arch/arm64/boot/dts/qcom/sm6125.dtsi | 140 ++++++++++++++++--------------- arch/arm64/boot/dts/qcom/sm6375.dtsi | 126 ++++++++++++++-------------- 10 files changed, 566 insertions(+), 529 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 7355f266742a..47b8b1d6730a 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -146,6 +146,32 @@ method = "smc"; }; + rpm: remoteproc { + compatible = "qcom,ipq6018-rpm-proc", "qcom,rpm-proc"; + + glink-edge { + compatible = "qcom,glink-rpm"; + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-ipq6018"; + qcom,glink-channels = "rpm_requests"; + + regulators { + compatible = "qcom,rpm-mp5496-regulators"; + + ipq6018_s2: s2 { + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1062500>; + regulator-always-on; + }; + }; + }; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -182,28 +208,6 @@ }; }; - rpm-glink { - compatible = "qcom,glink-rpm"; - interrupts = ; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - mboxes = <&apcs_glb 0>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-ipq6018"; - qcom,glink-channels = "rpm_requests"; - - regulators { - compatible = "qcom,rpm-mp5496-regulators"; - - ipq6018_s2: s2 { - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1062500>; - regulator-always-on; - }; - }; - }; - }; - smem { compatible = "qcom,smem"; memory-region = <&smem_region>; diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 2ba9454ad86e..a21225007f60 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -156,6 +156,22 @@ method = "smc"; }; + rpm: remoteproc { + compatible = "qcom,ipq9574-rpm-proc", "qcom,rpm-proc"; + + glink-edge { + compatible = "qcom,glink-rpm"; + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-ipq9574"; + qcom,glink-channels = "rpm_requests"; + }; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -184,18 +200,6 @@ }; }; - rpm-glink { - compatible = "qcom,glink-rpm"; - interrupts = ; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - mboxes = <&apcs_glb 0>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-ipq9574"; - qcom,glink-channels = "rpm_requests"; - }; - }; - soc: soc@0 { compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index b5866b111061..440557c8eca4 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -448,6 +448,63 @@ method = "smc"; }; + rpm: remoteproc { + compatible = "qcom,msm8996-rpm-proc", "qcom,rpm-proc"; + + glink-edge { + compatible = "qcom,glink-rpm"; + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-msm8996"; + qcom,glink-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc"; + #clock-cells = <1>; + clocks = <&xo_board>; + clock-names = "xo"; + }; + + rpmpd: power-controller { + compatible = "qcom,msm8996-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp1: opp1 { + opp-level = <1>; + }; + + rpmpd_opp2: opp2 { + opp-level = <2>; + }; + + rpmpd_opp3: opp3 { + opp-level = <3>; + }; + + rpmpd_opp4: opp4 { + opp-level = <4>; + }; + + rpmpd_opp5: opp5 { + opp-level = <5>; + }; + + rpmpd_opp6: opp6 { + opp-level = <6>; + }; + }; + }; + }; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -522,62 +579,6 @@ }; }; - rpm-glink { - compatible = "qcom,glink-rpm"; - - interrupts = ; - - qcom,rpm-msg-ram = <&rpm_msg_ram>; - - mboxes = <&apcs_glb 0>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-msm8996"; - qcom,glink-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc"; - #clock-cells = <1>; - clocks = <&xo_board>; - clock-names = "xo"; - }; - - rpmpd: power-controller { - compatible = "qcom,msm8996-rpmpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmpd_opp_table>; - - rpmpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmpd_opp1: opp1 { - opp-level = <1>; - }; - - rpmpd_opp2: opp2 { - opp-level = <2>; - }; - - rpmpd_opp3: opp3 { - opp-level = <3>; - }; - - rpmpd_opp4: opp4 { - opp-level = <4>; - }; - - rpmpd_opp5: opp5 { - opp-level = <5>; - }; - - rpmpd_opp6: opp6 { - opp-level = <6>; - }; - }; - }; - }; - }; - smem { compatible = "qcom,smem"; memory-region = <&smem_mem>; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 78867cb00875..360fe3edcc08 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -321,70 +321,74 @@ method = "smc"; }; - rpm-glink { - compatible = "qcom,glink-rpm"; + rpm: remoteproc { + compatible = "qcom,msm8998-rpm-proc", "qcom,rpm-proc"; - interrupts = ; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - mboxes = <&apcs_glb 0>; + glink-edge { + compatible = "qcom,glink-rpm"; - rpm_requests: rpm-requests { - compatible = "qcom,rpm-msm8998"; - qcom,glink-channels = "rpm_requests"; + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; - rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc"; - clocks = <&xo>; - clock-names = "xo"; - #clock-cells = <1>; - }; + rpm_requests: rpm-requests { + compatible = "qcom,rpm-msm8998"; + qcom,glink-channels = "rpm_requests"; - rpmpd: power-controller { - compatible = "qcom,msm8998-rpmpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmpd_opp_table>; + rpmcc: clock-controller { + compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc"; + clocks = <&xo>; + clock-names = "xo"; + #clock-cells = <1>; + }; - rpmpd_opp_table: opp-table { - compatible = "operating-points-v2"; + rpmpd: power-controller { + compatible = "qcom,msm8998-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; - rpmpd_opp_ret: opp1 { - opp-level = ; - }; + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; - rpmpd_opp_ret_plus: opp2 { - opp-level = ; - }; + rpmpd_opp_ret: opp1 { + opp-level = ; + }; - rpmpd_opp_min_svs: opp3 { - opp-level = ; - }; + rpmpd_opp_ret_plus: opp2 { + opp-level = ; + }; - rpmpd_opp_low_svs: opp4 { - opp-level = ; - }; + rpmpd_opp_min_svs: opp3 { + opp-level = ; + }; - rpmpd_opp_svs: opp5 { - opp-level = ; - }; + rpmpd_opp_low_svs: opp4 { + opp-level = ; + }; - rpmpd_opp_svs_plus: opp6 { - opp-level = ; - }; + rpmpd_opp_svs: opp5 { + opp-level = ; + }; - rpmpd_opp_nom: opp7 { - opp-level = ; - }; + rpmpd_opp_svs_plus: opp6 { + opp-level = ; + }; - rpmpd_opp_nom_plus: opp8 { - opp-level = ; - }; + rpmpd_opp_nom: opp7 { + opp-level = ; + }; - rpmpd_opp_turbo: opp9 { - opp-level = ; - }; + rpmpd_opp_nom_plus: opp8 { + opp-level = ; + }; + + rpmpd_opp_turbo: opp9 { + opp-level = ; + }; - rpmpd_opp_turbo_plus: opp10 { - opp-level = ; + rpmpd_opp_turbo_plus: opp10 { + opp-level = ; + }; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index cf995eefa11e..d46e591e72b5 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -198,6 +198,71 @@ }; }; + rpm: remoteproc { + compatible = "qcom,qcm2290-rpm-proc", "qcom,rpm-proc"; + + glink-edge { + compatible = "qcom,glink-rpm"; + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-qcm2290"; + qcom,glink-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-qcm2290", "qcom,rpmcc"; + clocks = <&xo_board>; + clock-names = "xo"; + #clock-cells = <1>; + }; + + rpmpd: power-controller { + compatible = "qcom,qcm2290-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_min_svs: opp1 { + opp-level = ; + }; + + rpmpd_opp_low_svs: opp2 { + opp-level = ; + }; + + rpmpd_opp_svs: opp3 { + opp-level = ; + }; + + rpmpd_opp_svs_plus: opp4 { + opp-level = ; + }; + + rpmpd_opp_nom: opp5 { + opp-level = ; + }; + + rpmpd_opp_nom_plus: opp6 { + opp-level = ; + }; + + rpmpd_opp_turbo: opp7 { + opp-level = ; + }; + + rpmpd_opp_turbo_plus: opp8 { + opp-level = ; + }; + }; + }; + }; + }; + }; + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -288,67 +353,6 @@ }; }; - rpm-glink { - compatible = "qcom,glink-rpm"; - interrupts = ; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - mboxes = <&apcs_glb 0>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-qcm2290"; - qcom,glink-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-qcm2290", "qcom,rpmcc"; - clocks = <&xo_board>; - clock-names = "xo"; - #clock-cells = <1>; - }; - - rpmpd: power-controller { - compatible = "qcom,qcm2290-rpmpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmpd_opp_table>; - - rpmpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmpd_opp_min_svs: opp1 { - opp-level = ; - }; - - rpmpd_opp_low_svs: opp2 { - opp-level = ; - }; - - rpmpd_opp_svs: opp3 { - opp-level = ; - }; - - rpmpd_opp_svs_plus: opp4 { - opp-level = ; - }; - - rpmpd_opp_nom: opp5 { - opp-level = ; - }; - - rpmpd_opp_nom_plus: opp6 { - opp-level = ; - }; - - rpmpd_opp_turbo: opp7 { - opp-level = ; - }; - - rpmpd_opp_turbo_plus: opp8 { - opp-level = ; - }; - }; - }; - }; - }; - smp2p-adsp { compatible = "qcom,smp2p"; qcom,smem = <443>, <429>; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index f2568aff14c8..2721f32dfb71 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -166,6 +166,84 @@ method = "smc"; }; + rpm: remoteproc { + compatible = "qcom,qcs404-rpm-proc", "qcom,rpm-proc"; + + glink-edge { + compatible = "qcom,glink-rpm"; + + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-qcs404"; + qcom,glink-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-qcs404", "qcom,rpmcc"; + #clock-cells = <1>; + clocks = <&xo_board>; + clock-names = "xo"; + }; + + rpmpd: power-controller { + compatible = "qcom,qcs404-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = <16>; + }; + + rpmpd_opp_ret_plus: opp2 { + opp-level = <32>; + }; + + rpmpd_opp_min_svs: opp3 { + opp-level = <48>; + }; + + rpmpd_opp_low_svs: opp4 { + opp-level = <64>; + }; + + rpmpd_opp_svs: opp5 { + opp-level = <128>; + }; + + rpmpd_opp_svs_plus: opp6 { + opp-level = <192>; + }; + + rpmpd_opp_nom: opp7 { + opp-level = <256>; + }; + + rpmpd_opp_nom_plus: opp8 { + opp-level = <320>; + }; + + rpmpd_opp_turbo: opp9 { + opp-level = <384>; + }; + + rpmpd_opp_turbo_no_cpr: opp10 { + opp-level = <416>; + }; + + rpmpd_opp_turbo_plus: opp11 { + opp-level = <512>; + }; + }; + }; + }; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -217,80 +295,6 @@ }; }; - rpm-glink { - compatible = "qcom,glink-rpm"; - - interrupts = ; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - mboxes = <&apcs_glb 0>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-qcs404"; - qcom,glink-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-qcs404", "qcom,rpmcc"; - #clock-cells = <1>; - clocks = <&xo_board>; - clock-names = "xo"; - }; - - rpmpd: power-controller { - compatible = "qcom,qcs404-rpmpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmpd_opp_table>; - - rpmpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmpd_opp_ret: opp1 { - opp-level = <16>; - }; - - rpmpd_opp_ret_plus: opp2 { - opp-level = <32>; - }; - - rpmpd_opp_min_svs: opp3 { - opp-level = <48>; - }; - - rpmpd_opp_low_svs: opp4 { - opp-level = <64>; - }; - - rpmpd_opp_svs: opp5 { - opp-level = <128>; - }; - - rpmpd_opp_svs_plus: opp6 { - opp-level = <192>; - }; - - rpmpd_opp_nom: opp7 { - opp-level = <256>; - }; - - rpmpd_opp_nom_plus: opp8 { - opp-level = <320>; - }; - - rpmpd_opp_turbo: opp9 { - opp-level = <384>; - }; - - rpmpd_opp_turbo_no_cpr: opp10 { - opp-level = <416>; - }; - - rpmpd_opp_turbo_plus: opp11 { - opp-level = <512>; - }; - }; - }; - }; - }; - smem { compatible = "qcom,smem"; diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 759b3a5964cc..83afce56a7b0 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -359,6 +359,74 @@ method = "smc"; }; + rpm: remoteproc { + compatible = "qcom,sdm660-rpm-proc", "qcom,rpm-proc"; + + glink-edge { + compatible = "qcom,glink-rpm"; + + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-sdm660"; + qcom,glink-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc"; + #clock-cells = <1>; + }; + + rpmpd: power-controller { + compatible = "qcom,sdm660-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmpd_opp_ret_plus: opp2 { + opp-level = ; + }; + + rpmpd_opp_min_svs: opp3 { + opp-level = ; + }; + + rpmpd_opp_low_svs: opp4 { + opp-level = ; + }; + + rpmpd_opp_svs: opp5 { + opp-level = ; + }; + + rpmpd_opp_svs_plus: opp6 { + opp-level = ; + }; + + rpmpd_opp_nom: opp7 { + opp-level = ; + }; + + rpmpd_opp_nom_plus: opp8 { + opp-level = ; + }; + + rpmpd_opp_turbo: opp9 { + opp-level = ; + }; + }; + }; + }; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -440,70 +508,6 @@ }; }; - rpm-glink { - compatible = "qcom,glink-rpm"; - - interrupts = ; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - mboxes = <&apcs_glb 0>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-sdm660"; - qcom,glink-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc"; - #clock-cells = <1>; - }; - - rpmpd: power-controller { - compatible = "qcom,sdm660-rpmpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmpd_opp_table>; - - rpmpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmpd_opp_ret: opp1 { - opp-level = ; - }; - - rpmpd_opp_ret_plus: opp2 { - opp-level = ; - }; - - rpmpd_opp_min_svs: opp3 { - opp-level = ; - }; - - rpmpd_opp_low_svs: opp4 { - opp-level = ; - }; - - rpmpd_opp_svs: opp5 { - opp-level = ; - }; - - rpmpd_opp_svs_plus: opp6 { - opp-level = ; - }; - - rpmpd_opp_nom: opp7 { - opp-level = ; - }; - - rpmpd_opp_nom_plus: opp8 { - opp-level = ; - }; - - rpmpd_opp_turbo: opp9 { - opp-level = ; - }; - }; - }; - }; - }; - smem: smem { compatible = "qcom,smem"; memory-region = <&smem_region>; diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 9f2c968e3ad7..839c60351240 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -341,6 +341,72 @@ }; }; + rpm: remoteproc { + compatible = "qcom,sm6115-rpm-proc", "qcom,rpm-proc"; + + glink-edge { + compatible = "qcom,glink-rpm"; + + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-sm6115"; + qcom,glink-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc"; + clocks = <&xo_board>; + clock-names = "xo"; + #clock-cells = <1>; + }; + + rpmpd: power-controller { + compatible = "qcom,sm6115-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_min_svs: opp1 { + opp-level = ; + }; + + rpmpd_opp_low_svs: opp2 { + opp-level = ; + }; + + rpmpd_opp_svs: opp3 { + opp-level = ; + }; + + rpmpd_opp_svs_plus: opp4 { + opp-level = ; + }; + + rpmpd_opp_nom: opp5 { + opp-level = ; + }; + + rpmpd_opp_nom_plus: opp6 { + opp-level = ; + }; + + rpmpd_opp_turbo: opp7 { + opp-level = ; + }; + + rpmpd_opp_turbo_plus: opp8 { + opp-level = ; + }; + }; + }; + }; + }; + }; + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -440,68 +506,6 @@ }; }; - rpm-glink { - compatible = "qcom,glink-rpm"; - - interrupts = ; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - mboxes = <&apcs_glb 0>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-sm6115"; - qcom,glink-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc"; - clocks = <&xo_board>; - clock-names = "xo"; - #clock-cells = <1>; - }; - - rpmpd: power-controller { - compatible = "qcom,sm6115-rpmpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmpd_opp_table>; - - rpmpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmpd_opp_min_svs: opp1 { - opp-level = ; - }; - - rpmpd_opp_low_svs: opp2 { - opp-level = ; - }; - - rpmpd_opp_svs: opp3 { - opp-level = ; - }; - - rpmpd_opp_svs_plus: opp4 { - opp-level = ; - }; - - rpmpd_opp_nom: opp5 { - opp-level = ; - }; - - rpmpd_opp_nom_plus: opp6 { - opp-level = ; - }; - - rpmpd_opp_turbo: opp7 { - opp-level = ; - }; - - rpmpd_opp_turbo_plus: opp8 { - opp-level = ; - }; - }; - }; - }; - }; - smp2p-adsp { compatible = "qcom,smp2p"; qcom,smem = <443>, <429>; diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index a596baa6ce3e..d7c1a40617c6 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -181,6 +181,78 @@ method = "smc"; }; + rpm: remoteproc { + compatible = "qcom,sm6125-rpm-proc", "qcom,rpm-proc"; + + glink-edge { + compatible = "qcom,glink-rpm"; + + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-sm6125"; + qcom,glink-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc"; + #clock-cells = <1>; + }; + + rpmpd: power-controller { + compatible = "qcom,sm6125-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmpd_opp_ret_plus: opp2 { + opp-level = ; + }; + + rpmpd_opp_min_svs: opp3 { + opp-level = ; + }; + + rpmpd_opp_low_svs: opp4 { + opp-level = ; + }; + + rpmpd_opp_svs: opp5 { + opp-level = ; + }; + + rpmpd_opp_svs_plus: opp6 { + opp-level = ; + }; + + rpmpd_opp_nom: opp7 { + opp-level = ; + }; + + rpmpd_opp_nom_plus: opp8 { + opp-level = ; + }; + + rpmpd_opp_turbo: opp9 { + opp-level = ; + }; + + rpmpd_opp_turbo_no_cpr: opp10 { + opp-level = ; + }; + }; + }; + }; + }; + }; + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -292,74 +364,6 @@ }; }; - rpm-glink { - compatible = "qcom,glink-rpm"; - - interrupts = ; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - mboxes = <&apcs_glb 0>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-sm6125"; - qcom,glink-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc"; - #clock-cells = <1>; - }; - - rpmpd: power-controller { - compatible = "qcom,sm6125-rpmpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmpd_opp_table>; - - rpmpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmpd_opp_ret: opp1 { - opp-level = ; - }; - - rpmpd_opp_ret_plus: opp2 { - opp-level = ; - }; - - rpmpd_opp_min_svs: opp3 { - opp-level = ; - }; - - rpmpd_opp_low_svs: opp4 { - opp-level = ; - }; - - rpmpd_opp_svs: opp5 { - opp-level = ; - }; - - rpmpd_opp_svs_plus: opp6 { - opp-level = ; - }; - - rpmpd_opp_nom: opp7 { - opp-level = ; - }; - - rpmpd_opp_nom_plus: opp8 { - opp-level = ; - }; - - rpmpd_opp_turbo: opp9 { - opp-level = ; - }; - - rpmpd_opp_turbo_no_cpr: opp10 { - opp-level = ; - }; - }; - }; - }; - }; - smem: smem { compatible = "qcom,smem"; memory-region = <&smem_mem>; diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 927aa59d4a07..e7ff55443da7 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -621,67 +621,71 @@ }; }; - rpm-glink { - compatible = "qcom,glink-rpm"; - interrupts-extended = <&ipcc IPCC_CLIENT_AOP - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-sm6375"; - qcom,glink-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-sm6375", "qcom,rpmcc"; - clocks = <&xo_board_clk>; - clock-names = "xo"; - #clock-cells = <1>; - }; - - rpmpd: power-controller { - compatible = "qcom,sm6375-rpmpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmpd_opp_table>; - - rpmpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmpd_opp_ret: opp1 { - opp-level = ; - }; - - rpmpd_opp_min_svs: opp2 { - opp-level = ; - }; - - rpmpd_opp_low_svs: opp3 { - opp-level = ; - }; - - rpmpd_opp_svs: opp4 { - opp-level = ; - }; - - rpmpd_opp_svs_plus: opp5 { - opp-level = ; - }; - - rpmpd_opp_nom: opp6 { - opp-level = ; - }; - - rpmpd_opp_nom_plus: opp7 { - opp-level = ; - }; - - rpmpd_opp_turbo: opp8 { - opp-level = ; - }; - - rpmpd_opp_turbo_no_cpr: opp9 { - opp-level = ; + rpm: remoteproc { + compatible = "qcom,sm6375-rpm-proc", "qcom,rpm-proc"; + + glink-edge { + compatible = "qcom,glink-rpm"; + interrupts-extended = <&ipcc IPCC_CLIENT_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-sm6375"; + qcom,glink-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-sm6375", "qcom,rpmcc"; + clocks = <&xo_board_clk>; + clock-names = "xo"; + #clock-cells = <1>; + }; + + rpmpd: power-controller { + compatible = "qcom,sm6375-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmpd_opp_min_svs: opp2 { + opp-level = ; + }; + + rpmpd_opp_low_svs: opp3 { + opp-level = ; + }; + + rpmpd_opp_svs: opp4 { + opp-level = ; + }; + + rpmpd_opp_svs_plus: opp5 { + opp-level = ; + }; + + rpmpd_opp_nom: opp6 { + opp-level = ; + }; + + rpmpd_opp_nom_plus: opp7 { + opp-level = ; + }; + + rpmpd_opp_turbo: opp8 { + opp-level = ; + }; + + rpmpd_opp_turbo_no_cpr: opp9 { + opp-level = ; + }; }; }; }; -- cgit v1.2.3-59-g8ed1b From 6b0fd355e9572f4db52880e63e0bc74a2a3bfd84 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 17 Jun 2023 19:15:12 +0200 Subject: arm64: dts: qcom: sdm850-c630: add missing panel supply Panel bindings (boe,nv133fhm-n61) require supply which here actually can be turned on/off via GPIO control: sdm850-lenovo-yoga-c630.dtb: panel: 'power-supply' is a required property Signed-off-by: Krzysztof Kozlowski Tested-by: Caleb Connolly Link: https://lore.kernel.org/r/20230617171512.286795-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index c6914db7dc6d..21048ad4ffeb 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -87,6 +87,25 @@ clock-frequency = <19200000>; }; + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + vlcm_3v3: regulator-vlcm-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vlcm_3v3"; + + vin-supply = <&vph_pwr>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 88 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + backlight: backlight { compatible = "pwm-backlight"; pwms = <&sn65dsi86 1000000>; @@ -419,6 +438,7 @@ panel: panel { compatible = "boe,nv133fhm-n61"; backlight = <&backlight>; + power-supply = <&vlcm_3v3>; port { panel_in_edp: endpoint { -- cgit v1.2.3-59-g8ed1b From 7e1f024ef0d1da456f61d00f01dc3287ede915b3 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 26 Jun 2023 22:00:25 +0200 Subject: arm64: dts: qcom: pm6150l: Add missing short interrupt Add the missing short interrupt. This fixes the schema warning: wled@d800: interrupt-names: ['ovp'] is too short Fixes: fe508ced49dd ("arm64: dts: qcom: pm6150l: Add wled node") Signed-off-by: Konrad Dybcio Reviewed-by: Luca Weiss Link: https://lore.kernel.org/r/20230626-topic-bindingsfixups-v1-3-254ae8642e69@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm6150l.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm6150l.dtsi b/arch/arm64/boot/dts/qcom/pm6150l.dtsi index 6f7aa67501e2..0fdf440596c0 100644 --- a/arch/arm64/boot/dts/qcom/pm6150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150l.dtsi @@ -121,8 +121,9 @@ pm6150l_wled: leds@d800 { compatible = "qcom,pm6150l-wled"; reg = <0xd800>, <0xd900>; - interrupts = <0x5 0xd8 0x1 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "ovp"; + interrupts = <0x5 0xd8 0x1 IRQ_TYPE_EDGE_RISING>, + <0x5 0xd8 0x2 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ovp", "short"; label = "backlight"; status = "disabled"; -- cgit v1.2.3-59-g8ed1b From 9a4ac09db3c7413e334b4abd6b2f6de8930dd781 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 26 Jun 2023 22:00:26 +0200 Subject: arm64: dts: qcom: pm660l: Add missing short interrupt Add the missing short interrupt. This fixes the schema warning: wled@d800: interrupt-names: ['ovp'] is too short Fixes: 7b56a804e58b ("arm64: dts: qcom: pm660l: Add WLED support") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230626-topic-bindingsfixups-v1-4-254ae8642e69@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm660l.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm660l.dtsi b/arch/arm64/boot/dts/qcom/pm660l.dtsi index 87b71b7205b8..6fdbf507c262 100644 --- a/arch/arm64/boot/dts/qcom/pm660l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm660l.dtsi @@ -74,8 +74,9 @@ pm660l_wled: leds@d800 { compatible = "qcom,pm660l-wled"; reg = <0xd800>, <0xd900>; - interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "ovp"; + interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>, + <0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ovp", "short"; label = "backlight"; status = "disabled"; -- cgit v1.2.3-59-g8ed1b From 4d77b639531fd85b84a7079c3369908dfaddf8b2 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 26 Jun 2023 22:00:27 +0200 Subject: arm64: dts: qcom: pmi8950: Add missing OVP interrupt Add the missing OVP interrupt. This fixes the schema warning: wled@d800: interrupt-names: ['short'] is too short Fixes: 0d97fdf380b4 ("arm64: dts: qcom: Add configuration for PMI8950 peripheral") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230626-topic-bindingsfixups-v1-5-254ae8642e69@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pmi8950.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pmi8950.dtsi b/arch/arm64/boot/dts/qcom/pmi8950.dtsi index 4891be3cd68a..c16adca4e93a 100644 --- a/arch/arm64/boot/dts/qcom/pmi8950.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8950.dtsi @@ -87,8 +87,9 @@ pmi8950_wled: leds@d800 { compatible = "qcom,pmi8950-wled"; reg = <0xd800>, <0xd900>; - interrupts = <0x3 0xd8 0x02 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "short"; + interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>, + <0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ovp", "short"; label = "backlight"; status = "disabled"; -- cgit v1.2.3-59-g8ed1b From 8db94432690371b1736e9a2566a9b3d8a73d5a97 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 26 Jun 2023 22:00:28 +0200 Subject: arm64: dts: qcom: pmi8994: Add missing OVP interrupt Add the missing OVP interrupt. This fixes the schema warning: wled@d800: interrupt-names: ['short'] is too short Fixes: 37aa540cbd30 ("arm64: dts: qcom: pmi8994: Add WLED node") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230626-topic-bindingsfixups-v1-6-254ae8642e69@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pmi8994.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pmi8994.dtsi b/arch/arm64/boot/dts/qcom/pmi8994.dtsi index 0192968f4d9b..36d6a1fb553a 100644 --- a/arch/arm64/boot/dts/qcom/pmi8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8994.dtsi @@ -54,8 +54,9 @@ pmi8994_wled: wled@d800 { compatible = "qcom,pmi8994-wled"; reg = <0xd800>, <0xd900>; - interrupts = <3 0xd8 0x02 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "short"; + interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>, + <0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ovp", "short"; qcom,cabc; qcom,external-pfet; status = "disabled"; -- cgit v1.2.3-59-g8ed1b From e4322bb818bbcd36b441de9880fa4ac911a5eb51 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 26 Jun 2023 22:00:29 +0200 Subject: arm64: dts: qcom: sc8180x: Add missing 'cache-unified' to L3 Add the missing property to fix the dt checker warning: qcom/sc8180x-primus.dtb: l3-cache: 'cache-unified' is a required property Fixes: 8575f197b077 ("arm64: dts: qcom: Introduce the SC8180x platform") Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230626-topic-bindingsfixups-v1-7-254ae8642e69@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index a65dfd136ca9..b7397fa3261b 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -64,6 +64,7 @@ L3_0: l3-cache { compatible = "cache"; cache-level = <3>; + cache-unified; }; }; }; -- cgit v1.2.3-59-g8ed1b From 2bc06b7604d214807918dea810b56e0840aa7ba3 Mon Sep 17 00:00:00 2001 From: Caleb Connolly Date: Thu, 29 Jun 2023 22:00:53 +0100 Subject: arm64: dts: qcom: c630: add panel bridge 1p2 regulator The VCC and VCCA supplies of the DSI<->eDP bridge are derived from vreg_l2a_1p2 and controlled by a GPIO on the PMIC. Add the regulator here so Linux can control it. Signed-off-by: Caleb Connolly Link: https://lore.kernel.org/r/20230627-c630-uart-and-1p2-reg-v2-1-496b581935c1@linaro.org Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 21048ad4ffeb..fbe1874f6cec 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -80,6 +80,22 @@ }; }; + sw_edp_1p2: edp-1p2-regulator { + compatible = "regulator-fixed"; + regulator-name = "sw_edp_1p2"; + + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + pinctrl-0 = <&sw_edp_1p2_en>; + pinctrl-names = "default"; + + gpio = <&pm8998_gpios 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vreg_l2a_1p2>; + }; + sn65dsi86_refclk: sn65dsi86-refclk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -406,6 +422,8 @@ enable-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + vcca-supply = <&sw_edp_1p2>; + vcc-supply = <&sw_edp_1p2>; vpll-supply = <&vreg_l14a_1p88>; vccio-supply = <&vreg_l14a_1p88>; @@ -500,6 +518,16 @@ firmware-name = "qcom/sdm850/LENOVO/81JL/qcdsp1v2850.mbn", "qcom/sdm850/LENOVO/81JL/qcdsp2850.mbn"; }; +&pm8998_gpios { + /* This pin is pulled down by a fixed resistor */ + sw_edp_1p2_en: pm8998-gpio9-state { + pins = "gpio9"; + function = "normal"; + bias-disable; + qcom,drive-strength = <0>; + }; +}; + &qup_i2c10_default { drive-strength = <2>; bias-disable; -- cgit v1.2.3-59-g8ed1b From 443042bec49e896705bbfd1969729c9bd69e194f Mon Sep 17 00:00:00 2001 From: Caleb Connolly Date: Thu, 29 Jun 2023 22:00:54 +0100 Subject: arm64: dts: qcom: c630: add debug uart The c630 exposes its debug UART via a connector on the PCB, enable it. Reviewed-by: Konrad Dybcio Signed-off-by: Caleb Connolly Link: https://lore.kernel.org/r/20230627-c630-uart-and-1p2-reg-v2-2-496b581935c1@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index fbe1874f6cec..f483b600722a 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -33,6 +33,7 @@ chassis-type = "convertible"; aliases { + serial0 = &uart9; hsuart0 = &uart6; }; @@ -706,6 +707,10 @@ }; }; +&uart9 { + status = "okay"; +}; + &ufs_mem_hc { status = "okay"; -- cgit v1.2.3-59-g8ed1b From 2c2f83d9c32ea6e58ad30d88f1edfa67165f151b Mon Sep 17 00:00:00 2001 From: Caleb Connolly Date: Thu, 29 Jun 2023 22:00:55 +0100 Subject: arm64: dts: qcom: sdm850-*: fix uart6 aliases This is a follow up on a previous patch[1] fixing the aliases for sdm845 devices, fix them here too. [1]: 4772c03002c3 ("arm64: dts: qcom: sdm845-*: fix uart6 aliases") Reviewed-by: Konrad Dybcio Signed-off-by: Caleb Connolly Link: https://lore.kernel.org/r/20230627-c630-uart-and-1p2-reg-v2-3-496b581935c1@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 2 +- arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index f483b600722a..92a812b5f423 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -34,7 +34,7 @@ aliases { serial0 = &uart9; - hsuart0 = &uart6; + serial1 = &uart6; }; gpio-keys { diff --git a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts index 41f59e32af64..543837316001 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts @@ -56,7 +56,7 @@ }; aliases { - hsuart0 = &uart6; + serial1 = &uart6; }; /* Reserved memory changes */ -- cgit v1.2.3-59-g8ed1b From 37e93c7c99e140584be9cacad598a2c3e274ce99 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 17 Jul 2023 23:00:54 +0200 Subject: arm64: dts: qcom: sc8180x-primus: remove superfluous "input-enable" Pin configuration property "input-enable" was used with the intention to disable the output, but this is done by default by Linux drivers. Since commit c4a48b0df8bf ("dt-bindings: pinctrl: qcom: tlmm should use output-disable, not input-enable") the property is not accepted anymore: sc8180x-primus.dtb: pinctrl@3100000: hall-int-active-state: 'oneOf' conditional failed, one must be fixed: 'bias-disable', 'function', 'input-enable', 'pins' do not match any of the regexes: '-pins$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230717210055.21979-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts index 9b8695b92c48..aaac2da69286 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts @@ -580,7 +580,6 @@ pins = "gpio121"; function = "gpio"; - input-enable; bias-disable; }; @@ -590,7 +589,6 @@ function = "gpio"; bias-pull-up; - intput-enable; }; kp-disable-pins { @@ -639,7 +637,6 @@ function = "gpio"; bias-disable; - input-enable; }; tp-close-n-pins { @@ -647,7 +644,6 @@ function = "gpio"; bias-disable; - input-enable; }; }; @@ -656,7 +652,6 @@ pins = "gpio122"; function = "gpio"; - input-enable; bias-disable; }; -- cgit v1.2.3-59-g8ed1b From 26834b452f40830011294497788bbc82bf1b14af Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 17 Jul 2023 23:00:55 +0200 Subject: arm64: dts: qcom: sm8250-pdx203: add required pin function DT bindings expect function in each pin state in the pin configuration: sm8250-sony-xperia-edo-pdx203.dtb: pinctrl@f100000: cam-pwr-b-state: 'oneOf' conditional failed, one must be fixed: 'function' is a required property Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230717210055.21979-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dts b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dts index f4c4575eb03b..b70bf9261ba9 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dts @@ -366,6 +366,7 @@ cam_pwr_b_cs: cam-pwr-b-state { pins = "gpio69"; + function = "gpio"; drive-strength = <2>; bias-disable; output-low; @@ -373,6 +374,7 @@ cam_pwr_a_cs: cam-pwr-a-state { pins = "gpio71"; + function = "gpio"; drive-strength = <2>; bias-disable; output-low; -- cgit v1.2.3-59-g8ed1b From d52775a696bca996271fee0d49f138c69ceff93d Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Thu, 6 Jul 2023 18:21:28 +0530 Subject: arm64: dts: qcom: qdu1000-idp: Update reserved memory region Add missing reserved regions as described in QDU1000 memory map. Signed-off-by: Komal Bajaj Link: https://lore.kernel.org/r/20230706125129.20969-2-quic_kbajaj@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts index 0496e87ddfd5..5a25cdec969e 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts +++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts @@ -448,6 +448,28 @@ status = "okay"; }; +&reserved_memory { + ecc_meta_data_mem: ecc-meta-data@e0000000 { + reg = <0x0 0xe0000000 0x0 0x20000000>; + no-map; + }; + + harq_buffer_mem: harq-buffer@800000000 { + reg = <0x8 0x0 0x0 0x80000000>; + no-map; + }; + + tenx_sp_buffer_mem: tenx-sp-buffer@880000000 { + reg = <0x8 0x80000000 0x0 0x50000000>; + no-map; + }; + + fapi_buffer_mem: fapi-buffer@8d0000000 { + reg = <0x8 0xd0000000 0x0 0x20000000>; + no-map; + }; +}; + &sdhc { pinctrl-0 = <&sdc_on_state>; pinctrl-1 = <&sdc_off_state>; -- cgit v1.2.3-59-g8ed1b From 3d5a9f6d5350a3a4b7f932939d9eb94a15988e0e Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Thu, 6 Jul 2023 18:21:29 +0530 Subject: arm64: dts: qcom: qru1000-idp: Update reserved memory region Add missing reserved regions as described in QRU1000 memory map. Signed-off-by: Komal Bajaj Link: https://lore.kernel.org/r/20230706125129.20969-3-quic_kbajaj@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qru1000-idp.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qru1000-idp.dts b/arch/arm64/boot/dts/qcom/qru1000-idp.dts index 80dadd2f30a3..2a862c83309e 100644 --- a/arch/arm64/boot/dts/qcom/qru1000-idp.dts +++ b/arch/arm64/boot/dts/qcom/qru1000-idp.dts @@ -448,6 +448,18 @@ status = "okay"; }; +&reserved_memory { + ecc_meta_data_mem: ecc-meta-data@f0000000 { + reg = <0x0 0xf0000000 0x0 0x10000000>; + no-map; + }; + + tenx_sp_mem: tenx-sp-buffer@800000000 { + reg = <0x8 0x0 0x0 0x80000000>; + no-map; + }; +}; + &tlmm { gpio-reserved-ranges = <28 2>; }; -- cgit v1.2.3-59-g8ed1b From 7f31667d29f48e560172468636e5b07af4882026 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Wed, 19 Jul 2023 10:52:41 +0530 Subject: dt-bindings: power: qcom,rpmhpd: Add Generic RPMh PD indexes Add Generic RPMh Power Domain indexes that can be used for all the Qualcomm SoC henceforth. The power domain indexes of these bindings are based on compatibility with current targets like SM8[2345]50 targets. Signed-off-by: Rohit Agarwal Suggested-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/1689744162-9421-2-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Bjorn Andersson --- include/dt-bindings/power/qcom,rpmhpd.h | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 include/dt-bindings/power/qcom,rpmhpd.h diff --git a/include/dt-bindings/power/qcom,rpmhpd.h b/include/dt-bindings/power/qcom,rpmhpd.h new file mode 100644 index 000000000000..7c201a66bc69 --- /dev/null +++ b/include/dt-bindings/power/qcom,rpmhpd.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_POWER_QCOM_RPMHPD_H +#define _DT_BINDINGS_POWER_QCOM_RPMHPD_H + +/* Generic RPMH Power Domain Indexes */ +#define RPMHPD_CX 0 +#define RPMHPD_CX_AO 1 +#define RPMHPD_EBI 2 +#define RPMHPD_GFX 3 +#define RPMHPD_LCX 4 +#define RPMHPD_LMX 5 +#define RPMHPD_MMCX 6 +#define RPMHPD_MMCX_AO 7 +#define RPMHPD_MX 8 +#define RPMHPD_MX_AO 9 +#define RPMHPD_MXC 10 +#define RPMHPD_MXC_AO 11 +#define RPMHPD_MSS 12 +#define RPMHPD_NSP 13 +#define RPMHPD_NSP0 14 +#define RPMHPD_NSP1 15 +#define RPMHPD_QPHY 16 +#define RPMHPD_DDR 17 +#define RPMHPD_XO 18 + +#endif -- cgit v1.2.3-59-g8ed1b From 34e2fd6a686ba4a6893d16dee1602a69d73bc66d Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Thu, 20 Jul 2023 13:39:02 +0530 Subject: arm64: dts: qcom: sm8250: Update the RPMHPD bindings entry Update the RPMHPD bindings entry as per the new generic bindings defined in rpmhpd.h for SM8250 SoC. Signed-off-by: Rohit Agarwal Link: https://lore.kernel.org/r/1689840545-5094-2-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 77 ++++++++++++++++++------------------ 1 file changed, 39 insertions(+), 38 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index c4e4f75e3941..1ffe7b0a03d3 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -1036,7 +1037,7 @@ dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, <&gpi_dma2 1 0 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1068,7 +1069,7 @@ dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, <&gpi_dma2 1 1 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1100,7 +1101,7 @@ dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, <&gpi_dma2 1 2 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1132,7 +1133,7 @@ dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, <&gpi_dma2 1 3 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1147,7 +1148,7 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart17_default>; interrupts = ; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -1177,7 +1178,7 @@ dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, <&gpi_dma2 1 4 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1192,7 +1193,7 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart18_default>; interrupts = ; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -1222,7 +1223,7 @@ dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, <&gpi_dma2 1 5 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1290,7 +1291,7 @@ dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, <&gpi_dma0 1 0 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1322,7 +1323,7 @@ dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, <&gpi_dma0 1 1 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1354,7 +1355,7 @@ dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, <&gpi_dma0 1 2 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1369,7 +1370,7 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart2_default>; interrupts = ; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -1399,7 +1400,7 @@ dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, <&gpi_dma0 1 3 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1431,7 +1432,7 @@ dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, <&gpi_dma0 1 4 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1463,7 +1464,7 @@ dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, <&gpi_dma0 1 5 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1495,7 +1496,7 @@ dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, <&gpi_dma0 1 6 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1510,7 +1511,7 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart6_default>; interrupts = ; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -1540,7 +1541,7 @@ dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, <&gpi_dma0 1 7 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1605,7 +1606,7 @@ dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, <&gpi_dma1 1 0 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1637,7 +1638,7 @@ dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, <&gpi_dma1 1 1 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1669,7 +1670,7 @@ dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, <&gpi_dma1 1 2 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1701,7 +1702,7 @@ dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, <&gpi_dma1 1 3 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1733,7 +1734,7 @@ dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, <&gpi_dma1 1 4 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1748,7 +1749,7 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart12_default>; interrupts = ; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -1778,7 +1779,7 @@ dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, <&gpi_dma1 1 5 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -2747,8 +2748,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd SM8250_LCX>, - <&rpmhpd SM8250_LMX>; + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; power-domain-names = "lcx", "lmx"; memory-region = <&slpi_mem>; @@ -3467,7 +3468,7 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; memory-region = <&cdsp_mem>; @@ -3664,7 +3665,7 @@ iommus = <&apps_smmu 0x4a0 0x0>; qcom,dll-config = <0x0007642c>; qcom,ddr-config = <0x80040868>; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&sdhc2_opp_table>; status = "disabled"; @@ -3962,7 +3963,7 @@ interrupts = ; power-domains = <&videocc MVS0C_GDSC>, <&videocc MVS0_GDSC>, - <&rpmhpd SM8250_MX>; + <&rpmhpd RPMHPD_MX>; power-domain-names = "venus", "vcodec0", "mx"; operating-points-v2 = <&venus_opp_table>; @@ -4023,7 +4024,7 @@ clocks = <&gcc GCC_VIDEO_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>; - power-domains = <&rpmhpd SM8250_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; #clock-cells = <1>; @@ -4303,7 +4304,7 @@ <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; - power-domains = <&rpmhpd SM8250_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; status = "disabled"; #clock-cells = <1>; @@ -4356,7 +4357,7 @@ assigned-clock-rates = <19200000>; operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmhpd SM8250_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; interrupt-parent = <&mdss>; interrupts = <0>; @@ -4431,7 +4432,7 @@ assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; operating-points-v2 = <&dsi_opp_table>; - power-domains = <&rpmhpd SM8250_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; phys = <&mdss_dsi0_phy>; @@ -4523,7 +4524,7 @@ assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; operating-points-v2 = <&dsi_opp_table>; - power-domains = <&rpmhpd SM8250_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; phys = <&mdss_dsi1_phy>; @@ -4574,7 +4575,7 @@ dispcc: clock-controller@af00000 { compatible = "qcom,sm8250-dispcc"; reg = <0 0x0af00000 0 0x10000>; - power-domains = <&rpmhpd SM8250_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&mdss_dsi0_phy 0>, @@ -5540,8 +5541,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd SM8250_LCX>, - <&rpmhpd SM8250_LMX>; + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; power-domain-names = "lcx", "lmx"; memory-region = <&adsp_mem>; -- cgit v1.2.3-59-g8ed1b From fc4cbfbb7fb2ce5ad6c2afa3e529e8f04021d5fc Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Thu, 20 Jul 2023 13:39:03 +0530 Subject: arm64: dts: qcom: sm8350: Update the RPMHPD bindings entry Update the RPMHPD bindings entry as per the new generic bindings defined in rpmhpd.h for SM8350 SoC. Signed-off-by: Rohit Agarwal Link: https://lore.kernel.org/r/1689840545-5094-3-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 75 ++++++++++++++++++------------------ 1 file changed, 38 insertions(+), 37 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index b1f9f447b78b..d34d02aee919 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -745,7 +746,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_120mhz>; dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, <&gpi_dma2 1 0 QCOM_GPI_SPI>; @@ -777,7 +778,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_120mhz>; dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, <&gpi_dma2 1 1 QCOM_GPI_SPI>; @@ -809,7 +810,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, <&gpi_dma2 1 2 QCOM_GPI_SPI>; @@ -841,7 +842,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, <&gpi_dma2 1 3 QCOM_GPI_SPI>; @@ -859,7 +860,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, <&gpi_dma2 1 4 QCOM_GPI_SPI>; @@ -877,7 +878,7 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart18_default>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; status = "disabled"; }; @@ -904,7 +905,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, <&gpi_dma2 1 5 QCOM_GPI_SPI>; @@ -971,7 +972,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, <&gpi_dma0 1 0 QCOM_GPI_SPI>; @@ -1003,7 +1004,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, <&gpi_dma0 1 1 QCOM_GPI_SPI>; @@ -1035,7 +1036,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, <&gpi_dma0 1 2 QCOM_GPI_SPI>; @@ -1053,7 +1054,7 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart3_default_state>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; status = "disabled"; }; @@ -1066,7 +1067,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, <&gpi_dma0 1 3 QCOM_GPI_SPI>; @@ -1098,7 +1099,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, <&gpi_dma0 1 4 QCOM_GPI_SPI>; @@ -1130,7 +1131,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, <&gpi_dma0 1 5 QCOM_GPI_SPI>; @@ -1162,7 +1163,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, <&gpi_dma0 1 6 QCOM_GPI_SPI>; @@ -1180,7 +1181,7 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart6_default>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; status = "disabled"; }; @@ -1207,7 +1208,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, <&gpi_dma0 1 7 QCOM_GPI_SPI>; @@ -1274,7 +1275,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_120mhz>; dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, <&gpi_dma1 1 0 QCOM_GPI_SPI>; @@ -1306,7 +1307,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, <&gpi_dma1 1 1 QCOM_GPI_SPI>; @@ -1338,7 +1339,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, <&gpi_dma1 1 2 QCOM_GPI_SPI>; @@ -1370,7 +1371,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, <&gpi_dma1 1 3 QCOM_GPI_SPI>; @@ -1402,7 +1403,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, <&gpi_dma1 1 4 QCOM_GPI_SPI>; @@ -1434,7 +1435,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; interrupts = ; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, <&gpi_dma1 1 5 QCOM_GPI_SPI>; @@ -2011,8 +2012,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd SM8350_CX>, - <&rpmhpd SM8350_MSS>; + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MSS>; power-domain-names = "cx", "mss"; interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; @@ -2052,8 +2053,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd SM8350_LCX>, - <&rpmhpd SM8350_LMX>; + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; power-domain-names = "lcx", "lmx"; memory-region = <&pil_slpi_mem>; @@ -2122,7 +2123,7 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; interconnect-names = "sdhc-ddr","cpu-sdhc"; iommus = <&apps_smmu 0x4a0 0x0>; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&sdhc2_opp_table>; bus-width = <4>; dma-coherent; @@ -2483,7 +2484,7 @@ assigned-clock-rates = <19200000>; operating-points-v2 = <&dpu_opp_table>; - power-domains = <&rpmhpd SM8350_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; interrupt-parent = <&mdss>; interrupts = <0>; @@ -2546,7 +2547,7 @@ #sound-dai-cells = <0>; operating-points-v2 = <&dp_opp_table>; - power-domains = <&rpmhpd SM8350_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; status = "disabled"; @@ -2614,7 +2615,7 @@ <&mdss_dsi0_phy 1>; operating-points-v2 = <&dsi0_opp_table>; - power-domains = <&rpmhpd SM8350_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; phys = <&mdss_dsi0_phy>; @@ -2712,7 +2713,7 @@ <&mdss_dsi1_phy 1>; operating-points-v2 = <&dsi1_opp_table>; - power-domains = <&rpmhpd SM8350_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; phys = <&mdss_dsi1_phy>; @@ -2803,7 +2804,7 @@ #reset-cells = <1>; #power-domain-cells = <1>; - power-domains = <&rpmhpd SM8350_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; }; pdc: interrupt-controller@b220000 { @@ -3196,8 +3197,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd SM8350_LCX>, - <&rpmhpd SM8350_LMX>; + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; power-domain-names = "lcx", "lmx"; memory-region = <&pil_adsp_mem>; @@ -3432,8 +3433,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd SM8350_CX>, - <&rpmhpd SM8350_MXC>; + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MXC>; power-domain-names = "cx", "mxc"; interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; -- cgit v1.2.3-59-g8ed1b From 8ed9de79680f1d0165e0bf6cc97a91fb08b67115 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Thu, 20 Jul 2023 13:39:04 +0530 Subject: arm64: dts: qcom: sm8450: Update the RPMHPD bindings entry Update the RPMHPD bindings entry as per the new generic bindings defined in rpmhpd.h for SM8450 SoC. Signed-off-by: Rohit Agarwal Link: https://lore.kernel.org/r/1689840545-5094-4-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 37 ++++++++++++++++++------------------ 1 file changed, 19 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 1d003297a497..4bc1c46a5f44 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -1150,7 +1151,7 @@ interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; - power-domains = <&rpmhpd SM8450_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, @@ -1313,7 +1314,7 @@ interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; - power-domains = <&rpmhpd SM8450_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, @@ -2098,8 +2099,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd SM8450_LCX>, - <&rpmhpd SM8450_LMX>; + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; power-domain-names = "lcx", "lmx"; memory-region = <&slpi_mem>; @@ -2373,8 +2374,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd SM8450_LCX>, - <&rpmhpd SM8450_LMX>; + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; power-domain-names = "lcx", "lmx"; memory-region = <&adsp_mem>; @@ -2478,8 +2479,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd SM8450_CX>, - <&rpmhpd SM8450_MXC>; + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MXC>; power-domain-names = "cx", "mxc"; memory-region = <&cdsp_mem>; @@ -2585,8 +2586,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd SM8450_CX>, - <&rpmhpd SM8450_MSS>; + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MSS>; power-domain-names = "cx", "mss"; memory-region = <&mpss_mem>; @@ -2614,7 +2615,7 @@ reg = <0 0x0aaf0000 0 0x10000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_VIDEO_AHB_CLK>; - power-domains = <&rpmhpd SM8450_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; @@ -2706,7 +2707,7 @@ <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; - power-domains = <&rpmhpd SM8450_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; @@ -2772,7 +2773,7 @@ assigned-clock-rates = <19200000>; operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmhpd SM8450_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; interrupt-parent = <&mdss>; interrupts = <0>; @@ -2864,7 +2865,7 @@ #sound-dai-cells = <0>; operating-points-v2 = <&dp_opp_table>; - power-domains = <&rpmhpd SM8450_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; status = "disabled"; @@ -2930,7 +2931,7 @@ assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; operating-points-v2 = <&mdss_dsi_opp_table>; - power-domains = <&rpmhpd SM8450_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; phys = <&mdss_dsi0_phy>; phy-names = "dsi"; @@ -3022,7 +3023,7 @@ assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; operating-points-v2 = <&mdss_dsi_opp_table>; - power-domains = <&rpmhpd SM8450_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; phys = <&mdss_dsi1_phy>; phy-names = "dsi"; @@ -3090,7 +3091,7 @@ <0>, <0>, /* dp3 */ <0>; - power-domains = <&rpmhpd SM8450_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; @@ -4252,7 +4253,7 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; interconnect-names = "sdhc-ddr","cpu-sdhc"; iommus = <&apps_smmu 0x4a0 0x0>; - power-domains = <&rpmhpd SM8450_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&sdhc2_opp_table>; bus-width = <4>; dma-coherent; -- cgit v1.2.3-59-g8ed1b From 1d14bcffb49c9d0d1268804bc9e7817120a9575f Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Thu, 20 Jul 2023 13:39:05 +0530 Subject: arm64: dts: qcom: sm8550: Update the RPMHPD bindings entry Update the RPMHPD bindings entry as per the new generic bindings defined in rpmhpd.h for SM8550 SoC. Signed-off-by: Rohit Agarwal Link: https://lore.kernel.org/r/1689840545-5094-5-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 6e8aba256931..c93ab3724eb4 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -1989,8 +1990,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd SM8550_CX>, - <&rpmhpd SM8550_MSS>; + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MSS>; power-domain-names = "cx", "mss"; interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; @@ -2368,7 +2369,7 @@ iommus = <&apps_smmu 0x540 0>; qcom,dll-config = <0x0007642c>; qcom,ddr-config = <0x80040868>; - power-domains = <&rpmhpd SM8550_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&sdhc2_opp_table>; interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, @@ -2412,7 +2413,7 @@ reg = <0 0x0aaf0000 0 0x10000>; clocks = <&bi_tcxo_div2>, <&gcc GCC_VIDEO_AHB_CLK>; - power-domains = <&rpmhpd SM8550_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; @@ -2471,7 +2472,7 @@ "core", "vsync"; - power-domains = <&rpmhpd SM8550_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; assigned-clock-rates = <19200000>; @@ -2560,7 +2561,7 @@ #sound-dai-cells = <0>; operating-points-v2 = <&dp_opp_table>; - power-domains = <&rpmhpd SM8550_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; status = "disabled"; @@ -2628,7 +2629,7 @@ "iface", "bus"; - power-domains = <&rpmhpd SM8550_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; @@ -2723,7 +2724,7 @@ "iface", "bus"; - power-domains = <&rpmhpd SM8550_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; @@ -2798,7 +2799,7 @@ <0>, <0>, /* dp3 */ <0>; - power-domains = <&rpmhpd SM8550_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; @@ -3933,8 +3934,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd SM8550_LCX>, - <&rpmhpd SM8550_LMX>; + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; power-domain-names = "lcx", "lmx"; interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; @@ -4065,9 +4066,9 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd SM8550_CX>, - <&rpmhpd SM8550_MXC>, - <&rpmhpd SM8550_NSP>; + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_NSP>; power-domain-names = "cx", "mxc", "nsp"; interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; -- cgit v1.2.3-59-g8ed1b From 4b6ea15c0a1122422b44bf6c47a3c22fc8d46777 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 20 Jul 2023 11:10:48 +0530 Subject: arm64: dts: qcom: sdm845: Add missing RPMh power domain to GCC GCC and it's GDSCs are under the RPMh CX power domain. So let's add the missing RPMh power domain to the GCC node. Fixes: 6d4cf750d03a ("arm64: dts: sdm845: Add minimal dts/dtsi files for sdm845 SoC and MTP") Reviewed-by: Konrad Dybcio Co-developed-by: Krzysztof Kozlowski Signed-off-by: Krzysztof Kozlowski Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20230720054100.9940-4-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 02a6ea0b8b2c..9ed74bf72d05 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1207,6 +1207,7 @@ #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + power-domains = <&rpmhpd SDM845_CX>; }; qfprom@784000 { -- cgit v1.2.3-59-g8ed1b From bbbef6e24bc4493602df68b052f6f48d48e3184a Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 20 Jul 2023 11:10:49 +0530 Subject: arm64: dts: qcom: sdm845: Fix the min frequency of "ice_core_clk" Minimum frequency of the "ice_core_clk" should be 75MHz as specified in the downstream vendor devicetree. So fix it! https://git.codelinaro.org/clo/la/kernel/msm-4.9/-/blob/LA.UM.7.3.r1-09300-sdm845.0/arch/arm64/boot/dts/qcom/sdm845.dtsi Fixes: 433f9a57298f ("arm64: dts: sdm845: add Inline Crypto Engine registers and clock") Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20230720054100.9940-5-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 9ed74bf72d05..89520a9fe1e3 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2614,7 +2614,7 @@ <0 0>, <0 0>, <0 0>, - <0 300000000>; + <75000000 300000000>; status = "disabled"; }; -- cgit v1.2.3-59-g8ed1b From 84e2e371f4f911337604e8ba9281e950230d1189 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 20 Jul 2023 11:10:57 +0530 Subject: arm64: dts: qcom: sdm845: Add interconnect paths to UFSHC UFS host controller requires interconnect path configuration for proper working. So let's specify them for SDM845 SoC. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20230720054100.9940-13-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 89520a9fe1e3..055ca80c0075 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2616,6 +2616,10 @@ <0 0>, <75000000 300000000>; + interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mem_noc SLAVE_EBI1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; + interconnect-names = "ufs-ddr", "cpu-ufs"; + status = "disabled"; }; -- cgit v1.2.3-59-g8ed1b From aeea56072cc8cb0af2b35798aa7d72047f4c8ffa Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Thu, 20 Jul 2023 11:10:58 +0530 Subject: arm64: dts: qcom: sm8250: Add interconnect paths to UFSHC UFS host controller requires interconnect path configuration for proper working. So let's specify them for SM8250 SoC. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20230720054100.9940-14-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 1ffe7b0a03d3..f2d68248e2e2 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2208,6 +2208,10 @@ <0 0>, <0 0>; + interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI_CH0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_UFS_MEM_CFG 0>; + interconnect-names = "ufs-ddr", "cpu-ufs"; + status = "disabled"; }; -- cgit v1.2.3-59-g8ed1b From dd29cb5eddfd2d9fbe9a3924ff1519670633d1d0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 19 Jul 2023 21:28:07 +0200 Subject: arm64: dts: qcom: sm8350-hdk: include PMK8350 HDK8350 comes with PMK8350 PMIC, so include relevant DTSI. This also allows to use reboot reason. Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230719192809.434709-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index 939e169b703a..42f6126068df 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -7,6 +7,7 @@ #include #include "sm8350.dtsi" +#include "pmk8350.dtsi" / { model = "Qualcomm Technologies, Inc. SM8350 HDK"; -- cgit v1.2.3-59-g8ed1b From 423f3a7ec72db9f2be02c20e4661e69300ba0a21 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 19 Jul 2023 21:28:08 +0200 Subject: arm64: dts: qcom: sm8350-hdk: add uSD card Add uSD card to HDK8350. Reviewed-by: Konrad Dybcio Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230719192809.434709-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index 42f6126068df..4013d25a7df3 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -468,6 +468,18 @@ status = "okay"; }; +&sdhc_2 { + cd-gpios = <&tlmm 92 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep_state &sdc2_card_det_n>; + vmmc-supply = <&vreg_l9c_2p96>; + vqmmc-supply = <&vreg_l6c_1p8>; + no-sdio; + no-mmc; + status = "okay"; +}; + &slpi { status = "okay"; firmware-name = "qcom/sm8350/slpi.mbn"; @@ -726,6 +738,13 @@ bias-pull-up; }; }; + + sdc2_card_det_n: sd-card-det-n-state { + pins = "gpio92"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; }; &uart2 { -- cgit v1.2.3-59-g8ed1b From 45a6bf1b272ee6b590233984408e0ba2093ac903 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 19 Jul 2023 21:28:09 +0200 Subject: arm64: dts: qcom: sm8350: add APR and LPASS TLMM Add audio-related nodes: the APR in the ADSP (same as on SM8250) and LPASS TLMM pin controller. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230719192809.434709-3-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 85 ++++++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index d34d02aee919..99e587506b56 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -16,7 +16,9 @@ #include #include #include +#include #include +#include #include #include @@ -1811,6 +1813,20 @@ #hwlock-cells = <1>; }; + lpass_tlmm: pinctrl@33c0000 { + compatible = "qcom,sm8350-lpass-lpi-pinctrl"; + reg = <0 0x033c0000 0 0x20000>, + <0 0x03550000 0 0x10000>; + + clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 15>; + }; + gpu: gpu@3d00000 { compatible = "qcom,adreno-660.1", "qcom,adreno"; @@ -3220,6 +3236,75 @@ label = "lpass"; qcom,remote-pid = <2>; + apr { + compatible = "qcom,apr-v2"; + qcom,glink-channels = "apr_audio_svc"; + qcom,domain = ; + #address-cells = <1>; + #size-cells = <0>; + + service@3 { + reg = ; + compatible = "qcom,q6core"; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + }; + + q6afe: service@4 { + compatible = "qcom,q6afe"; + reg = ; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + + q6afedai: dais { + compatible = "qcom,q6afe-dais"; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + }; + + q6afecc: clock-controller { + compatible = "qcom,q6afe-clocks"; + #clock-cells = <2>; + }; + }; + + q6asm: service@7 { + compatible = "qcom,q6asm"; + reg = ; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + + q6asmdai: dais { + compatible = "qcom,q6asm-dais"; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + iommus = <&apps_smmu 0x1801 0x0>; + + dai@0 { + reg = <0>; + }; + + dai@1 { + reg = <1>; + }; + + dai@2 { + reg = <2>; + }; + }; + }; + + q6adm: service@8 { + compatible = "qcom,q6adm"; + reg = ; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + + q6routing: routing { + compatible = "qcom,q6adm-routing"; + #sound-dai-cells = <0>; + }; + }; + }; + fastrpc { compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; -- cgit v1.2.3-59-g8ed1b From 3e9b36783b22327a4c88fe67b48b8fefae868a4a Mon Sep 17 00:00:00 2001 From: "Lin, Meng-Bo" Date: Sun, 16 Jul 2023 19:08:24 +0000 Subject: arm64: dts: qcom: msm8916-samsung-e2015: Add accelerometer E5, E7 and Grand Max have ST LIS2HH12 accelerometer. Add support for it. Signed-off-by: Stephan Gerhold Signed-off-by: Lin, Meng-Bo Link: https://lore.kernel.org/r/20230716190807.7056-1-linmengbo0689@protonmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/msm8916-samsung-e2015-common.dtsi | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi index 0cdd6af7817f..6f65fd4b3ed3 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi @@ -42,10 +42,27 @@ &blsp_i2c2 { /* lis2hh12 accelerometer instead of BMC150 */ - status = "disabled"; - /delete-node/ accelerometer@10; /delete-node/ magnetometer@12; + + accelerometer@1d { + compatible = "st,lis2hh12"; + reg = <0x1d>; + + interrupt-parent = <&tlmm>; + interrupts = <115 IRQ_TYPE_LEVEL_HIGH>; + + vdd-supply = <&pm8916_l5>; + vddio-supply = <&pm8916_l5>; + + st,drdy-int-pin = <1>; + mount-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "1"; + + pinctrl-0 = <&accel_int_default>; + pinctrl-names = "default"; + }; }; ®_motor_vdd { -- cgit v1.2.3-59-g8ed1b From 63c7fe554264ed17716df8eb9150d8e057d4c728 Mon Sep 17 00:00:00 2001 From: "Lin, Meng-Bo" Date: Sat, 15 Jul 2023 21:41:01 +0000 Subject: arm64: dts: qcom: msm8916-samsung-j5-common: Add touchscreen J5 and J5X use an Imagis IST3038C touchscreen that is connected to blsp_i2c5. Add it to the device tree. MFD driver for SM5703 is unavailable at the moment, which is required to power up the touchscreen on J5, so it's disabled on J5 for now. Signed-off-by: Lin, Meng-Bo Link: https://lore.kernel.org/r/20230715214046.14902-1-linmengbo0689@protonmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/msm8916-samsung-j5-common.dtsi | 29 ++++++++++++++++++++++ arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts | 8 ++++++ arch/arm64/boot/dts/qcom/msm8916-samsung-j5x.dts | 26 +++++++++++++++++++ 3 files changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi index f4fd5d72b28b..cb0e4a7faf91 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi @@ -86,6 +86,26 @@ }; }; +&blsp_i2c5 { + status = "okay"; + + touchscreen: touchscreen@50 { + compatible = "imagis,ist3038c"; + reg = <0x50>; + + interrupt-parent = <&tlmm>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + + touchscreen-size-x = <720>; + touchscreen-size-y = <1280>; + + vddio-supply = <&pm8916_l6>; + + pinctrl-0 = <&tsp_int_default>; + pinctrl-names = "default"; + }; +}; + &blsp_uart2 { status = "okay"; }; @@ -162,6 +182,15 @@ sdc2_cd_default: sdc2-cd-default-state { pins = "gpio38"; function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + tsp_int_default: tsp-int-default-state { + pins = "gpio13"; + function = "gpio"; + drive-strength = <2>; bias-disable; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts index 0a32d33e9778..3e1ff5b4d2d7 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts @@ -10,6 +10,14 @@ chassis-type = "handset"; }; +&blsp_i2c5 { + status = "disabled"; +}; + +&touchscreen { + /* FIXME: Missing sm5703-mfd driver to power up vdd-supply */ +}; + &usb_hs_phy { qcom,init-seq = /bits/ 8 <0x1 0x19 0x2 0x0b>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5x.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5x.dts index 7e1326cc13c5..b2fe109723d8 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5x.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5x.dts @@ -8,12 +8,38 @@ model = "Samsung Galaxy J5 (2016)"; compatible = "samsung,j5x", "qcom,msm8916"; chassis-type = "handset"; + + reg_vdd_tsp_a: regulator-vdd-tsp-a { + compatible = "regulator-fixed"; + regulator-name = "vdd_tsp_a"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + gpio = <&tlmm 108 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&tsp_ldo_en_default>; + pinctrl-names = "default"; + }; }; &muic { interrupts = <121 IRQ_TYPE_EDGE_FALLING>; }; +&touchscreen { + vdd-supply = <®_vdd_tsp_a>; +}; + +&tlmm { + tsp_ldo_en_default: tsp-ldo-en-default-state { + pins = "gpio108"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + &muic_int_default { pins = "gpio121"; }; -- cgit v1.2.3-59-g8ed1b From e40266d90545ef11f95832177faedf41eadcc453 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 26 Jun 2023 22:00:23 +0200 Subject: dt-bindings: qcom: Allow SoC names ending in "pro" There are a couple of SoCs whose names end in "pro", with the currently- upstream examples being msm8974pro and msm8996pro. Allow such suffix in SoC-specific compatibles. Fixes: 5aa332c5e7ca ("dt-bindings: qcom: document preferred compatible naming") Signed-off-by: Konrad Dybcio Acked-by: Rob Herring Link: https://lore.kernel.org/r/20230626-topic-bindingsfixups-v1-1-254ae8642e69@linaro.org [bjorn: Changed (pro|) to (pro)?, per Rob's request] Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom-soc.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/qcom-soc.yaml b/Documentation/devicetree/bindings/arm/qcom-soc.yaml index e333ec4a9c5f..97621c92a1ab 100644 --- a/Documentation/devicetree/bindings/arm/qcom-soc.yaml +++ b/Documentation/devicetree/bindings/arm/qcom-soc.yaml @@ -31,7 +31,7 @@ properties: compatible: oneOf: # Preferred naming style for compatibles of SoC components: - - pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+-.*$" + - pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+(pro)?-.*$" - pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$" # Legacy namings - variations of existing patterns/compatibles are OK, -- cgit v1.2.3-59-g8ed1b From 0391cb15439625c12f0630dc1f8b00ea8ee71113 Mon Sep 17 00:00:00 2001 From: "Lin, Meng-Bo" Date: Fri, 23 Jun 2023 10:02:34 +0000 Subject: dt-bindings: qcom: Document msm8939,a7 Document samsung,a7 bindings used in its device tree. Signed-off-by: Lin, Meng-Bo Acked-by: Rob Herring Link: https://lore.kernel.org/r/20230623100220.5284-1-linmengbo0689@protonmail.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 450f616774e0..a6f7ef4f0830 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -186,6 +186,7 @@ properties: - items: - enum: + - samsung,a7 - sony,kanuti-tulip - square,apq8039-t2 - const: qcom,msm8939 -- cgit v1.2.3-59-g8ed1b From 507f9db1e9decaec1b71d320a15c7b1cb95c0848 Mon Sep 17 00:00:00 2001 From: "Lin, Meng-Bo" Date: Fri, 23 Jun 2023 10:02:51 +0000 Subject: arm64: dts: qcom: msm8939-samsung-a7: Add initial dts This dts adds support for Samsung Galaxy A7 smartphone released in 2015. Add a device tree for A7 with initial support for: - GPIO keys - Hall Sensor - SDHCI (internal and external storage) - USB Device Mode - UART (on USB connector via the SM5502 MUIC) - WCNSS (WiFi/BT) - Regulators - Touch key - Accelerometer/Magnetometer - Fuelgauge - NFC - Vibrator - Touchscreen Signed-off-by: Lin, Meng-Bo Link: https://lore.kernel.org/r/20230623100237.5299-1-linmengbo0689@protonmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts | 495 ++++++++++++++++++++++++ 2 files changed, 496 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 337abc4ceb17..23fd31d4bf5a 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -39,6 +39,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-uf896.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-ufi001c.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-yiming-uz801v3.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8939-samsung-a7.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8939-sony-xperia-kanuti-tulip.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8953-motorola-potter.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-daisy.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts b/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts new file mode 100644 index 000000000000..66e56ac59998 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts @@ -0,0 +1,495 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8939-pm8916.dtsi" + +#include +#include +#include + +/ { + model = "Samsung Galaxy A7 (2015)"; + compatible = "samsung,a7", "qcom,msm8939"; + chassis-type = "handset"; + + aliases { + mmc0 = &sdhc_1; /* SDC1 eMMC slot */ + mmc1 = &sdhc_2; /* SDC2 SD card slot */ + serial0 = &blsp_uart2; + }; + + chosen { + stdout-path = "serial0"; + }; + + reserved-memory { + /* Additional memory used by Samsung firmware modifications */ + tz-apps@85500000 { + reg = <0x0 0x85500000 0x0 0xb00000>; + no-map; + }; + }; + + gpio-hall-sensor { + compatible = "gpio-keys"; + + pinctrl-0 = <&gpio_hall_sensor_default>; + pinctrl-names = "default"; + + label = "GPIO Hall Effect Sensor"; + + event-hall-sensor { + label = "Hall Effect Sensor"; + gpios = <&tlmm 52 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + linux,can-disable; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; + + label = "GPIO Buttons"; + + button-volume-up { + label = "Volume Up"; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + button-home { + label = "Home"; + gpios = <&tlmm 109 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + i2c-fg { + compatible = "i2c-gpio"; + sda-gpios = <&tlmm 106 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 105 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + pinctrl-0 = <&fg_i2c_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + battery@35 { + compatible = "richtek,rt5033-battery"; + reg = <0x35>; + + interrupt-parent = <&tlmm>; + interrupts = <121 IRQ_TYPE_EDGE_BOTH>; + + pinctrl-0 = <&fg_alert_default>; + pinctrl-names = "default"; + }; + }; + + i2c-nfc { + compatible = "i2c-gpio"; + sda-gpios = <&tlmm 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + pinctrl-0 = <&nfc_i2c_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + nfc@2b { + compatible = "nxp,pn547", "nxp,nxp-nci-i2c"; + reg = <0x2b>; + + interrupt-parent = <&tlmm>; + interrupts = <21 IRQ_TYPE_EDGE_RISING>; + + enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + firmware-gpios = <&tlmm 49 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&nfc_default>; + pinctrl-names = "default"; + }; + }; + + i2c-sensor { + compatible = "i2c-gpio"; + sda-gpios = <&tlmm 84 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 85 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + pinctrl-0 = <&sensor_i2c_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + accelerometer: accelerometer@10 { + compatible = "bosch,bmc150_accel"; + reg = <0x10>; + interrupt-parent = <&tlmm>; + interrupts = <115 IRQ_TYPE_EDGE_RISING>; + + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l5>; + + pinctrl-0 = <&accel_int_default>; + pinctrl-names = "default"; + + mount-matrix = "-1", "0", "0", + "0", "-1", "0", + "0", "0", "1"; + }; + + magnetometer@12 { + compatible = "bosch,bmc150_magn"; + reg = <0x12>; + + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l5>; + }; + }; + + i2c-tkey { + compatible = "i2c-gpio"; + sda-gpios = <&tlmm 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 17 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + pinctrl-0 = <&tkey_i2c_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + touchkey@20 { + /* Note: Actually an ABOV MCU that implements same interface */ + compatible = "coreriver,tc360-touchkey"; + reg = <0x20>; + + interrupt-parent = <&tlmm>; + interrupts = <20 IRQ_TYPE_EDGE_FALLING>; + + vcc-supply = <®_touch_key>; + vdd-supply = <®_keyled>; + vddio-supply = <&pm8916_l6>; + + linux,keycodes = ; + + pinctrl-0 = <&tkey_default>; + pinctrl-names = "default"; + }; + }; + + pwm_vibrator: pwm-vibrator { + compatible = "clk-pwm"; + #pwm-cells = <2>; + + clocks = <&gcc GCC_GP2_CLK>; + + pinctrl-0 = <&motor_pwm_default>; + pinctrl-names = "default"; + }; + + reg_keyled: regulator-keyled { + compatible = "regulator-fixed"; + regulator-name = "keyled"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + /* NOTE: On some variants e.g. SM-A700FD it's GPIO 91 */ + gpio = <&tlmm 100 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&tkey_led_en_default>; + pinctrl-names = "default"; + }; + + reg_touch_key: regulator-touch-key { + compatible = "regulator-fixed"; + regulator-name = "touch_key"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + gpio = <&tlmm 56 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&tkey_en_default>; + pinctrl-names = "default"; + }; + + reg_tsp_vdd: regulator-tsp-vdd { + compatible = "regulator-fixed"; + regulator-name = "tsp_vdd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&pm8916_s4>; + + gpio = <&tlmm 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <®_tsp_io_en_default>; + pinctrl-names = "default"; + }; + + reg_vdd_tsp: regulator-vdd-tsp { + compatible = "regulator-fixed"; + regulator-name = "vdd_tsp"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 73 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <®_tsp_en_default>; + pinctrl-names = "default"; + }; + + reg_vibrator: regulator-vibrator { + compatible = "regulator-fixed"; + regulator-name = "motor_en"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + gpio = <&tlmm 86 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&motor_en_default>; + pinctrl-names = "default"; + }; + + vibrator { + compatible = "pwm-vibrator"; + + pwms = <&pwm_vibrator 0 100000>; + pwm-names = "enable"; + + vcc-supply = <®_vibrator>; + }; +}; + +&blsp_i2c1 { + status = "okay"; + + muic: extcon@25 { + compatible = "siliconmitus,sm5502-muic"; + reg = <0x25>; + + interrupt-parent = <&tlmm>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&muic_int_default>; + pinctrl-names = "default"; + }; +}; + +&blsp_i2c5 { + status = "okay"; + + touchscreen@24 { + compatible = "cypress,tt21000"; + + reg = <0x24>; + interrupt-parent = <&tlmm>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + + vdd-supply = <®_vdd_tsp>; + vddio-supply = <®_tsp_vdd>; + + pinctrl-0 = <&tsp_int_default>; + pinctrl-names = "default"; + }; +}; + +&blsp_uart2 { + status = "okay"; +}; + +&pm8916_resin { + linux,code = ; + status = "okay"; +}; + +&pm8916_rpm_regulators { + pm8916_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; +}; + +&sdhc_1 { + status = "okay"; +}; + +&sdhc_2 { + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; + pinctrl-names = "default", "sleep"; + + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&usb { + extcon = <&muic>, <&muic>; + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&muic>; +}; + +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3660b"; +}; + +&tlmm { + accel_int_default: accel-int-default-state { + pins = "gpio115"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + fg_alert_default: fg-alert-default-state { + pins = "gpio121"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + fg_i2c_default: fg-i2c-default-state { + pins = "gpio105", "gpio106"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + gpio_hall_sensor_default: gpio-hall-sensor-default-state { + pins = "gpio52"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + gpio_keys_default: gpio-keys-default-state { + pins = "gpio107", "gpio109"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + motor_en_default: motor-en-default-state { + pins = "gpio86"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + motor_pwm_default: motor-pwm-default-state { + pins = "gpio50"; + function = "gcc_gp2_clk_a"; + }; + + muic_int_default: muic-int-default-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + nfc_default: nfc-default-state { + irq-pins { + pins = "gpio21"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + nfc-pins { + pins = "gpio49", "gpio116"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + + nfc_i2c_default: nfc-i2c-default-state { + pins = "gpio0", "gpio1"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + reg_tsp_en_default: reg-tsp-en-default-state { + pins = "gpio73"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + reg_tsp_io_en_default: reg-tsp-io-en-default-state { + pins = "gpio8"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + sensor_i2c_default: sensor-i2c-default-state { + pins = "gpio84", "gpio85"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tkey_default: tkey-default-state { + pins = "gpio20"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tkey_en_default: tkey-en-default-state { + pins = "gpio56"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tkey_i2c_default: tkey-i2c-default-state { + pins = "gpio16", "gpio17"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tkey_led_en_default: tkey-led-en-default-state { + pins = "gpio100"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tsp_int_default: tsp-int-default-state { + pins = "gpio13"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; -- cgit v1.2.3-59-g8ed1b From 5229c1d6a0c7d7d8f51a27833e568909b8707c39 Mon Sep 17 00:00:00 2001 From: Devi Priya Date: Thu, 15 Jun 2023 14:18:41 +0530 Subject: arm64: dts: qcom: ipq9574: Use assigned-clock-rates for QUP I2C core clks Use assigned-clock-rates property for configuring the QUP I2C core clocks to operate at nominal frequency. Signed-off-by: Devi Priya Link: https://lore.kernel.org/r/20230615084841.12375-1-quic_devipriy@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index a21225007f60..51aba071c1eb 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -410,6 +410,8 @@ clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + assigned-clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; + assigned-clock-rates = <50000000>; dmas = <&blsp_dma 14>, <&blsp_dma 15>; dma-names = "tx", "rx"; status = "disabled"; @@ -438,6 +440,8 @@ clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + assigned-clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; + assigned-clock-rates = <50000000>; dmas = <&blsp_dma 16>, <&blsp_dma 17>; dma-names = "tx", "rx"; status = "disabled"; @@ -466,6 +470,8 @@ clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + assigned-clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; + assigned-clock-rates = <50000000>; dmas = <&blsp_dma 18>, <&blsp_dma 19>; dma-names = "tx", "rx"; status = "disabled"; @@ -495,6 +501,8 @@ clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + assigned-clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; + assigned-clock-rates = <50000000>; dmas = <&blsp_dma 20>, <&blsp_dma 21>; dma-names = "tx", "rx"; status = "disabled"; -- cgit v1.2.3-59-g8ed1b From b0246331c51e65c1d7c853bc617904058540d47f Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 12 Jun 2023 15:14:54 -0700 Subject: arm64: dts: qcom: sc8180x: Add USB Type-C of_graph anchors Define anchors for wiring up the USB Type-C graph in the board files. Signed-off-by: Bjorn Andersson Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230612221456.1887533-2-quic_bjorande@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 48 +++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index b7397fa3261b..d4ce72c533f1 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -2465,6 +2465,23 @@ status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_prim_qmpphy_out: endpoint {}; + }; + + port@2 { + reg = <2>; + + usb_prim_qmpphy_dp_in: endpoint {}; + }; + }; + usb_prim_ssphy: usb3-phy@88e9200 { reg = <0 0x088e9200 0 0x200>, <0 0x088e9400 0 0x200>, @@ -2514,6 +2531,23 @@ status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_sec_qmpphy_out: endpoint {}; + }; + + port@2 { + reg = <2>; + + usb_sec_qmpphy_dp_in: endpoint {}; + }; + }; + usb_sec_ssphy: usb3-phy@88e9200 { reg = <0 0x088ee200 0 0x200>, <0 0x088ee400 0 0x200>, @@ -2605,6 +2639,11 @@ snps,dis_enblslpm_quirk; phys = <&usb_prim_hsphy>, <&usb_prim_ssphy>; phy-names = "usb2-phy", "usb3-phy"; + + port { + usb_prim_role_switch: endpoint { + }; + }; }; }; @@ -2657,6 +2696,11 @@ snps,dis_enblslpm_quirk; phys = <&usb_sec_hsphy>, <&usb_sec_ssphy>; phy-names = "usb2-phy", "usb3-phy"; + + port { + usb_sec_role_switch: endpoint { + }; + }; }; }; @@ -2984,6 +3028,8 @@ port@1 { reg = <1>; + mdss_dp0_out: endpoint { + }; }; }; @@ -3058,6 +3104,8 @@ port@1 { reg = <1>; + mdss_dp1_out: endpoint { + }; }; }; -- cgit v1.2.3-59-g8ed1b From ab590fa619b562b43f7c31c60d2725e04c63d961 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 12 Jun 2023 15:14:55 -0700 Subject: arm64: dts: qcom: sc8180x-primus: Wire up USB Type-C Wire up pmic_glink and the various components of USB Type-C to get battery status, orientation switching of SuperSpeed USB, as well as support for external display on the SC8180X Primus reference device. Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230612221456.1887533-3-quic_bjorande@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 196 ++++++++++++++++++++++++++++ 1 file changed, 196 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts index aaac2da69286..834e6f9fb7c8 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts @@ -50,6 +50,84 @@ }; }; + pmic-glink { + compatible = "qcom,sc8180x-pmic-glink", "qcom,pmic-glink"; + + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_con0_hs: endpoint { + remote-endpoint = <&usb_prim_role_switch>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_con0_ss: endpoint { + remote-endpoint = <&usb_prim_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_con0_sbu: endpoint { + remote-endpoint = <&usbprim_sbu_mux>; + }; + }; + }; + }; + + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + + pmic_glink_con1_hs: endpoint { + remote-endpoint = <&usb_sec_role_switch>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_con1_ss: endpoint { + remote-endpoint = <&usb_sec_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_con1_sbu: endpoint { + remote-endpoint = <&usbsec_sbu_mux>; + }; + }; + }; + }; + }; + reserved-memory { rmtfs_mem: rmtfs-region@85500000 { compatible = "qcom,rmtfs-mem"; @@ -143,6 +221,44 @@ vin-supply = <&vph_pwr>; }; + + usbprim-sbu-mux { + compatible = "pericom,pi3usb102", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&usbprim_sbu_default>; + + mode-switch; + orientation-switch; + + port { + usbprim_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_con0_sbu>; + }; + }; + }; + + usbsec-sbu-mux { + compatible = "pericom,pi3usb102", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 188 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 187 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&usbsec_sbu_default>; + + mode-switch; + orientation-switch; + + port { + usbsec_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_con1_sbu>; + }; + }; + }; }; &apps_rsc { @@ -363,6 +479,24 @@ status = "okay"; }; +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + data-lanes = <0 1>; + remote-endpoint = <&usb_prim_qmpphy_dp_in>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + data-lanes = <0 1>; + remote-endpoint = <&usb_sec_qmpphy_dp_in>; +}; + &mdss_edp { data-lanes = <0 1 2 3>; @@ -494,6 +628,8 @@ vdda-phy-supply = <&vreg_l3c_1p2>; vdda-pll-supply = <&vreg_l5e_0p88>; + orientation-switch; + status = "okay"; }; @@ -505,6 +641,18 @@ dr_mode = "host"; }; +&usb_prim_qmpphy_dp_in { + remote-endpoint = <&mdss_dp0_out>; +}; + +&usb_prim_qmpphy_out { + remote-endpoint = <&pmic_glink_con0_ss>; +}; + +&usb_prim_role_switch { + remote-endpoint = <&pmic_glink_con0_hs>; +}; + &usb_sec_hsphy { vdda-pll-supply = <&vreg_l5e_0p88>; vdda18-supply = <&vreg_l12a_1p8>; @@ -517,9 +665,23 @@ vdda-phy-supply = <&vreg_l3c_1p2>; vdda-pll-supply = <&vreg_l5e_0p88>; + orientation-switch; + status = "okay"; }; +&usb_sec_qmpphy_dp_in { + remote-endpoint = <&mdss_dp1_out>; +}; + +&usb_sec_qmpphy_out { + remote-endpoint = <&pmic_glink_con1_ss>; +}; + +&usb_sec_role_switch { + remote-endpoint = <&pmic_glink_con1_hs>; +}; + &usb_sec { status = "okay"; }; @@ -631,6 +793,40 @@ }; }; + usbprim_sbu_default: usbprim-sbu-state { + oe-n-pins { + pins = "gpio152"; + function = "gpio"; + bias-disable; + drive-strength = <16>; + output-high; + }; + + sel-pins { + pins = "gpio100"; + function = "gpio"; + bias-disable; + drive-strength = <16>; + }; + }; + + usbsec_sbu_default: usbsec-sbu-state { + oe-n-pins { + pins = "gpio188"; + function = "gpio"; + bias-disable; + drive-strength = <16>; + output-high; + }; + + sel-pins { + pins = "gpio187"; + function = "gpio"; + bias-disable; + drive-strength = <16>; + }; + }; + tp_int_active_state: tp-int-active-state { tp-int-pins { pins = "gpio24"; -- cgit v1.2.3-59-g8ed1b From 36bd9fad228e62d029380083e037a6632678cd3a Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 12 Jun 2023 15:14:56 -0700 Subject: arm64: dts: qcom: sc8180x-flex5g: Wire up USB Type-C Following the SC8180X Primus reference design, add pmic_glink and USB Type-C wiring for battery manager, external display and orientation switching. Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230612221456.1887533-4-quic_bjorande@quicinc.com Signed-off-by: Bjorn Andersson --- .../arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 196 +++++++++++++++++++++ 1 file changed, 196 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index fca08db89769..abc66613ccaa 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -45,6 +45,84 @@ }; }; + pmic-glink { + compatible = "qcom,sc8180x-pmic-glink", "qcom,pmic-glink"; + + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_con0_hs: endpoint { + remote-endpoint = <&usb_prim_role_switch>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_con0_ss: endpoint { + remote-endpoint = <&usb_prim_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_con0_sbu: endpoint { + remote-endpoint = <&usbprim_sbu_mux>; + }; + }; + }; + }; + + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + + pmic_glink_con1_hs: endpoint { + remote-endpoint = <&usb_sec_role_switch>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_con1_ss: endpoint { + remote-endpoint = <&usb_sec_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_con1_sbu: endpoint { + remote-endpoint = <&usbsec_sbu_mux>; + }; + }; + }; + }; + }; + reserved-memory { rmtfs_mem: rmtfs-region@85500000 { compatible = "qcom,rmtfs-mem"; @@ -100,6 +178,44 @@ vin-supply = <&vph_pwr>; }; + + usbprim-sbu-mux { + compatible = "pericom,pi3usb102", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&usbprim_sbu_default>; + + mode-switch; + orientation-switch; + + port { + usbprim_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_con0_sbu>; + }; + }; + }; + + usbsec-sbu-mux { + compatible = "pericom,pi3usb102", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 188 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 187 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&usbsec_sbu_default>; + + mode-switch; + orientation-switch; + + port { + usbsec_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_con1_sbu>; + }; + }; + }; }; &apps_rsc { @@ -283,6 +399,24 @@ status = "okay"; }; +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + data-lanes = <0 1>; + remote-endpoint = <&usb_prim_qmpphy_dp_in>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + data-lanes = <0 1>; + remote-endpoint = <&usb_sec_qmpphy_dp_in>; +}; + &mdss_edp { data-lanes = <0 1 2 3>; @@ -417,6 +551,8 @@ vdda-phy-supply = <&vreg_l3c_1p2>; vdda-pll-supply = <&vreg_l5e_0p88>; + orientation-switch; + status = "okay"; }; @@ -428,6 +564,18 @@ dr_mode = "host"; }; +&usb_prim_qmpphy_dp_in { + remote-endpoint = <&mdss_dp0_out>; +}; + +&usb_prim_qmpphy_out { + remote-endpoint = <&pmic_glink_con0_ss>; +}; + +&usb_prim_role_switch { + remote-endpoint = <&pmic_glink_con0_hs>; +}; + &usb_sec_hsphy { vdda-pll-supply = <&vreg_l5e_0p88>; vdda18-supply = <&vreg_l12a_1p8>; @@ -440,9 +588,23 @@ vdda-phy-supply = <&vreg_l3c_1p2>; vdda-pll-supply = <&vreg_l5e_0p88>; + orientation-switch; + status = "okay"; }; +&usb_sec_qmpphy_dp_in { + remote-endpoint = <&mdss_dp1_out>; +}; + +&usb_sec_qmpphy_out { + remote-endpoint = <&pmic_glink_con1_ss>; +}; + +&usb_sec_role_switch { + remote-endpoint = <&pmic_glink_con1_hs>; +}; + &usb_sec { status = "okay"; }; @@ -555,6 +717,40 @@ }; }; + usbprim_sbu_default: usbprim-sbu-state { + oe-n-pins { + pins = "gpio152"; + function = "gpio"; + bias-disable; + drive-strength = <16>; + output-high; + }; + + sel-pins { + pins = "gpio100"; + function = "gpio"; + bias-disable; + drive-strength = <16>; + }; + }; + + usbsec_sbu_default: usbsec-sbu-state { + oe-n-pins { + pins = "gpio188"; + function = "gpio"; + bias-disable; + drive-strength = <16>; + output-high; + }; + + sel-pins { + pins = "gpio187"; + function = "gpio"; + bias-disable; + drive-strength = <16>; + }; + }; + uart13_state: uart13-state { cts-pins { pins = "gpio43"; -- cgit v1.2.3-59-g8ed1b From 74cf6675c35ec3034053a69926f4d98e52852eb0 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 12 Jun 2023 15:06:32 -0700 Subject: arm64: dts: qcom: sc8180x: Fix LLCC reg property The LLCC binding and driver was recently corrected to handle the stride varying between platforms. Switch to the new format to ensure accesses are done in the right place. Fixes: 8575f197b077 ("arm64: dts: qcom: Introduce the SC8180x platform") Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230612220632.1885175-1-quic_bjorande@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index d4ce72c533f1..0c72efeee70e 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -2576,8 +2576,11 @@ system-cache-controller@9200000 { compatible = "qcom,sc8180x-llcc"; - reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, + <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, + <0 0x09600000 0 0x50000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; interrupts = ; }; -- cgit v1.2.3-59-g8ed1b From 489f14be0e0a19225ef8575e4a04b0f9ee77ab3e Mon Sep 17 00:00:00 2001 From: Mrinmay Sarkar Date: Fri, 21 Jul 2023 22:54:34 +0530 Subject: arm64: dts: qcom: sa8775p: Add pcie0 and pcie1 nodes Add pcie dtsi nodes for two controllers found on sa8775p platform. Signed-off-by: Mrinmay Sarkar Link: https://lore.kernel.org/r/1689960276-29266-4-git-send-email-quic_msarkar@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 204 +++++++++++++++++++++++++++++++++- 1 file changed, 202 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 59eedfc9c2cb..7b55cb701472 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -481,8 +481,8 @@ <0>, <0>, <0>, - <0>, - <0>, + <&pcie0_phy>, + <&pcie1_phy>, <0>, <0>, <0>; @@ -2357,4 +2357,204 @@ , ; }; + + pcie0: pci@1c00000{ + compatible = "qcom,pcie-sa8775p"; + reg = <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf20>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x4000>, + <0x0 0x40100000 0x0 0x100000>, + <0x0 0x01c03000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <0>; + num-lanes = <2>; + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; + + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, + <0x100 &pcie_smmu 0x0001 0x1>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + power-domains = <&gcc PCIE_0_GDSC>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie0_phy: phy@1c04000 { + compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy"; + reg = <0x0 0x1c04000 0x0 0x2000>; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_PIPEDIV2_CLK>, + <&gcc GCC_PCIE_0_PHY_AUX_CLK>; + + clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", + "pipediv2", "phy_aux"; + + assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "phy"; + + #clock-cells = <0>; + clock-output-names = "pcie_0_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + pcie1: pci@1c10000{ + compatible = "qcom,pcie-sa8775p"; + reg = <0x0 0x01c10000 0x0 0x3000>, + <0x0 0x60000000 0x0 0xf20>, + <0x0 0x60000f20 0x0 0xa8>, + <0x0 0x60001000 0x0 0x4000>, + <0x0 0x60100000 0x0 0x100000>, + <0x0 0x01c13000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <1>; + num-lanes = <4>; + + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; + + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, + <0x100 &pcie_smmu 0x0081 0x1>; + + resets = <&gcc GCC_PCIE_1_BCR>; + reset-names = "pci"; + power-domains = <&gcc PCIE_1_GDSC>; + + phys = <&pcie1_phy>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie1_phy: phy@1c14000 { + compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy"; + reg = <0x0 0x1c14000 0x0 0x4000>; + + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_PIPEDIV2_CLK>, + <&gcc GCC_PCIE_1_PHY_AUX_CLK>; + + clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", + "pipediv2", "phy_aux"; + + assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + resets = <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names = "phy"; + + #clock-cells = <0>; + clock-output-names = "pcie_1_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; }; -- cgit v1.2.3-59-g8ed1b From bf3ee3db23ed2e72ee61141ade9a3964b509a8d4 Mon Sep 17 00:00:00 2001 From: Mrinmay Sarkar Date: Fri, 21 Jul 2023 22:54:35 +0530 Subject: arm64: dts: qcom: sa8775p-ride: enable pcie nodes Enable pcie0, pcie1 nodes and their respective phy's. Signed-off-by: Mrinmay Sarkar Link: https://lore.kernel.org/r/1689960276-29266-5-git-send-email-quic_msarkar@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 80 +++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index b2aa16037707..1cd7707e1eb3 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -552,6 +552,86 @@ bias-pull-down; }; }; + + pcie0_default_state: pcie0-default-state { + perst-pins { + pins = "gpio2"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq-pins { + pins = "gpio1"; + function = "pcie0_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio0"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie1_default_state: pcie1-default-state { + perst-pins { + pins = "gpio4"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq-pins { + pins = "gpio3"; + function = "pcie1_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio5"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + +&pcie0 { + perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default_state>; + + status = "okay"; +}; + +&pcie1 { + perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default_state>; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l1c>; + + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l1c>; + + status = "okay"; }; &uart10 { -- cgit v1.2.3-59-g8ed1b From b019cf7e5fbaa7d25f716cb936a9237b47156f2d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Jul 2023 13:53:30 +0200 Subject: arm64: dts: qcom: msm8953-vince: drop duplicated touschreen parent interrupt Interrupts extended already define a parent interrupt controller: msm8953-xiaomi-vince.dtb: touchscreen@20: Unevaluated properties are not allowed ('interrupts-parent' was unexpected) Fixes: aa17e707e04a ("arm64: dts: qcom: msm8953: Add device tree for Xiaomi Redmi 5 Plus") Cc: Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230720115335.137354-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts index 0956c866d6cb..1a1d3f92a511 100644 --- a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts +++ b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts @@ -132,7 +132,6 @@ touchscreen@20 { reg = <0x20>; compatible = "syna,rmi4-i2c"; - interrupts-parent = <&tlmm>; interrupts-extended = <&tlmm 65 IRQ_TYPE_EDGE_FALLING>; #address-cells = <1>; -- cgit v1.2.3-59-g8ed1b From 21fc24ee9c5943732c9ae538766c9be93d70d936 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Jul 2023 13:53:31 +0200 Subject: arm64: dts: qcom: msm8996-gemini: fix touchscreen VIO supply According to bindings and Linux driver, there is no VDDA but VIO supply. Fixes: 4ac46b3682c5 ("arm64: dts: qcom: msm8996: xiaomi-gemini: Add support for Xiaomi Mi 5") Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230720115335.137354-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts index bdedcf9dff03..d1066edaea47 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts @@ -82,7 +82,7 @@ #size-cells = <0>; interrupt-parent = <&tlmm>; interrupts = <125 IRQ_TYPE_LEVEL_LOW>; - vdda-supply = <&vreg_l6a_1p8>; + vio-supply = <&vreg_l6a_1p8>; vdd-supply = <&vdd_3v2_tp>; reset-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; -- cgit v1.2.3-59-g8ed1b From 5bea22fbe76937d9e03e80b6a7b76fec17e7a4ef Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Jul 2023 13:53:32 +0200 Subject: arm64: dts: qcom: msm8996-sagit: drop unsupported syna,codes Synaptics RMI4 Touchscreen bindings never defined syna,codes property for function 1a. No usage in Linux drivers. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230720115335.137354-3-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts b/arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts index 2444b87fddf7..437b30cc8bdc 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts @@ -213,7 +213,6 @@ rmi4-f1a@1a { reg = <0x1a>; - syna,codes = ; }; }; }; -- cgit v1.2.3-59-g8ed1b From 0304fc1de3d930db83749cca6ccb3a4f89918fc4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Jul 2023 10:34:57 +0200 Subject: arm64: dts: qcom: sc8180x-pmics: add missing qcom,spmi-gpio fallbacks The GPIO children of PMICs should use qcom,spmi-gpio fallback: sc8180x-primus.dtb: pmic@0: gpio@c000:compatible: ['qcom,pmc8180-gpio'] is too short Fixes: d3302290f59e ("arm64: dts: qcom: sc8180x: Add pmics") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Vinod Koul Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230720083500.73554-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi index 4556af6cd103..ef2f8b732833 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi @@ -142,7 +142,7 @@ }; pmc8180_gpios: gpio@c000 { - compatible = "qcom,pmc8180-gpio"; + compatible = "qcom,pmc8180-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; #gpio-cells = <2>; @@ -300,7 +300,7 @@ }; pmc8180c_gpios: gpio@c000 { - compatible = "qcom,pmc8180c-gpio"; + compatible = "qcom,pmc8180c-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; #gpio-cells = <2>; -- cgit v1.2.3-59-g8ed1b From 565951b1202e1984154abaae4567f16f8073fca3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Jul 2023 10:34:58 +0200 Subject: arm64: dts: qcom: sc8180x-pmics: add missing gpio-ranges The GPIO children of PMICs should use gpio-ranges: sc8180x-primus.dtb: pmic@0: gpio@c000: 'gpio-ranges' is a required property Fixes: d3302290f59e ("arm64: dts: qcom: sc8180x: Add pmics") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Vinod Koul Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230720083500.73554-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi index ef2f8b732833..53b283e29407 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi @@ -145,6 +145,7 @@ compatible = "qcom,pmc8180-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pmc8180_gpios 0 0 10>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; @@ -303,6 +304,7 @@ compatible = "qcom,pmc8180c-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pmc8180c_gpios 0 0 12>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; -- cgit v1.2.3-59-g8ed1b From bf520227bd32381c587fa36271475e035daab3d7 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Jul 2023 10:34:59 +0200 Subject: arm64: dts: qcom: sc8180x-pmics: align SPMI PMIC Power-on node name with dtschema Bindings expect the Power-on node name to be "pon": sc8180x-lenovo-flex-5g.dtb: pmic@0: 'power-on@800' does not match any of the regexes: Fixes: d3302290f59e ("arm64: dts: qcom: sc8180x: Add pmics") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Vinod Koul Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230720083500.73554-3-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi index 53b283e29407..bc17d22dbefc 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi @@ -74,7 +74,7 @@ #address-cells = <1>; #size-cells = <0>; - pon: power-on@800 { + pon: pon@800 { compatible = "qcom,pm8916-pon"; reg = <0x0800>; pwrkey { @@ -247,7 +247,7 @@ #address-cells = <1>; #size-cells = <0>; - power-on@800 { + pon@800 { compatible = "qcom,pm8916-pon"; reg = <0x0800>; -- cgit v1.2.3-59-g8ed1b From 4af302a7e29e70bd930e80ab8f967da48a99a31a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 20 Jul 2023 10:35:00 +0200 Subject: arm64: dts: qcom: sc8180x-pmics: align LPG node name with dtschema Bindings expect the LPG node name to be "pwm": sc8180x-lenovo-flex-5g.dtb: pmic@5: 'lpg' does not match any of the regexes: Fixes: d3302290f59e ("arm64: dts: qcom: sc8180x: Add pmics") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Vinod Koul Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230720083500.73554-4-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi index bc17d22dbefc..ddc84282f142 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi @@ -315,7 +315,7 @@ compatible = "qcom,pmc8180c", "qcom,spmi-pmic"; reg = <0x5 SPMI_USID>; - pmc8180c_lpg: lpg { + pmc8180c_lpg: pwm { compatible = "qcom,pmc8180c-lpg"; #address-cells = <1>; -- cgit v1.2.3-59-g8ed1b From f648504139a6f91224276ab77be684ba3da649d2 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Mon, 24 Jul 2023 12:39:13 +0200 Subject: arm64: dts: qcom: Replace deprecated extcon-usb-gpio id-gpio/vbus-gpio properties Use id-gpios and vbus-gpios instead. Signed-off-by: Alexander Stein Reviewed-by: AngeloGioacchino Del Regno Acked-by: Shawn Guo Acked-by: Krzysztof Kozlowski Acked-by: Heiko Stuebner #rockchip Link: https://lore.kernel.org/r/20230724103914.1779027-7-alexander.stein@ew.tq-group.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 2 +- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 4 ++-- arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts | 2 +- arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts | 2 +- arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts | 2 +- arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts | 2 +- arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts | 2 +- arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts | 2 +- arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts | 2 +- arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-dora.dts | 2 +- arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts | 2 +- arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts | 2 +- arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts | 2 +- arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts | 2 +- arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi | 2 +- 19 files changed, 21 insertions(+), 21 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index e0993e32ee38..f6eeb2598846 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -77,7 +77,7 @@ usb_id: usb-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&tlmm 121 GPIO_ACTIVE_HIGH>; + id-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb_id_default>; }; diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index 16353e3b7fab..385b178314db 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -99,14 +99,14 @@ usb2_id: usb2-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pmi8994_gpios 6 GPIO_ACTIVE_HIGH>; + id-gpios = <&pmi8994_gpios 6 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb2_vbus_det_gpio>; }; usb3_id: usb3-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pm8994_gpios 22 GPIO_ACTIVE_HIGH>; + id-gpios = <&pm8994_gpios 22 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb3_vbus_det_gpio>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts b/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts index 5ad49fe999db..84723c9b73b4 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts @@ -48,7 +48,7 @@ usb_id: usb-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&tlmm 110 GPIO_ACTIVE_HIGH>; + id-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb_id_default>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts index 1c43f3d6a0b4..47da738661bf 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts @@ -52,7 +52,7 @@ usb_id: usb-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&tlmm 69 GPIO_ACTIVE_HIGH>; + id-gpios = <&tlmm 69 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb_id_default>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts index f4dbc515c47a..4aeeee24cedc 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts @@ -75,7 +75,7 @@ usb_id: usb-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&tlmm 110 GPIO_ACTIVE_HIGH>; + id-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; pinctrl-0 = <&usb_id_default>; pinctrl-names = "default"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts index 4239c8fda11b..484e488a5eca 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts @@ -80,7 +80,7 @@ usb_id: usb-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&tlmm 117 GPIO_ACTIVE_HIGH>; + id-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb_id_default>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts index 9757182fba3e..d73294af1a06 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts @@ -68,7 +68,7 @@ usb_id: usb-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&tlmm 110 GPIO_ACTIVE_HIGH>; + id-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb_id_default>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts index c94d36b38651..8e238976ab1c 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts @@ -56,7 +56,7 @@ usb_id: usb-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&tlmm 110 GPIO_ACTIVE_HIGH>; + id-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb_id_default>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts b/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts index 0633e3006f17..89b6aebba404 100644 --- a/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts +++ b/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts @@ -33,7 +33,7 @@ usb_id: usb-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&tlmm 110 GPIO_ACTIVE_HIGH>; + id-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; pinctrl-0 = <&usb_id_default>; pinctrl-names = "default"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-dora.dts b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-dora.dts index 4a0645db0ae1..6374c5f53d9a 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-dora.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-dora.dts @@ -24,5 +24,5 @@ }; &usb3_id { - id-gpio = <&tlmm 24 GPIO_ACTIVE_LOW>; + id-gpios = <&tlmm 24 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi index b4b770a9277d..d55e4075040f 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi @@ -71,7 +71,7 @@ usb3_id: usb3-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&tlmm 25 GPIO_ACTIVE_LOW>; + id-gpios = <&tlmm 25 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&usb_detect>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts index b35e2d9f428c..b6a214bea70f 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts @@ -31,7 +31,7 @@ */ extcon_usb: extcon-usb { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&tlmm 38 GPIO_ACTIVE_HIGH>; + id-gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>; }; gpio-hall-sensors { diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index 687e96068cb2..876c6921ddf0 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -89,8 +89,8 @@ extcon_usb: extcon-usb { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&tlmm 38 GPIO_ACTIVE_HIGH>; - vbus-gpio = <&tlmm 128 GPIO_ACTIVE_HIGH>; + id-gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>; + vbus-gpios = <&tlmm 128 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&cc_dir_default &usb_detect_en>; }; diff --git a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts index 0b23d5bb3f26..2ed39d402d3f 100644 --- a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts +++ b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts @@ -43,7 +43,7 @@ */ extcon_usb: extcon-usb { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&tlmm 58 GPIO_ACTIVE_HIGH>; + id-gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>; }; hdmi-out { diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi index 3033723fc6ff..87d0293c728d 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi @@ -150,7 +150,7 @@ */ extcon_usb: extcon-usb { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&tlmm 58 GPIO_ACTIVE_HIGH>; + id-gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index 8fb2d1788742..3c47410ba94c 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -85,7 +85,7 @@ */ extcon_usb: extcon-usb { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&tlmm 58 GPIO_ACTIVE_HIGH>; + id-gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts index de85086c65ad..e42a4e710cd2 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts +++ b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts @@ -42,7 +42,7 @@ extcon_usb: extcon-usb { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>; + id-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; }; gpio-keys { diff --git a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts index 7c58d1299a60..272bc85f1719 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts +++ b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts @@ -63,7 +63,7 @@ extcon_usb: usb-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>; + id-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; }; gpio-keys { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi index aa3e21bd6c8f..20e3f41efe97 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi @@ -27,7 +27,7 @@ extcon_usb3: extcon-usb3 { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + id-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb3_id>; }; -- cgit v1.2.3-59-g8ed1b From ee0e92b8e7b5894daf5c94e6433a1989f7233fbe Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Sun, 23 Jul 2023 12:54:41 +0200 Subject: arm64: dts: qcom: msm8939-samsung-a7: Drop internal pull for SD CD A7 seems to have external pull-up for the SD card chip detect (like most MSM8916/MSM8939 devices) so drop the internal pull-up. It's not necessary. Tested-by: "Lin, Meng-Bo" Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20230723-a7sdc2cdnopull-v1-1-699fd730afcb@gerhold.net Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts b/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts index 66e56ac59998..ba652909d162 100644 --- a/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts +++ b/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts @@ -448,7 +448,7 @@ pins = "gpio38"; function = "gpio"; drive-strength = <2>; - bias-pull-up; + bias-disable; }; sensor_i2c_default: sensor-i2c-default-state { -- cgit v1.2.3-59-g8ed1b From f9568d22ce06192a7e14bda3a29dc216659554ff Mon Sep 17 00:00:00 2001 From: Zeyan Li Date: Thu, 27 Jul 2023 10:53:21 +0800 Subject: arm64: dts: qcom: sm8150: Fix the I2C7 interrupt I2C6 and I2C7 use the same interrupts, which is incorrect. In the downstream kernel, I2C7 has interrupts of 608 instead of 607. Fixes: 81bee6953b58 ("arm64: dts: qcom: sm8150: add i2c nodes") Signed-off-by: Zeyan Li Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/SY7P282MB378712225CBCEA95FE71554DB201A@SY7P282MB3787.AUSP282.PROD.OUTLOOK.COM Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 1ceadd6e0d67..86608f01c4bc 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1231,7 +1231,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c7_default>; - interrupts = ; + interrupts = ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; -- cgit v1.2.3-59-g8ed1b From 243f1a6d3df947874827a9a8837145621cbef7d3 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 19 Jun 2023 10:07:16 +0200 Subject: arm64: dts: qcom: sm8550: add ports subnodes in usb/dp qmpphy node Add the USB3+DP Combo QMP PHY port subnodes in the SM8550 SoC DTSI to avoid duplication in the devices DTs. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20230601-topic-sm8550-upstream-type-c-v5-4-9221cd300903@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index c93ab3724eb4..d115960bdeec 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2839,6 +2839,32 @@ #phy-cells = <1>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_dp_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_dp_qmpphy_usb_ss_in: endpoint { + }; + }; + + port@2 { + reg = <2>; + + usb_dp_qmpphy_dp_in: endpoint { + }; + }; + }; }; usb_1: usb@a6f8800 { -- cgit v1.2.3-59-g8ed1b From 7a69845b3a08eb28dacbef35f47d979e4908e21f Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 19 Jun 2023 10:07:17 +0200 Subject: arm64: dts: qcom: sm8550-mtp: add pmic glink port/endpoints Add nodes to support Type-C USB/DP functionality. Signed-off-by: Neil Armstrong Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230601-topic-sm8550-upstream-type-c-v5-5-9221cd300903@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 59 +++++++++++++++++++++++++++++++-- 1 file changed, 57 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 00c7e1704a8c..39a43db26ea1 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -81,7 +81,15 @@ reg = <1>; pmic_glink_ss_in: endpoint { - remote-endpoint = <&usb_1_dwc3_ss>; + remote-endpoint = <&usb_dp_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu: endpoint { + remote-endpoint = <&fsa4480_sbu_mux>; }; }; }; @@ -501,6 +509,30 @@ }; }; +&i2c_master_hub_0 { + status = "okay"; +}; + +&i2c_hub_2 { + status = "okay"; + + typec-mux@42 { + compatible = "fcs,fsa4480"; + reg = <0x42>; + + vcc-supply = <&vreg_bob1>; + + mode-switch; + orientation-switch; + + port { + fsa4480_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_sbu>; + }; + }; + }; +}; + &lpass_tlmm { spkr_1_sd_n_active: spkr-1-sd-n-active-state { pins = "gpio17"; @@ -559,6 +591,15 @@ status = "okay"; }; +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + data-lanes = <0 1>; + remote-endpoint = <&usb_dp_qmpphy_dp_in>; +}; + &pcie_1_phy_aux_clk { clock-frequency = <1000>; }; @@ -782,7 +823,7 @@ }; &usb_1_dwc3_ss { - remote-endpoint = <&pmic_glink_ss_in>; + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; }; &usb_1_hsphy { @@ -798,9 +839,23 @@ vdda-phy-supply = <&vreg_l3e_1p2>; vdda-pll-supply = <&vreg_l3f_0p91>; + orientation-switch; + status = "okay"; }; +&usb_dp_qmpphy_dp_in { + remote-endpoint = <&mdss_dp0_out>; +}; + +&usb_dp_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&usb_dp_qmpphy_usb_ss_in { + remote-endpoint = <&usb_1_dwc3_ss>; +}; + &xo_board { clock-frequency = <76800000>; }; -- cgit v1.2.3-59-g8ed1b From fd42c8ec68905bfd093ce08ecf893d995d8f1478 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 19 Jun 2023 10:07:18 +0200 Subject: arm64: dts: qcom: sm8550-qrd: add pmic glink port/endpoints Add nodes to support Type-C USB/DP functionality. On this platform, a Type-C redriver is added to the SuperSpeed graph. Signed-off-by: Neil Armstrong Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230601-topic-sm8550-upstream-type-c-v5-6-9221cd300903@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 91 ++++++++++++++++++++++++++++++++- 1 file changed, 89 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index 3bf4121e36ce..2c09ce8aeafd 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -98,7 +98,15 @@ reg = <1>; pmic_glink_ss_in: endpoint { - remote-endpoint = <&usb_1_dwc3_ss>; + remote-endpoint = <&redriver_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu: endpoint { + remote-endpoint = <&fsa4480_sbu_mux>; }; }; }; @@ -518,6 +526,62 @@ }; }; +&i2c_master_hub_0 { + status = "okay"; +}; + +&i2c_hub_2 { + status = "okay"; + + typec-retimer@1c { + compatible = "onnn,nb7vpq904m"; + reg = <0x1c>; + + vcc-supply = <&vreg_l15b_1p8>; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + redriver_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + redriver_ss_in: endpoint { + data-lanes = <3 2 1 0>; + remote-endpoint = <&usb_dp_qmpphy_out>; + }; + }; + }; + }; + + typec-mux@42 { + compatible = "fcs,fsa4480"; + reg = <0x42>; + + vcc-supply = <&vreg_bob1>; + + mode-switch; + orientation-switch; + + port { + fsa4480_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_sbu>; + }; + }; + }; +}; + &gcc { clocks = <&bi_tcxo_div2>, <&sleep_clk>, <&pcie0_phy>, @@ -587,6 +651,15 @@ status = "okay"; }; +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + data-lanes = <0 1>; + remote-endpoint = <&usb_dp_qmpphy_dp_in>; +}; + &pcie_1_phy_aux_clk { status = "disabled"; }; @@ -843,7 +916,7 @@ }; &usb_1_dwc3_ss { - remote-endpoint = <&pmic_glink_ss_in>; + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; }; &usb_1_hsphy { @@ -859,9 +932,23 @@ vdda-phy-supply = <&vreg_l3e_1p2>; vdda-pll-supply = <&vreg_l3f_0p88>; + orientation-switch; + status = "okay"; }; +&usb_dp_qmpphy_dp_in { + remote-endpoint = <&mdss_dp0_out>; +}; + +&usb_dp_qmpphy_out { + remote-endpoint = <&redriver_ss_in>; +}; + +&usb_dp_qmpphy_usb_ss_in { + remote-endpoint = <&usb_1_dwc3_ss>; +}; + &xo_board { clock-frequency = <76800000>; }; -- cgit v1.2.3-59-g8ed1b From 2b1fd18fe5f9382409d4c881d28bca9693f361a1 Mon Sep 17 00:00:00 2001 From: Tengfei Fan Date: Mon, 31 Jul 2023 16:00:39 +0800 Subject: dt-bindings: arm: qcom: Document SM4450 SoC and boards Document the SM4450 SoC binding and also the boards using it. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Tengfei Fan Link: https://lore.kernel.org/r/20230731080043.38552-3-quic_tengfan@quicinc.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index a6f7ef4f0830..b1f2f015c127 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -72,6 +72,7 @@ description: | sdx65 sdx75 sm4250 + sm4450 sm6115 sm6115p sm6125 @@ -903,6 +904,11 @@ properties: - const: qcom,qrb4210 - const: qcom,sm4250 + - items: + - enum: + - qcom,sm4450-qrd + - const: qcom,sm4450 + - items: - enum: - fxtec,pro1x -- cgit v1.2.3-59-g8ed1b From 7a1fd03e7410a8413e6140d967d66c624ddec690 Mon Sep 17 00:00:00 2001 From: Tengfei Fan Date: Mon, 31 Jul 2023 16:00:40 +0800 Subject: arm64: dts: qcom: Adds base SM4450 DTSI Add based DTSI for SM4450 SoC and includes base description of CPUs and interrupt-controller which helps to boot to shell with dcc console on boards with this SoC. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Tengfei Fan Link: https://lore.kernel.org/r/20230731080043.38552-4-quic_tengfan@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm4450.dtsi | 431 +++++++++++++++++++++++++++++++++++ 1 file changed, 431 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm4450.dtsi diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi new file mode 100644 index 000000000000..c4e5b33f5169 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi @@ -0,0 +1,431 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks{ + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <76800000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + #cooling-cells = <2>; + + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + + L3_0: l3-cache { + compatible = "cache"; + cache-level = <3>; + cache-unified; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_100>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + #cooling-cells = <2>; + + L2_100: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&L2_200>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + #cooling-cells = <2>; + + L2_200: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&L2_300>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + #cooling-cells = <2>; + + L2_300: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x400>; + enable-method = "psci"; + next-level-cache = <&L2_400>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + #cooling-cells = <2>; + + L2_400: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x500>; + enable-method = "psci"; + next-level-cache = <&L2_500>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + #cooling-cells = <2>; + + L2_500: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x0 0x600>; + enable-method = "psci"; + next-level-cache = <&L2_600>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + #cooling-cells = <2>; + + L2_600: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x0 0x700>; + enable-method = "psci"; + next-level-cache = <&L2_700>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + #cooling-cells = <2>; + + L2_700: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + + core6 { + cpu = <&CPU6>; + }; + + core7 { + cpu = <&CPU7>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <800>; + exit-latency-us = <750>; + min-residency-us = <4090>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <600>; + exit-latency-us = <1550>; + min-residency-us = <4791>; + local-timer-stop; + }; + }; + + domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <1050>; + exit-latency-us = <2500>; + min-residency-us = <5309>; + }; + + CLUSTER_SLEEP_1: cluster-sleep-1 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41003344>; + entry-latency-us = <1561>; + exit-latency-us = <2801>; + min-residency-us = <8550>; + }; + }; + }; + + memory@a0000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0xa0000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD4: power-domain-cpu4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD5: power-domain-cpu5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD6: power-domain-cpu6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD7: power-domain-cpu7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CLUSTER_PD: power-domain-cpu-cluster0 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; + }; + }; + + soc: soc@0 { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + compatible = "simple-bus"; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01f40000 0x0 0x40000>; + #hwlock-cells = <1>; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sm4450-pdc", "qcom,pdc"; + reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; + qcom,pdc-ranges = <0 480 94>, <94 494 31>, + <125 63 1>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + intc: interrupt-controller@17200000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */ + <0x0 0x17260000 0x0 0x100000>; /* GICR * 8 */ + interrupts = ; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + }; + + timer@17420000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x17420000 0x0 0x1000>; + ranges = <0 0 0 0x20000000>; + #address-cells = <1>; + #size-cells = <1>; + + frame@17421000 { + reg = <0x17421000 0x1000>, + <0x17422000 0x1000>; + frame-number = <0>; + interrupts = , + ; + }; + + frame@17423000 { + reg = <0x17423000 0x1000>; + frame-number = <1>; + interrupts = ; + status = "disabled"; + }; + + frame@17425000 { + reg = <0x17425000 0x1000>; + frame-number = <2>; + interrupts = ; + status = "disabled"; + }; + + frame@17427000 { + reg = <0x17427000 0x1000>; + frame-number = <3>; + interrupts = ; + status = "disabled"; + }; + + frame@17429000 { + reg = <0x17429000 0x1000>; + frame-number = <4>; + interrupts = ; + status = "disabled"; + }; + + frame@1742b000 { + reg = <0x1742b000 0x1000>; + frame-number = <5>; + interrupts = ; + status = "disabled"; + }; + + frame@1742d000 { + reg = <0x1742d000 0x1000>; + frame-number = <6>; + interrupts = ; + status = "disabled"; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; -- cgit v1.2.3-59-g8ed1b From a5de9bc61181cd65df0170ba8c855b6be650c1e8 Mon Sep 17 00:00:00 2001 From: Tengfei Fan Date: Mon, 31 Jul 2023 16:00:41 +0800 Subject: arm64: dts: qcom: Add base SM4450 QRD DTS Add DTS for Qualcomm QRD platform which uses SM4450 SoC. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Tengfei Fan Link: https://lore.kernel.org/r/20230731080043.38552-5-quic_tengfan@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sm4450-qrd.dts | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm4450-qrd.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 23fd31d4bf5a..f15548dbfa56 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -187,6 +187,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb dtb-$(CONFIG_ARCH_QCOM) += sdx75-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm4450-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6115-fxtec-pro1x.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6115p-lenovo-j606f.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb diff --git a/arch/arm64/boot/dts/qcom/sm4450-qrd.dts b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts new file mode 100644 index 000000000000..00a1c81ca397 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "sm4450.dtsi" +/ { + model = "Qualcomm Technologies, Inc. SM4450 QRD"; + compatible = "qcom,sm4450-qrd", "qcom,sm4450"; + + aliases { }; + + chosen { + bootargs = "console=hvc0"; + }; +}; -- cgit v1.2.3-59-g8ed1b From 2c9e45dfeed126488aa73e7b82b3576c4c6f1036 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Tue, 1 Aug 2023 12:52:46 +0300 Subject: arm64: dts: qcom: sm8550-mtp: Add missing supply for L1B regulator Even though currently there is no consumer for L1B, add the supply for it anyway. Fixes: 71342fb91eae ("arm64: dts: qcom: Add base SM8550 MTP dts") Signed-off-by: Abel Vesa Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20230801095246.2884770-1-abel.vesa@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 39a43db26ea1..f29cce5186ac 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -195,6 +195,7 @@ vdd-bob1-supply = <&vph_pwr>; vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s6g_1p8>; vdd-l2-l13-l14-supply = <&vreg_bob1>; vdd-l3-supply = <&vreg_s4g_1p3>; vdd-l5-l16-supply = <&vreg_bob1>; -- cgit v1.2.3-59-g8ed1b From b79663a5515f01307f25206c313997ef6267e0fd Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 30 Jul 2023 20:06:38 +0200 Subject: arm64: dts: qcom: use defines for interrupts Replace hard-coded interrupt parts (GIC, flags) with standard defines for readability. No changes in resulting DTBs. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230730180638.23539-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8939.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8976.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8994.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8996.dtsi | 12 ++++++------ arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdm630.dtsi | 18 +++++++++--------- arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts | 2 +- 7 files changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi index af6d644a5d38..6e24f0f2374f 100644 --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -1975,7 +1975,7 @@ }; smd-edge { - interrupts = ; + interrupts = ; qcom,ipc = <&apcs1_mbox 8 17>; qcom,smd-edge = <6>; qcom,remote-pid = <4>; diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index ab76806317a7..f9f5afbcc52b 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -439,7 +439,7 @@ hexagon_smsm: hexagon@1 { reg = <1>; - interrupts = <0 290 IRQ_TYPE_EDGE_RISING>; + interrupts = ; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index c374fba5d8f9..c3262571520d 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -456,7 +456,7 @@ usb@f9200000 { compatible = "snps,dwc3"; reg = <0xf9200000 0xcc00>; - interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; maximum-speed = "high-speed"; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 440557c8eca4..6f7065e8fd6c 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -589,7 +589,7 @@ compatible = "qcom,smp2p"; qcom,smem = <443>, <429>; - interrupts = <0 158 IRQ_TYPE_EDGE_RISING>; + interrupts = ; mboxes = <&apcs_glb 10>; @@ -1264,7 +1264,7 @@ reg = <0x00b00000 0x3f000>; reg-names = "kgsl_3d0_reg_memory"; - interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&mmcc GPU_GX_GFX3D_CLK>, <&mmcc GPU_AHB_CLK>, @@ -3054,7 +3054,7 @@ usb3_dwc3: usb@6a00000 { compatible = "snps,dwc3"; reg = <0x06a00000 0xcc00>; - interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; phys = <&hsusb_phy1>, <&ssusb_phy_0>; phy-names = "usb2-phy", "usb3-phy"; snps,hird-threshold = /bits/ 8 <0>; @@ -3412,7 +3412,7 @@ usb2_dwc3: usb@7600000 { compatible = "snps,dwc3"; reg = <0x07600000 0xcc00>; - interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; phys = <&hsusb_phy2>; phy-names = "usb2-phy"; maximum-speed = "high-speed"; @@ -3426,7 +3426,7 @@ qcom,controlled-remotely; reg = <0x09184000 0x32000>; num-channels = <31>; - interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; #dma-cells = <1>; qcom,ee = <1>; qcom,num-ees = <2>; @@ -3435,7 +3435,7 @@ slim_msm: slim-ngd@91c0000 { compatible = "qcom,slim-ngd-v1.5.0"; reg = <0x091c0000 0x2c000>; - interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; dmas = <&slimbam 3>, <&slimbam 4>; dma-names = "rx", "tx"; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 360fe3edcc08..a41a34dbcc3c 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -1494,7 +1494,7 @@ "rbcpr", "core"; - interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; iommus = <&adreno_smmu 0>; operating-points-v2 = <&gpu_opp_table>; power-domains = <&rpmpd MSM8998_VDDMX>; diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 83afce56a7b0..ec6003212c4d 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1034,7 +1034,7 @@ reg = <0x05000000 0x40000>; reg-names = "kgsl_3d0_reg_memory"; - interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, <&gpucc GPUCC_RBBMTIMER_CLK>, @@ -2290,50 +2290,50 @@ frame@17921000 { frame-number = <0>; - interrupts = <0 8 0x4>, - <0 7 0x4>; + interrupts = , + ; reg = <0x17921000 0x1000>, <0x17922000 0x1000>; }; frame@17923000 { frame-number = <1>; - interrupts = <0 9 0x4>; + interrupts = ; reg = <0x17923000 0x1000>; status = "disabled"; }; frame@17924000 { frame-number = <2>; - interrupts = <0 10 0x4>; + interrupts = ; reg = <0x17924000 0x1000>; status = "disabled"; }; frame@17925000 { frame-number = <3>; - interrupts = <0 11 0x4>; + interrupts = ; reg = <0x17925000 0x1000>; status = "disabled"; }; frame@17926000 { frame-number = <4>; - interrupts = <0 12 0x4>; + interrupts = ; reg = <0x17926000 0x1000>; status = "disabled"; }; frame@17927000 { frame-number = <5>; - interrupts = <0 13 0x4>; + interrupts = ; reg = <0x17927000 0x1000>; status = "disabled"; }; frame@17928000 { frame-number = <6>; - interrupts = <0 14 0x4>; + interrupts = ; reg = <0x17928000 0x1000>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index dce0141f3719..fbb8655653fb 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -440,7 +440,7 @@ reg = <0x38>; wakeup-source; interrupt-parent = <&tlmm>; - interrupts = <125 0x2>; + interrupts = <125 IRQ_TYPE_EDGE_FALLING>; vdd-supply = <&vreg_l28a_3p0>; vcc-i2c-supply = <&vreg_l14a_1p88>; -- cgit v1.2.3-59-g8ed1b From 7c0755120f1f0495fe418d50f0618945136df9d1 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 30 Jul 2023 22:19:12 +0200 Subject: arm64: dts: qcom: msm8953-tissot: use 0 as speaker DAI cells MAX98927 speaker amplifier has only one DAI, so DAI cells can be just 0 (as expected by bindings). Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230730201913.70667-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8953-xiaomi-tissot.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-tissot.dts b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-tissot.dts index 831d3a42b583..61ff629c9bf3 100644 --- a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-tissot.dts +++ b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-tissot.dts @@ -96,7 +96,7 @@ vmon-slot-no = <1>; imon-slot-no = <1>; - #sound-dai-cells = <1>; + #sound-dai-cells = <0>; }; led-controller@45 { -- cgit v1.2.3-59-g8ed1b From 636f47cac06a881415b8126802c38cbe5b32b575 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 30 Jul 2023 22:19:13 +0200 Subject: arm64: dts: qcom: sdm845-enchilada: use 0 as speaker DAI cells MAX98927 speaker amplifier has only one DAI, so DAI cells can be just 0 (as expected by bindings). Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230730201913.70667-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts index 62fe72ff3763..4005e04d998a 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts @@ -39,7 +39,7 @@ max98927_codec: max98927@3a { compatible = "maxim,max98927"; reg = <0x3a>; - #sound-dai-cells = <1>; + #sound-dai-cells = <0>; pinctrl-0 = <&speaker_default>; pinctrl-names = "default"; @@ -66,7 +66,7 @@ &speaker_playback_dai { codec { - sound-dai = <&max98927_codec 0>; + sound-dai = <&max98927_codec>; }; }; -- cgit v1.2.3-59-g8ed1b From b6866546c214aad707f69a7d96215e3d08c2eb84 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 30 Jul 2023 22:20:51 +0200 Subject: arm64: dts: qcom: msm8953-daisy: use new speaker maxim,interleave-mode MAX98927 speaker amplifier "interleave_mode" property was never documented. Corrected bindings expect "maxim,interleave-mode" instead, which is already supported by Linux driver. Change is not compatible with older Linux kernels. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230730202051.71099-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts index 790d19c99af1..a5957e79b818 100644 --- a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts +++ b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts @@ -125,7 +125,7 @@ vmon-slot-no = <1>; imon-slot-no = <1>; - interleave_mode = <0>; + maxim,interleave-mode; #sound-dai-cells = <0>; }; -- cgit v1.2.3-59-g8ed1b From 41c1855232ed277e74daedbecac8d328b6c2ceb8 Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Sun, 30 Jul 2023 22:31:26 +0200 Subject: arm64: dts: qcom: Use labels with generic node names for ADC channels As discussed in [1] it is more convenient to use a generic `channel` node name for ADC channels while storing a friendly - board-specific instead of PMIC-specific - name in the label, if/when desired to overwrite the channel description already contained (but previously unused) in the driver [2]. Follow up on the dt-bindings' `channel` node name requirement, and instead provide this (sometimes per-board) channel description through a label property. Also remove all the unused label references (not to be confused with label properties) from pm660, pmp8074 and pms405. [1]: https://lore.kernel.org/linux-arm-msm/20221106193018.270106-1-marijn.suijten@somainline.org/T/#u [2]: https://lore.kernel.org/linux-arm-msm/20230116220909.196926-4-marijn.suijten@somainline.org/ Acked-by: Konrad Dybcio Signed-off-by: Marijn Suijten Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20230730-generic-adc-channels-v5-2-e6c69bda8034@somainline.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm6125.dtsi | 18 ++++++---- arch/arm64/boot/dts/qcom/pm6150.dtsi | 2 +- arch/arm64/boot/dts/qcom/pm6150l.dtsi | 8 ++--- arch/arm64/boot/dts/qcom/pm660.dtsi | 33 ++++++++++++------ arch/arm64/boot/dts/qcom/pm7250b.dtsi | 24 ++++++------- arch/arm64/boot/dts/qcom/pm8150.dtsi | 6 ++-- arch/arm64/boot/dts/qcom/pm8150b.dtsi | 8 ++--- arch/arm64/boot/dts/qcom/pm8150l.dtsi | 6 ++-- arch/arm64/boot/dts/qcom/pm8916.dtsi | 14 ++++---- arch/arm64/boot/dts/qcom/pm8950.dtsi | 39 ++++++++++++++-------- arch/arm64/boot/dts/qcom/pm8953.dtsi | 12 +++---- arch/arm64/boot/dts/qcom/pm8994.dtsi | 12 +++---- arch/arm64/boot/dts/qcom/pm8998.dtsi | 2 +- arch/arm64/boot/dts/qcom/pmi8950.dtsi | 12 +++---- arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi | 6 ++-- arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi | 6 ++-- arch/arm64/boot/dts/qcom/pmp8074.dtsi | 27 ++++++++++----- arch/arm64/boot/dts/qcom/pms405.dtsi | 21 ++++++++---- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 15 ++++++--- .../boot/dts/qcom/sc7180-trogdor-coachz-r1.dts | 4 +-- .../arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi | 3 +- .../boot/dts/qcom/sc7180-trogdor-homestar.dtsi | 3 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi | 2 +- .../boot/dts/qcom/sc7180-trogdor-pompom-r1.dts | 2 +- .../boot/dts/qcom/sc7180-trogdor-pompom-r2.dts | 2 +- .../arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi | 3 +- .../boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi | 3 +- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 3 +- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 2 +- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 2 +- arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi | 4 +-- .../dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 26 +++++++-------- arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 10 +++--- arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 12 +++---- .../dts/qcom/sm6125-sony-xperia-seine-pdx201.dts | 15 ++++++--- arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 6 ++-- arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 21 ++++++++---- 37 files changed, 231 insertions(+), 163 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm6125.dtsi b/arch/arm64/boot/dts/qcom/pm6125.dtsi index 59092a551a16..99369a0cdb61 100644 --- a/arch/arm64/boot/dts/qcom/pm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6125.dtsi @@ -85,36 +85,42 @@ interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; #io-channel-cells = <1>; - ref-gnd@0 { + channel@0 { reg = ; qcom,pre-scaling = <1 1>; + label = "ref_gnd"; }; - vref-1p25@1 { + channel@1 { reg = ; qcom,pre-scaling = <1 1>; + label = "vref_1p25"; }; - die-temp@6 { + channel@6 { reg = ; qcom,pre-scaling = <1 1>; + label = "die_temp"; }; - vph-pwr@83 { + channel@83 { reg = ; qcom,pre-scaling = <1 3>; + label = "vph_pwr"; }; - vcoin@85 { + channel@85 { reg = ; qcom,pre-scaling = <1 3>; + label = "vcoin"; }; - xo-therm@4c { + channel@4c { reg = ; qcom,pre-scaling = <1 1>; qcom,hw-settle-time = <200>; qcom,ratiometric; + label = "xo_therm"; }; }; diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi b/arch/arm64/boot/dts/qcom/pm6150.dtsi index 2e6afa296141..7d4d1f2767ed 100644 --- a/arch/arm64/boot/dts/qcom/pm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150.dtsi @@ -72,7 +72,7 @@ #size-cells = <0>; #io-channel-cells = <1>; - adc-chan@6 { + channel@6 { reg = ; label = "die_temp"; }; diff --git a/arch/arm64/boot/dts/qcom/pm6150l.dtsi b/arch/arm64/boot/dts/qcom/pm6150l.dtsi index 0fdf440596c0..d13a1ab7c20b 100644 --- a/arch/arm64/boot/dts/qcom/pm6150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150l.dtsi @@ -60,25 +60,25 @@ #size-cells = <0>; #io-channel-cells = <1>; - adc-chan@0 { + channel@0 { reg = ; qcom,pre-scaling = <1 1>; label = "ref_gnd"; }; - adc-chan@1 { + channel@1 { reg = ; qcom,pre-scaling = <1 1>; label = "vref_1p25"; }; - adc-chan@6 { + channel@6 { reg = ; qcom,pre-scaling = <1 1>; label = "die_temp"; }; - adc-chan@83 { + channel@83 { reg = ; qcom,pre-scaling = <1 3>; label = "vph_pwr"; diff --git a/arch/arm64/boot/dts/qcom/pm660.dtsi b/arch/arm64/boot/dts/qcom/pm660.dtsi index 4bc717917f44..98dc04962fe3 100644 --- a/arch/arm64/boot/dts/qcom/pm660.dtsi +++ b/arch/arm64/boot/dts/qcom/pm660.dtsi @@ -91,82 +91,93 @@ #size-cells = <0>; #io-channel-cells = <1>; - ref_gnd: ref_gnd@0 { + channel@0 { reg = ; qcom,decimation = <1024>; qcom,pre-scaling = <1 1>; + label = "ref_gnd"; }; - vref_1p25: vref_1p25@1 { + channel@1 { reg = ; qcom,decimation = <1024>; qcom,pre-scaling = <1 1>; + label = "vref_1p25"; }; - die_temp: die_temp@6 { + channel@6 { reg = ; qcom,decimation = <1024>; qcom,pre-scaling = <1 1>; + label = "die_temp"; }; - xo_therm: xo_therm@4c { + channel@4c { reg = ; qcom,pre-scaling = <1 1>; qcom,decimation = <1024>; qcom,hw-settle-time = <200>; qcom,ratiometric; + label = "xo_therm"; }; - msm_therm: msm_therm@4d { + channel@4d { reg = ; qcom,pre-scaling = <1 1>; qcom,decimation = <1024>; qcom,hw-settle-time = <200>; qcom,ratiometric; + label = "msm_therm"; }; - emmc_therm: emmc_therm@4e { + channel@4e { reg = ; qcom,pre-scaling = <1 1>; qcom,decimation = <1024>; qcom,hw-settle-time = <200>; qcom,ratiometric; + label = "emmc_therm"; }; - pa_therm0: thermistor0@4f { + channel@4f { reg = ; qcom,pre-scaling = <1 1>; qcom,decimation = <1024>; qcom,hw-settle-time = <200>; qcom,ratiometric; + label = "pa_therm0"; }; - pa_therm1: thermistor1@50 { + channel@50 { reg = ; qcom,pre-scaling = <1 1>; qcom,decimation = <1024>; qcom,hw-settle-time = <200>; qcom,ratiometric; + label = "pa_therm1"; }; - quiet_therm: quiet_therm@51 { + channel@51 { reg = ; qcom,pre-scaling = <1 1>; qcom,decimation = <1024>; qcom,hw-settle-time = <200>; qcom,ratiometric; + label = "quiet_therm"; }; - vadc_vph_pwr: vph_pwr@83 { + channel@83 { reg = ; qcom,decimation = <1024>; qcom,pre-scaling = <1 3>; + label = "vph_pwr"; }; - vcoin: vcoin@85 { + channel@85 { reg = ; qcom,decimation = <1024>; qcom,pre-scaling = <1 3>; + label = "vcoin"; }; }; diff --git a/arch/arm64/boot/dts/qcom/pm7250b.dtsi b/arch/arm64/boot/dts/qcom/pm7250b.dtsi index daa6f1d30efa..22c0d5266179 100644 --- a/arch/arm64/boot/dts/qcom/pm7250b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm7250b.dtsi @@ -62,56 +62,56 @@ #io-channel-cells = <1>; interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - adc-chan@0 { + channel@0 { reg = ; qcom,pre-scaling = <1 1>; label = "ref_gnd"; }; - adc-chan@1 { + channel@1 { reg = ; qcom,pre-scaling = <1 1>; label = "vref_1p25"; }; - adc-chan@2 { + channel@2 { reg = ; qcom,pre-scaling = <1 1>; label = "die_temp"; }; - adc-chan@7 { + channel@7 { reg = ; qcom,pre-scaling = <1 1>; label = "usb_in_i_uv"; }; - adc-chan@8 { + channel@8 { reg = ; qcom,pre-scaling = <1 16>; label = "usb_in_v_div_16"; }; - adc-chan@9 { + channel@9 { reg = ; qcom,pre-scaling = <1 1>; label = "chg_temp"; }; - adc-chan@e { + channel@e { reg = ; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; label = "smb1390_therm"; }; - adc-chan@1e { + channel@1e { reg = ; qcom,pre-scaling = <1 6>; label = "chg_mid"; }; - adc-chan@4b { + channel@4b { reg = ; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; @@ -119,19 +119,19 @@ label = "bat_id"; }; - adc-chan@83 { + channel@83 { reg = ; qcom,pre-scaling = <1 3>; label = "vph_pwr"; }; - adc-chan@84 { + channel@84 { reg = ; qcom,pre-scaling = <1 3>; label = "vbat_sns"; }; - adc-chan@99 { + channel@99 { reg = ; qcom,pre-scaling = <1 3>; label = "chg_sbux"; diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi index db90c55fa2cf..3ba3ba5d8fce 100644 --- a/arch/arm64/boot/dts/qcom/pm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150.dtsi @@ -90,19 +90,19 @@ #io-channel-cells = <1>; interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - ref-gnd@0 { + channel@0 { reg = ; qcom,pre-scaling = <1 1>; label = "ref_gnd"; }; - vref-1p25@1 { + channel@1 { reg = ; qcom,pre-scaling = <1 1>; label = "vref_1p25"; }; - die-temp@6 { + channel@6 { reg = ; qcom,pre-scaling = <1 1>; label = "die_temp"; diff --git a/arch/arm64/boot/dts/qcom/pm8150b.dtsi b/arch/arm64/boot/dts/qcom/pm8150b.dtsi index 66752cc063d6..2b9123df5847 100644 --- a/arch/arm64/boot/dts/qcom/pm8150b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150b.dtsi @@ -76,25 +76,25 @@ #io-channel-cells = <1>; interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - ref-gnd@0 { + channel@0 { reg = ; qcom,pre-scaling = <1 1>; label = "ref_gnd"; }; - vref-1p25@1 { + channel@1 { reg = ; qcom,pre-scaling = <1 1>; label = "vref_1p25"; }; - die-temp@6 { + channel@6 { reg = ; qcom,pre-scaling = <1 1>; label = "die_temp"; }; - chg-temp@9 { + channel@9 { reg = ; qcom,pre-scaling = <1 1>; label = "chg_temp"; diff --git a/arch/arm64/boot/dts/qcom/pm8150l.dtsi b/arch/arm64/boot/dts/qcom/pm8150l.dtsi index cca45fad75ac..b1686e5777b8 100644 --- a/arch/arm64/boot/dts/qcom/pm8150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150l.dtsi @@ -70,19 +70,19 @@ #io-channel-cells = <1>; interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - ref-gnd@0 { + channel@0 { reg = ; qcom,pre-scaling = <1 1>; label = "ref_gnd"; }; - vref-1p25@1 { + channel@1 { reg = ; qcom,pre-scaling = <1 1>; label = "vref_1p25"; }; - die-temp@6 { + channel@6 { reg = ; qcom,pre-scaling = <1 1>; label = "die_temp"; diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi index 1ea8920ff369..223442f909f1 100644 --- a/arch/arm64/boot/dts/qcom/pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi @@ -66,27 +66,27 @@ #size-cells = <0>; #io-channel-cells = <1>; - adc-chan@0 { + channel@0 { reg = ; qcom,pre-scaling = <1 10>; }; - adc-chan@7 { + channel@7 { reg = ; qcom,pre-scaling = <1 3>; }; - adc-chan@8 { + channel@8 { reg = ; }; - adc-chan@9 { + channel@9 { reg = ; }; - adc-chan@a { + channel@a { reg = ; }; - adc-chan@e { + channel@e { reg = ; }; - adc-chan@f { + channel@f { reg = ; }; }; diff --git a/arch/arm64/boot/dts/qcom/pm8950.dtsi b/arch/arm64/boot/dts/qcom/pm8950.dtsi index 5ec38b7e335a..f03095779de0 100644 --- a/arch/arm64/boot/dts/qcom/pm8950.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8950.dtsi @@ -50,77 +50,90 @@ #size-cells = <0>; #io-channel-cells = <1>; - vcoin@5 { + channel@5 { reg = ; qcom,pre-scaling = <1 1>; + label = "vcoin"; }; - vph-pwr@7 { + channel@7 { reg = ; qcom,pre-scaling = <1 1>; + label = "vph_pwr"; }; - die-temp@8 { + channel@8 { reg = ; qcom,pre-scaling = <1 1>; + label = "die_temp"; }; - ref-625mv@9 { + channel@9 { reg = ; qcom,pre-scaling = <1 1>; + label = "ref_625mv"; }; - ref-1250mv@a { + channel@a { reg = ; qcom,pre-scaling = <1 1>; + label = "ref_1250mv"; }; - ref-buf-625mv@c { + channel@c { reg = ; qcom,pre-scaling = <1 1>; + label = "ref_buf_625mv"; }; - ref-gnd@e { + channel@e { reg = ; + label = "ref_gnd"; }; - ref-vdd@f { + channel@f { reg = ; + label = "ref_vdd"; }; - pa-therm1@11 { + channel@11 { reg = ; qcom,pre-scaling = <1 1>; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "pa_therm1"; }; - case-therm@13 { + channel@13 { reg = ; qcom,pre-scaling = <1 1>; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "case_therm"; }; - xo-therm@32 { + channel@32 { reg = ; qcom,pre-scaling = <1 1>; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "xo_therm"; }; - pa-therm0@36 { + channel@36 { reg = ; qcom,pre-scaling = <1 1>; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "pa_therm0"; }; - xo-therm-buf@3c { + channel@3c { reg = ; qcom,pre-scaling = <1 1>; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "xo_therm_buf"; }; }; diff --git a/arch/arm64/boot/dts/qcom/pm8953.dtsi b/arch/arm64/boot/dts/qcom/pm8953.dtsi index d2dfc1699174..1067e141be6c 100644 --- a/arch/arm64/boot/dts/qcom/pm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8953.dtsi @@ -84,22 +84,22 @@ #size-cells = <0>; #io-channel-cells = <1>; - adc-chan@8 { + channel@8 { reg = ; }; - adc-chan@9 { + channel@9 { reg = ; }; - adc-chan@a { + channel@a { reg = ; }; - adc-chan@c { + channel@c { reg = ; }; - adc-chan@e { + channel@e { reg = ; }; - adc-chan@f { + channel@f { reg = ; }; }; diff --git a/arch/arm64/boot/dts/qcom/pm8994.dtsi b/arch/arm64/boot/dts/qcom/pm8994.dtsi index 672094c8ca58..d44a95caf04a 100644 --- a/arch/arm64/boot/dts/qcom/pm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8994.dtsi @@ -83,27 +83,27 @@ #size-cells = <0>; #io-channel-cells = <1>; - adc-chan@7 { + channel@7 { reg = ; qcom,pre-scaling = <1 3>; label = "vph_pwr"; }; - adc-chan@8 { + channel@8 { reg = ; label = "die_temp"; }; - adc-chan@9 { + channel@9 { reg = ; label = "ref_625mv"; }; - adc-chan@a { + channel@a { reg = ; label = "ref_1250mv"; }; - adc-chan@e { + channel@e { reg = ; }; - adc-chan@f { + channel@f { reg = ; }; }; diff --git a/arch/arm64/boot/dts/qcom/pm8998.dtsi b/arch/arm64/boot/dts/qcom/pm8998.dtsi index 695d79116cde..3f82715392c6 100644 --- a/arch/arm64/boot/dts/qcom/pm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8998.dtsi @@ -86,7 +86,7 @@ #size-cells = <0>; #io-channel-cells = <1>; - adc-chan@6 { + channel@6 { reg = ; label = "die_temp"; }; diff --git a/arch/arm64/boot/dts/qcom/pmi8950.dtsi b/arch/arm64/boot/dts/qcom/pmi8950.dtsi index c16adca4e93a..1029f3b1bb9a 100644 --- a/arch/arm64/boot/dts/qcom/pmi8950.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8950.dtsi @@ -20,37 +20,37 @@ #size-cells = <0>; #io-channel-cells = <1>; - adc-chan@0 { + channel@0 { reg = ; qcom,pre-scaling = <1 4>; label = "usbin"; }; - adc-chan@1 { + channel@1 { reg = ; qcom,pre-scaling = <1 4>; label = "dcin"; }; - adc-chan@2 { + channel@2 { reg = ; qcom,pre-scaling = <1 1>; label = "vchg_sns"; }; - adc-chan@9 { + channel@9 { reg = ; qcom,pre-scaling = <1 1>; label = "ref_625mv"; }; - adc-chan@a { + channel@a { reg = ; qcom,pre-scaling = <1 1>; label = "ref_1250mv"; }; - adc-chan@d { + channel@d { reg = ; qcom,pre-scaling = <1 1>; label = "chg_temp"; diff --git a/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi b/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi index ee1e428d3a6e..dbd4b91dfe06 100644 --- a/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi +++ b/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi @@ -77,19 +77,19 @@ #io-channel-cells = <1>; interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - ref-gnd@0 { + channel@0 { reg = ; qcom,pre-scaling = <1 1>; label = "ref_gnd"; }; - vref-1p25@1 { + channel@1 { reg = ; qcom,pre-scaling = <1 1>; label = "vref_1p25"; }; - die-temp@6 { + channel@6 { reg = ; qcom,pre-scaling = <1 1>; label = "die_temp"; diff --git a/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi b/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi index 1da4606e8ee6..1cee20ac2c9c 100644 --- a/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi +++ b/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi @@ -69,19 +69,19 @@ #io-channel-cells = <1>; interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - ref-gnd@0 { + channel@0 { reg = ; qcom,pre-scaling = <1 1>; label = "ref_gnd"; }; - vref-1p25@1 { + channel@1 { reg = ; qcom,pre-scaling = <1 1>; label = "vref_1p25"; }; - die-temp@6 { + channel@6 { reg = ; qcom,pre-scaling = <1 1>; label = "die_temp"; diff --git a/arch/arm64/boot/dts/qcom/pmp8074.dtsi b/arch/arm64/boot/dts/qcom/pmp8074.dtsi index 580684411d74..0d0a846ac8d9 100644 --- a/arch/arm64/boot/dts/qcom/pmp8074.dtsi +++ b/arch/arm64/boot/dts/qcom/pmp8074.dtsi @@ -18,57 +18,66 @@ #size-cells = <0>; #io-channel-cells = <1>; - ref-gnd@0 { + channel@0 { reg = ; qcom,pre-scaling = <1 1>; + label = "ref_gnd"; }; - vref-1p25@1 { + channel@1 { reg = ; qcom,pre-scaling = <1 1>; + label = "vref_1p25"; }; - vref-vadc@2 { + channel@2 { reg = ; qcom,pre-scaling = <1 1>; + label = "vref_vadc"; }; - pmic_die: die-temp@6 { + channel@6 { reg = ; qcom,pre-scaling = <1 1>; + label = "pmic_die"; }; - xo_therm: xo-temp@76 { + channel@76 { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; + label = "xo_therm"; }; - pa_therm1: thermistor1@77 { + channel@77 { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; + label = "pa_therm1"; }; - pa_therm2: thermistor2@78 { + channel@78 { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; + label = "pa_therm2"; }; - pa_therm3: thermistor3@79 { + channel@79 { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; + label = "pa_therm3"; }; - vph-pwr@131 { + channel@131 { reg = ; qcom,pre-scaling = <1 3>; + label = "vph_pwr"; }; }; diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi b/arch/arm64/boot/dts/qcom/pms405.dtsi index 22edb47c6a84..461ad97032f7 100644 --- a/arch/arm64/boot/dts/qcom/pms405.dtsi +++ b/arch/arm64/boot/dts/qcom/pms405.dtsi @@ -81,45 +81,52 @@ #size-cells = <0>; #io-channel-cells = <1>; - ref_gnd@0 { + channel@0 { reg = ; qcom,pre-scaling = <1 1>; + label = "ref_gnd"; }; - vref_1p25@1 { + channel@1 { reg = ; qcom,pre-scaling = <1 1>; + label = "vref_1p25"; }; - pon_1: vph_pwr@131 { + channel@131 { reg = ; qcom,pre-scaling = <1 3>; + label = "vph_pwr"; }; - die_temp@6 { + channel@6 { reg = ; qcom,pre-scaling = <1 1>; + label = "die_temp"; }; - pa_therm1: thermistor1@77 { + channel@77 { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; + label = "pa_therm1"; }; - pa_therm3: thermistor3@79 { + channel@79 { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; + label = "pa_therm3"; }; - xo_therm: xo_temp@76 { + channel@76 { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; + label = "xo_therm"; }; }; diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 9022ad726741..7289da134962 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -640,16 +640,18 @@ }; &pm8150_adc { - xo-therm@4c { + channel@4c { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "xo_therm"; }; - wifi-therm@4e { + channel@4e { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "wifi_therm"; }; }; @@ -717,10 +719,11 @@ }; &pm8150b_adc { - conn-therm@4f { + channel@4f { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "conn_therm"; }; }; @@ -752,16 +755,18 @@ }; &pm8150l_adc { - skin-msm-therm@4e { + channel@4e { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "skin_msm_therm"; }; - pm8150l-therm@4f { + channel@4f { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "pm8150l_therm"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts index edfcd47e1a00..03d350dcec96 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts @@ -24,8 +24,8 @@ }; &pm6150_adc { - /delete-node/ skin-temp-thermistor@4e; - /delete-node/ charger-thermistor@4f; + /delete-node/ channel@4e; + /delete-node/ channel@4f; }; &pm6150_adc_tm { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi index 8b8ea8af165d..a532cc4aac47 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi @@ -119,10 +119,11 @@ ap_ts_pen_1v8: &i2c4 { }; &pm6150_adc { - skin-temp-thermistor@4e { + channel@4e { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "skin_therm"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi index b3ba23a88a0b..b27dcd2ec856 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi @@ -145,10 +145,11 @@ ap_ts_pen_1v8: &i2c4 { }; &pm6150_adc { - skin-temp-thermistor@4d { + channel@4d { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "skin_therm"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi index 269007d73162..13339b723a93 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi @@ -55,7 +55,7 @@ ap_ts_pen_1v8: &i2c4 { }; &pm6150_adc { - /delete-node/ charger-thermistor@4f; + /delete-node/ channel@4f; }; &pm6150_adc_tm { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dts index 8467ff41e6d5..ba222a60c4c6 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dts @@ -27,7 +27,7 @@ }; &pm6150_adc { - /delete-node/ charger-thermistor@4f; + /delete-node/ channel@4f; }; &pm6150_adc_tm { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2.dts index 88cf2246c18a..64d6172bf402 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2.dts @@ -24,7 +24,7 @@ }; &pm6150_adc { - /delete-node/ charger-thermistor@4f; + /delete-node/ channel@4f; }; &pm6150_adc_tm { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi index 6c5287bd27d6..fd944842dd6c 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi @@ -148,10 +148,11 @@ ap_ts_pen_1v8: &i2c4 { }; &pm6150_adc { - 5v-choke-thermistor@4e { + channel@4e { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "5v_choke_therm"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi index 2efa8a4bcda6..2f6a340ddd2a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi @@ -163,10 +163,11 @@ }; &pm6150_adc { - skin-temp-thermistor@4d { + channel@4d { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "skin_therm"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 681637cf6c4a..af16e36bcb40 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -837,10 +837,11 @@ hp_i2c: &i2c9 { }; &pm6150_adc { - charger-thermistor@4f { + channel@4f { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "charger_therm"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts index 15222e92e3f5..b5fe7356be48 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -73,7 +73,7 @@ }; &pmk8350_vadc { - pmr735a-die-temp@403 { + channel@403 { reg = ; label = "pmr735a_die_temp"; qcom,pre-scaling = <1 1>; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 21027042cf13..2ff549f4dc7a 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -432,7 +432,7 @@ }; &pmk8350_vadc { - pmk8350-die-temp@3 { + channel@3 { reg = ; label = "pmk8350_die_temp"; qcom,pre-scaling = <1 1>; diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi index 9137db066d9e..f9b96bd2477e 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi @@ -383,13 +383,13 @@ }; &pmk8350_vadc { - pmk8350-die-temp@3 { + channel@3 { reg = ; label = "pmk8350_die_temp"; qcom,pre-scaling = <1 1>; }; - pmr735a-die-temp@403 { + channel@403 { reg = ; label = "pmr735a_die_temp"; qcom,pre-scaling = <1 1>; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 6b5a7de6a27d..ffcca4f028e7 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -834,88 +834,88 @@ &pmk8280_vadc { status = "okay"; - pmic-die-temp@3 { + channel@3 { reg = ; qcom,pre-scaling = <1 1>; label = "pmk8350_die_temp"; }; - xo-therm@44 { + channel@44 { reg = ; qcom,hw-settle-time = <200>; qcom,ratiometric; label = "pmk8350_xo_therm"; }; - pmic-die-temp@103 { + channel@103 { reg = ; qcom,pre-scaling = <1 1>; label = "pmc8280_1_die_temp"; }; - sys-therm@144 { + channel@144 { reg = ; qcom,hw-settle-time = <200>; qcom,ratiometric; label = "sys_therm1"; }; - sys-therm@145 { + channel@145 { reg = ; qcom,hw-settle-time = <200>; qcom,ratiometric; label = "sys_therm2"; }; - sys-therm@146 { + channel@146 { reg = ; qcom,hw-settle-time = <200>; qcom,ratiometric; label = "sys_therm3"; }; - sys-therm@147 { + channel@147 { reg = ; qcom,hw-settle-time = <200>; qcom,ratiometric; label = "sys_therm4"; }; - pmic-die-temp@303 { + channel@303 { reg = ; qcom,pre-scaling = <1 1>; label = "pmc8280_2_die_temp"; }; - sys-therm@344 { + channel@344 { reg = ; qcom,hw-settle-time = <200>; qcom,ratiometric; label = "sys_therm5"; }; - sys-therm@345 { + channel@345 { reg = ; qcom,hw-settle-time = <200>; qcom,ratiometric; label = "sys_therm6"; }; - sys-therm@346 { + channel@346 { reg = ; qcom,hw-settle-time = <200>; qcom,ratiometric; label = "sys_therm7"; }; - sys-therm@347 { + channel@347 { reg = ; qcom,hw-settle-time = <200>; qcom,ratiometric; label = "sys_therm8"; }; - pmic-die-temp@403 { + channel@403 { reg = ; qcom,pre-scaling = <1 1>; label = "pmr735a_die_temp"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi index 1ce413263b7f..f86e7acdfd99 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -1071,27 +1071,27 @@ ap_ts_i2c: &i2c14 { }; &pm8998_adc { - adc-chan@4d { + channel@4d { reg = ; label = "sdm_temp"; }; - adc-chan@4e { + channel@4e { reg = ; label = "quiet_temp"; }; - adc-chan@4f { + channel@4f { reg = ; label = "lte_temp_1"; }; - adc-chan@50 { + channel@50 { reg = ; label = "lte_temp_2"; }; - adc-chan@51 { + channel@51 { reg = ; label = "charger_temp"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index 41675a8de268..b3c27a524742 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -534,42 +534,42 @@ }; &pm8998_adc { - adc-chan@4c { + channel@4c { reg = ; label = "xo_therm"; qcom,ratiometric; qcom,hw-settle-time = <200>; }; - adc-chan@4d { + channel@4d { reg = ; label = "msm_therm"; qcom,ratiometric; qcom,hw-settle-time = <200>; }; - adc-chan@4f { + channel@4f { reg = ; label = "pa_therm1"; qcom,ratiometric; qcom,hw-settle-time = <200>; }; - adc-chan@51 { + channel@51 { reg = ; label = "quiet_therm"; qcom,ratiometric; qcom,hw-settle-time = <200>; }; - adc-chan@83 { + channel@83 { reg = ; label = "vph_pwr"; qcom,ratiometric; qcom,hw-settle-time = <200>; }; - adc-chan@85 { + channel@85 { reg = ; label = "vcoin"; qcom,ratiometric; diff --git a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts index e42a4e710cd2..fb4cba004367 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts +++ b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts @@ -183,39 +183,44 @@ pinctrl-names = "default"; pinctrl-0 = <&camera_flash_therm &emmc_ufs_therm &rf_pa1_therm>; - rf-pa0-therm@4d { + channel@4d { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; + label = "rf_pa0_therm"; }; - quiet-therm@4e { + channel@4e { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; + label = "quiet_therm"; }; - camera-flash-therm@52 { + channel@52 { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; + label = "camera_flash_therm"; }; - emmc-ufs-therm@54 { + channel@54 { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; + label = "emmc_ufs_therm"; }; - rf-pa1-therm@55 { + channel@55 { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; + label = "rf_pa1_therm"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index e3dc49951523..18171c5d8a38 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -476,7 +476,7 @@ }; &pm7250b_adc { - adc-chan@4d { + channel@4d { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; @@ -484,7 +484,7 @@ label = "charger_skin_therm"; }; - adc-chan@4f { + channel@4f { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; @@ -516,7 +516,7 @@ }; &pmk8350_vadc { - adc-chan@644 { + channel@644 { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index ad2b60e281eb..7ef99038cb37 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -526,22 +526,25 @@ }; &pm8150_adc { - xo-therm@4c { + channel@4c { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "xo_therm"; }; - skin-therm@4d { + channel@4d { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "skin_therm"; }; - pa-therm1@4e { + channel@4e { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "pa_therm1"; }; }; @@ -571,10 +574,11 @@ }; &pm8150b_adc { - conn-therm@4f { + channel@4f { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "conn_therm"; }; }; @@ -615,22 +619,25 @@ }; &pm8150l_adc { - camera-flash-therm@4d { + channel@4d { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "camera_flash_therm"; }; - skin-msm-therm@4e { + channel@4e { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "skin_msm_therm"; }; - pa-therm2@4f { + channel@4f { reg = ; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "pa_therm2"; }; }; -- cgit v1.2.3-59-g8ed1b From 8cd5597a9b18b890c743f50cfc5237fc74c6b9a0 Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Tue, 1 Aug 2023 21:15:50 -0400 Subject: arm64: dts: qcom: sdm670: add osm l3 Add the interconnect node for L3 cache on SDM670. Signed-off-by: Richard Acayan Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230802011548.387519-8-mailingradian@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index a1c207c0266d..45f9633d2d2c 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -1354,5 +1354,15 @@ interrupts = ; #interrupt-cells = <3>; }; + + osm_l3: interconnect@17d41000 { + compatible = "qcom,sdm670-osm-l3", "qcom,osm-l3"; + reg = <0 0x17d41000 0 0x1400>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + }; }; }; -- cgit v1.2.3-59-g8ed1b From 0c665213d12641a88241297eb383e5f1123e424e Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Tue, 1 Aug 2023 21:15:51 -0400 Subject: arm64: dts: qcom: sdm670: add cpu frequency scaling Add CPU frequency scaling, and also add the corresponding memory and cache bandwidths for each frequency. Signed-off-by: Richard Acayan Link: https://lore.kernel.org/r/20230802011548.387519-9-mailingradian@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 149 +++++++++++++++++++++++++++++++++++ 1 file changed, 149 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index 45f9633d2d2c..e1ef3fc2ace0 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -35,6 +36,10 @@ compatible = "qcom,kryo360"; reg = <0x0 0x0>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; next-level-cache = <&L2_0>; @@ -56,6 +61,10 @@ compatible = "qcom,kryo360"; reg = <0x0 0x100>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD1>; power-domain-names = "psci"; next-level-cache = <&L2_100>; @@ -72,6 +81,10 @@ compatible = "qcom,kryo360"; reg = <0x0 0x200>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD2>; power-domain-names = "psci"; next-level-cache = <&L2_200>; @@ -88,6 +101,10 @@ compatible = "qcom,kryo360"; reg = <0x0 0x300>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD3>; power-domain-names = "psci"; next-level-cache = <&L2_300>; @@ -104,6 +121,10 @@ compatible = "qcom,kryo360"; reg = <0x0 0x400>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD4>; power-domain-names = "psci"; next-level-cache = <&L2_400>; @@ -120,6 +141,10 @@ compatible = "qcom,kryo360"; reg = <0x0 0x500>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD5>; power-domain-names = "psci"; next-level-cache = <&L2_500>; @@ -136,6 +161,10 @@ compatible = "qcom,kryo360"; reg = <0x0 0x600>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu6_opp_table>; + interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD6>; power-domain-names = "psci"; next-level-cache = <&L2_600>; @@ -152,6 +181,10 @@ compatible = "qcom,kryo360"; reg = <0x0 0x700>; enable-method = "psci"; + qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu6_opp_table>; + interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD7>; power-domain-names = "psci"; next-level-cache = <&L2_700>; @@ -246,6 +279,111 @@ reg = <0x0 0x80000000 0x0 0x0>; }; + cpu0_opp_table: opp-table-cpu0 { + compatible = "operating-points-v2"; + opp-shared; + + cpu0_opp1: opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-peak-kBps = <400000 4800000>; + }; + + cpu0_opp2: opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + opp-peak-kBps = <400000 4800000>; + }; + + cpu0_opp3: opp-748800000 { + opp-hz = /bits/ 64 <748800000>; + opp-peak-kBps = <1200000 4800000>; + }; + + cpu0_opp4: opp-998400000 { + opp-hz = /bits/ 64 <998400000>; + opp-peak-kBps = <1804000 8908800>; + }; + + cpu0_opp5: opp-1209600000 { + opp-hz = /bits/ 64 <1209600000>; + opp-peak-kBps = <2188000 8908800>; + }; + + cpu0_opp6: opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + opp-peak-kBps = <2188000 13516800>; + }; + + cpu0_opp7: opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + opp-peak-kBps = <3072000 15052800>; + }; + + cpu0_opp8: opp-1612800000 { + opp-hz = /bits/ 64 <1612800000>; + opp-peak-kBps = <3072000 22118400>; + }; + + cpu0_opp9: opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <4068000 23040000>; + }; + }; + + cpu6_opp_table: opp-table-cpu6 { + compatible = "operating-points-v2"; + opp-shared; + + cpu6_opp1: opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-peak-kBps = <400000 4800000>; + }; + + cpu6_opp2: opp-652800000 { + opp-hz = /bits/ 64 <652800000>; + opp-peak-kBps = <400000 4800000>; + }; + + cpu6_opp3: opp-825600000 { + opp-hz = /bits/ 64 <825600000>; + opp-peak-kBps = <1200000 4800000>; + }; + + cpu6_opp4: opp-979200000 { + opp-hz = /bits/ 64 <979200000>; + opp-peak-kBps = <1200000 4800000>; + }; + + cpu6_opp5: opp-1132800000 { + opp-hz = /bits/ 64 <1132800000>; + opp-peak-kBps = <2188000 8908800>; + }; + + cpu6_opp6: opp-1363200000 { + opp-hz = /bits/ 64 <1363200000>; + opp-peak-kBps = <4068000 12902400>; + }; + + cpu6_opp7: opp-1536000000 { + opp-hz = /bits/ 64 <1536000000>; + opp-peak-kBps = <4068000 12902400>; + }; + + cpu6_opp8: opp-1747200000 { + opp-hz = /bits/ 64 <1747200000>; + opp-peak-kBps = <4068000 15052800>; + }; + + cpu6_opp9: opp-1843200000 { + opp-hz = /bits/ 64 <1843200000>; + opp-peak-kBps = <4068000 15052800>; + }; + + cpu6_opp10: opp-1996800000 { + opp-hz = /bits/ 64 <1996800000>; + opp-peak-kBps = <6220000 19046400>; + }; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -1364,5 +1502,16 @@ #interconnect-cells = <1>; }; + + cpufreq_hw: cpufreq@17d43000 { + compatible = "qcom,cpufreq-hw"; + reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; + reg-names = "freq-domain0", "freq-domain1"; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + }; }; }; -- cgit v1.2.3-59-g8ed1b From 605a981e53dc226f0b654b3aa74c303e5ca7c051 Mon Sep 17 00:00:00 2001 From: Richard Acayan Date: Tue, 1 Aug 2023 21:15:52 -0400 Subject: arm64: dts: qcom: sdm670: add frequency profile Add the coefficients for the CPU frequencies to aid in frequency scaling. Profiling setup: - freqbench (https://github.com/kdrag0n/freqbench) - LineageOS kernel, android_kernel_google_msm-4.9 - recommended configuration options by freqbench - disabled options that require clang or 32-bit compilers - mmc governor switched from simple_ondemand to powersave Frequency domains: cpu1 cpu6 Offline CPUs: cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 Sampling power every 1000 ms Baseline power usage: 445 mW ===== CPU 1 ===== Frequencies: 300 576 748 998 1209 1324 1516 1612 1708 300: 1114 3.7 C/MHz 43 mW 11.6 J 25.8 I/mJ 269.4 s 576: 2138 3.7 C/MHz 51 mW 7.1 J 42.2 I/mJ 140.3 s 748: 2780 3.7 C/MHz 67 mW 7.3 J 41.3 I/mJ 107.9 s 998: 3706 3.7 C/MHz 73 mW 5.9 J 51.1 I/mJ 80.9 s 1209: 4490 3.7 C/MHz 86 mW 5.7 J 52.2 I/mJ 66.8 s 1324: 4918 3.7 C/MHz 90 mW 5.5 J 54.6 I/mJ 61.0 s 1516: 5631 3.7 C/MHz 103 mW 5.5 J 54.9 I/mJ 53.3 s 1612: 5987 3.7 C/MHz 109 mW 5.5 J 55.0 I/mJ 50.1 s 1708: 6344 3.7 C/MHz 126 mW 5.9 J 50.5 I/mJ 47.3 s ===== CPU 6 ===== Frequencies: 300 652 825 979 1132 1363 1536 1747 1843 1996 300: 1868 6.2 C/MHz 53 mW 8.5 J 35.2 I/mJ 160.6 s 652: 4073 6.2 C/MHz 96 mW 7.1 J 42.4 I/mJ 73.7 s 825: 5132 6.2 C/MHz 117 mW 6.9 J 43.7 I/mJ 58.5 s 979: 6099 6.2 C/MHz 151 mW 7.4 J 40.4 I/mJ 49.2 s 1132: 7071 6.2 C/MHz 207 mW 8.8 J 34.1 I/mJ 42.4 s 1363: 8482 6.2 C/MHz 235 mW 8.3 J 36.1 I/mJ 35.4 s 1536: 9578 6.2 C/MHz 287 mW 9.0 J 33.3 I/mJ 31.3 s 1747: 10892 6.2 C/MHz 340 mW 9.4 J 32.0 I/mJ 27.6 s 1843: 11471 6.2 C/MHz 368 mW 9.6 J 31.1 I/mJ 26.2 s 1996: 12425 6.2 C/MHz 438 mW 10.6 J 28.3 I/mJ 24.2 s Signed-off-by: Richard Acayan Link: https://lore.kernel.org/r/20230802011548.387519-10-mailingradian@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index e1ef3fc2ace0..0ac39d3d68ca 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -36,6 +36,8 @@ compatible = "qcom,kryo360"; reg = <0x0 0x0>; enable-method = "psci"; + capacity-dmips-mhz = <610>; + dynamic-power-coefficient = <203>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, @@ -61,6 +63,8 @@ compatible = "qcom,kryo360"; reg = <0x0 0x100>; enable-method = "psci"; + capacity-dmips-mhz = <610>; + dynamic-power-coefficient = <203>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, @@ -81,6 +85,8 @@ compatible = "qcom,kryo360"; reg = <0x0 0x200>; enable-method = "psci"; + capacity-dmips-mhz = <610>; + dynamic-power-coefficient = <203>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, @@ -101,6 +107,8 @@ compatible = "qcom,kryo360"; reg = <0x0 0x300>; enable-method = "psci"; + capacity-dmips-mhz = <610>; + dynamic-power-coefficient = <203>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, @@ -121,6 +129,8 @@ compatible = "qcom,kryo360"; reg = <0x0 0x400>; enable-method = "psci"; + capacity-dmips-mhz = <610>; + dynamic-power-coefficient = <203>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, @@ -141,6 +151,8 @@ compatible = "qcom,kryo360"; reg = <0x0 0x500>; enable-method = "psci"; + capacity-dmips-mhz = <610>; + dynamic-power-coefficient = <203>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, @@ -161,6 +173,8 @@ compatible = "qcom,kryo360"; reg = <0x0 0x600>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <393>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu6_opp_table>; interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, @@ -181,6 +195,8 @@ compatible = "qcom,kryo360"; reg = <0x0 0x700>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <393>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu6_opp_table>; interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, -- cgit v1.2.3-59-g8ed1b From e85cbb34f3eabc27d6e77cfde6c9afbab3d70b4b Mon Sep 17 00:00:00 2001 From: Eric Chanudet Date: Wed, 9 Aug 2023 16:32:33 -0400 Subject: arm64: dts: qcom: sa8540p-ride: enable rtc SA8540P-ride is one of the Qualcomm platforms that does not have access to UEFI runtime services and on which the RTC registers are read-only, as described in: https://lore.kernel.org/all/20230202155448.6715-1-johan+linaro@kernel.org/ Reserve four bytes in one of the PMIC registers to hold the RTC offset the same way as it was done for sc8280xp-crd which has similar limitations: commit e67b45582c5e ("arm64: dts: qcom: sc8280xp-crd: enable rtc") On SA8540P-ride, the register bank SDAM6 of the first PMIC is not writable. Following recommendations provided during the review, use SDAM2 from the second PMIC at offset 0xa0 instead. Reviewed-by: Caleb Connolly Signed-off-by: Eric Chanudet Link: https://lore.kernel.org/r/20230809203506.1833205-1-echanude@redhat.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8540p-pmics.dtsi | 11 ++++++++++- arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 15 +++++++++++++++ 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sa8540p-pmics.dtsi b/arch/arm64/boot/dts/qcom/sa8540p-pmics.dtsi index 1221be89b3de..a1fbb477fafe 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8540p-pmics.dtsi @@ -14,7 +14,7 @@ #address-cells = <1>; #size-cells = <0>; - rtc@6000 { + pmm8540a_rtc: rtc@6000 { compatible = "qcom,pm8941-rtc"; reg = <0x6000>, <0x6100>; reg-names = "rtc", "alarm"; @@ -39,6 +39,15 @@ #address-cells = <1>; #size-cells = <0>; + pmm8540c_sdam_2: nvram@b110 { + compatible = "qcom,spmi-sdam"; + reg = <0xb110>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xb110 0xb0>; + status = "disabled"; + }; + pmm8540c_gpios: gpio@c000 { compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio"; reg = <0xc000>; diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts index 5a26974dcf8f..b04f72ec097c 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -407,6 +407,21 @@ status = "okay"; }; +&pmm8540a_rtc { + nvmem-cells = <&rtc_offset>; + nvmem-cell-names = "offset"; + + status = "okay"; +}; + +&pmm8540c_sdam_2 { + status = "okay"; + + rtc_offset: rtc-offset@a0 { + reg = <0xa0 0x4>; + }; +}; + &qup0 { status = "okay"; }; -- cgit v1.2.3-59-g8ed1b From 5480b0c67f120a6c293cc5eff72fa1d6a74de504 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Wed, 9 Aug 2023 21:35:34 +0100 Subject: arm64: dts: qcom: sdm845: Enable CAMSS on the bare rb3 board Enable CAMSS on the standard RB3 as it is possible to run the test pattern generator (TPG) without any populated ports/endpoints. media-ctl --reset yavta --no-query -w '0x009f0903 9' /dev/v4l-subdev4 yavta --list /dev/v4l-subdev4 media-ctl -d /dev/media0 -V '"msm_csid0":0[fmt:SGRBG10_1X10/3280x2464]' media-ctl -d /dev/media0 -V '"msm_vfe0_rdi0":0[fmt:SGRBG10_1X10/3280x2464]' media-ctl -l '"msm_csid0":1->"msm_vfe0_rdi0":0[1]' media-ctl -d /dev/media0 -p yavta -B capture-mplane --capture=5 -n 5 -I -f SGRBG10P -s 3280x2464 --file=TPG-SGRBG10-3280x2464-000-#.bin /dev/video2 Signed-off-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20230809203534.1100030-2-bryan.odonoghue@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index d6b464cb61d6..14f9afbd75e5 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -410,6 +410,13 @@ }; }; +&camss { + status = "okay"; + + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l26a_1p2>; +}; + &cdsp_pas { status = "okay"; firmware-name = "qcom/sdm845/cdsp.mbn"; -- cgit v1.2.3-59-g8ed1b From 31cd8caf0cbe191c0157c1581a8f0b82b891960d Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 10 Aug 2023 10:09:01 +0200 Subject: arm64: dts: qcom: sa8775p: add a node for the second serdes PHY Add a node for the SerDes PHY used by EMAC1 on sa8775p-ride. Signed-off-by: Bartosz Golaszewski Reviewed-by: Andrew Halaney Reviewed-by: Konrad Dybcio Tested-by: Andrew Halaney Link: https://lore.kernel.org/r/20230810080909.6259-2-brgl@bgdev.pl Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 7b55cb701472..38d10af37ab0 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -1846,6 +1846,15 @@ status = "disabled"; }; + serdes1: phy@8902000 { + compatible = "qcom,sa8775p-dwmac-sgmii-phy"; + reg = <0x0 0x08902000 0x0 0xe10>; + clocks = <&gcc GCC_SGMI_CLKREF_EN>; + clock-names = "sgmi_ref"; + #phy-cells = <0>; + status = "disabled"; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sa8775p-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x30000>, -- cgit v1.2.3-59-g8ed1b From e952348a7cc7b35883bdd43d73b8c9b296936547 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 10 Aug 2023 10:09:02 +0200 Subject: arm64: dts: qcom: sa8775p: add a node for EMAC1 Add a node for the second MAC on sa8775p platforms. Signed-off-by: Bartosz Golaszewski Reviewed-by: Andrew Halaney Reviewed-by: Konrad Dybcio Tested-by: Andrew Halaney Link: https://lore.kernel.org/r/20230810080909.6259-3-brgl@bgdev.pl Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 38d10af37ab0..73fd8a0c0320 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -2325,6 +2325,39 @@ #freq-domain-cells = <1>; }; + ethernet1: ethernet@23000000 { + compatible = "qcom,sa8775p-ethqos"; + reg = <0x0 0x23000000 0x0 0x10000>, + <0x0 0x23016000 0x0 0x100>; + reg-names = "stmmaceth", "rgmii"; + + interrupts = ; + interrupt-names = "macirq"; + + clocks = <&gcc GCC_EMAC1_AXI_CLK>, + <&gcc GCC_EMAC1_SLV_AHB_CLK>, + <&gcc GCC_EMAC1_PTP_CLK>, + <&gcc GCC_EMAC1_PHY_AUX_CLK>; + clock-names = "stmmaceth", + "pclk", + "ptp_ref", + "phyaux"; + + power-domains = <&gcc EMAC1_GDSC>; + + phys = <&serdes1>; + phy-names = "serdes"; + + iommus = <&apps_smmu 0x140 0xf>; + + snps,tso; + snps,pbl = <32>; + rx-fifo-depth = <16384>; + tx-fifo-depth = <16384>; + + status = "disabled"; + }; + ethernet0: ethernet@23040000 { compatible = "qcom,sa8775p-ethqos"; reg = <0x0 0x23040000 0x0 0x10000>, -- cgit v1.2.3-59-g8ed1b From 6ca89cc6803b3895a0b2caba458dbece9b6ea52b Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 10 Aug 2023 10:09:03 +0200 Subject: arm64: dts: qcom: sa8775p-ride: enable the second SerDes PHY Enable the second SerDes PHY on sa8775p-ride development board. Signed-off-by: Bartosz Golaszewski Reviewed-by: Andrew Halaney Reviewed-by: Konrad Dybcio Tested-by: Andrew Halaney Link: https://lore.kernel.org/r/20230810080909.6259-4-brgl@bgdev.pl Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index 1cd7707e1eb3..8eb133c8245f 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -448,6 +448,11 @@ status = "okay"; }; +&serdes1 { + phy-supply = <&vreg_l5a>; + status = "okay"; +}; + &sleep_clk { clock-frequency = <32764>; }; -- cgit v1.2.3-59-g8ed1b From 5255901fb26efcb91eee1739aded174ff6c6443e Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 10 Aug 2023 10:09:04 +0200 Subject: arm64: dts: qcom: sa8775p-ride: move the reset-gpios property of the PHY Device-tree bindings for MDIO define per-PHY reset-gpios as well as a global reset-gpios property at the MDIO node level which controls all devices on the bus. The latter is most likely a workaround for the chicken-and-egg problem where we cannot read the ID of the PHY before bringing it out of reset but we cannot bring it out of reset until we've read its ID. I have proposed a comprehensive solution for this problem in 2020 but it never got upstream. We do however have workaround in place which allows us to hard-code the PHY id in the compatible property, thus skipping the ID scanning. Let's make the device-tree for sa8775p-ride slightly more correct by moving the reset-gpios property to the PHY node with its ID put into the PHY node's compatible. Link: https://lore.kernel.org/all/20200622093744.13685-1-brgl@bgdev.pl/ Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Tested-by: Andrew Halaney Link: https://lore.kernel.org/r/20230810080909.6259-5-brgl@bgdev.pl Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index 8eb133c8245f..457182510412 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -279,13 +279,13 @@ #address-cells = <1>; #size-cells = <0>; - reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>; - reset-delay-us = <11000>; - reset-post-delay-us = <70000>; - sgmii_phy: phy@8 { + compatible = "ethernet-phy-id0141.0dd4"; reg = <0x8>; device_type = "ethernet-phy"; + reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; }; }; -- cgit v1.2.3-59-g8ed1b From 1e7ef41b5fa7de8de746a5d6cb7c96c409888c53 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 10 Aug 2023 10:09:05 +0200 Subject: arm64: dts: qcom: sa8775p-ride: index the first SGMII PHY We'll be adding a second SGMII PHY on the same MDIO bus, so let's index the first one for better readability. Signed-off-by: Bartosz Golaszewski Reviewed-by: Andrew Halaney Reviewed-by: Konrad Dybcio Tested-by: Andrew Halaney Link: https://lore.kernel.org/r/20230810080909.6259-6-brgl@bgdev.pl Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index 457182510412..fa32190a960f 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -263,7 +263,7 @@ ðernet0 { phy-mode = "sgmii"; - phy-handle = <&sgmii_phy>; + phy-handle = <&sgmii_phy0>; pinctrl-0 = <ðernet0_default>; pinctrl-names = "default"; @@ -279,7 +279,7 @@ #address-cells = <1>; #size-cells = <0>; - sgmii_phy: phy@8 { + sgmii_phy0: phy@8 { compatible = "ethernet-phy-id0141.0dd4"; reg = <0x8>; device_type = "ethernet-phy"; -- cgit v1.2.3-59-g8ed1b From 1a00a068de4a657a2af53943d446b7b7199b5871 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 10 Aug 2023 10:09:06 +0200 Subject: arm64: dts: qcom: sa8775p-ride: add the second SGMII PHY Add a second SGMII PHY that will be used by EMAC1 on sa8775p-ride. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Tested-by: Andrew Halaney Link: https://lore.kernel.org/r/20230810080909.6259-7-brgl@bgdev.pl Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index fa32190a960f..bcf4101622dc 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -287,6 +287,15 @@ reset-assert-us = <11000>; reset-deassert-us = <70000>; }; + + sgmii_phy1: phy@a { + compatible = "ethernet-phy-id0141.0dd4"; + reg = <0xa>; + device_type = "ethernet-phy"; + reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + }; }; mtl_rx_setup: rx-queues-config { -- cgit v1.2.3-59-g8ed1b From f8be0c50ce0e5bc38938fb1a7405288cf3fc96ac Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 10 Aug 2023 10:09:07 +0200 Subject: arm64: dts: qcom: sa8775p-ride: sort aliases alphabetically For improved readability order the aliases alphabetically for sa8775p-ride. Signed-off-by: Bartosz Golaszewski Suggested-by: Konrad Dybcio Reviewed-by: Konrad Dybcio Tested-by: Andrew Halaney Link: https://lore.kernel.org/r/20230810080909.6259-8-brgl@bgdev.pl Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index bcf4101622dc..fb5c7b279301 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -16,11 +16,11 @@ compatible = "qcom,sa8775p-ride", "qcom,sa8775p"; aliases { + i2c11 = &i2c11; + i2c18 = &i2c18; serial0 = &uart10; serial1 = &uart12; serial2 = &uart17; - i2c11 = &i2c11; - i2c18 = &i2c18; spi16 = &spi16; ufshc1 = &ufs_mem_hc; }; -- cgit v1.2.3-59-g8ed1b From fdc051e3926ee52b43f16dc3d6f35f40f8a5d3c3 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 10 Aug 2023 10:09:08 +0200 Subject: arm64: dts: qcom: sa8775p-ride: add an alias for ethernet0 Once we add a second ethernet node, the MDIO bus names will conflict unless we provide aliases. Add one for the existing ethernet node. Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Tested-by: Andrew Halaney Link: https://lore.kernel.org/r/20230810080909.6259-9-brgl@bgdev.pl Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index fb5c7b279301..2caee299d410 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -16,6 +16,7 @@ compatible = "qcom,sa8775p-ride", "qcom,sa8775p"; aliases { + ethernet0 = ðernet0; i2c11 = &i2c11; i2c18 = &i2c18; serial0 = &uart10; -- cgit v1.2.3-59-g8ed1b From 27eb552ef585c9852d1d04afde9fde34f8b69dc2 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 10 Aug 2023 10:09:09 +0200 Subject: arm64: dts: qcom: sa8775p-ride: enable EMAC1 Enable the second MAC on sa8775p-ride. Signed-off-by: Bartosz Golaszewski Tested-by: Andrew Halaney Link: https://lore.kernel.org/r/20230810080909.6259-10-brgl@bgdev.pl Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 71 +++++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index 2caee299d410..038d3a464bd9 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -17,6 +17,7 @@ aliases { ethernet0 = ðernet0; + ethernet1 = ðernet1; i2c11 = &i2c11; i2c18 = &i2c18; serial0 = &uart10; @@ -359,6 +360,76 @@ }; }; +ðernet1 { + phy-mode = "sgmii"; + phy-handle = <&sgmii_phy1>; + + snps,mtl-rx-config = <&mtl_rx_setup1>; + snps,mtl-tx-config = <&mtl_tx_setup1>; + snps,ps-speed = <1000>; + + status = "okay"; + + mtl_rx_setup1: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xc>; + }; + }; + + mtl_tx_setup1: tx-queues-config { + snps,tx-queues-to-use = <4>; + snps,tx-sched-sp; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + }; +}; + &i2c11 { clock-frequency = <400000>; pinctrl-0 = <&qup_i2c11_default>; -- cgit v1.2.3-59-g8ed1b From f62d184ef7970d42cb303b1f7201a98aea1a3b2f Mon Sep 17 00:00:00 2001 From: Sricharan Ramabadhran Date: Fri, 28 Jul 2023 14:03:07 +0530 Subject: dt-bindings: clock: Add IPQ5018 clock and reset This patch adds support for the global clock controller found on the IPQ5018 based devices. Reviewed-by: Krzysztof Kozlowski Co-developed-by: Varadarajan Narayanan Signed-off-by: Varadarajan Narayanan Signed-off-by: Sricharan Ramabadhran Link: https://lore.kernel.org/r/1690533192-22220-2-git-send-email-quic_srichara@quicinc.com Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,ipq5018-gcc.yaml | 63 +++++++ include/dt-bindings/clock/qcom,gcc-ipq5018.h | 183 +++++++++++++++++++++ include/dt-bindings/reset/qcom,gcc-ipq5018.h | 122 ++++++++++++++ 3 files changed, 368 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq5018.h create mode 100644 include/dt-bindings/reset/qcom,gcc-ipq5018.h diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml new file mode 100644 index 000000000000..ef84a0c95f7e --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq5018-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on IPQ5018 + +maintainers: + - Sricharan Ramabadhran + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on IPQ5018 + + See also:: + include/dt-bindings/clock/qcom,ipq5018-gcc.h + include/dt-bindings/reset/qcom,ipq5018-gcc.h + +properties: + compatible: + const: qcom,gcc-ipq5018 + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: PCIE20 PHY0 pipe clock source + - description: PCIE20 PHY1 pipe clock source + - description: USB3 PHY pipe clock source + - description: GEPHY RX clock source + - description: GEPHY TX clock source + - description: UNIPHY RX clock source + - description: UNIPHY TX clk source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + clock-controller@1800000 { + compatible = "qcom,gcc-ipq5018"; + reg = <0x01800000 0x80000>; + clocks = <&xo_board_clk>, + <&sleep_clk>, + <&pcie20_phy0_pipe_clk>, + <&pcie20_phy1_pipe_clk>, + <&usb3_phy0_pipe_clk>, + <&gephy_rx_clk>, + <&gephy_tx_clk>, + <&uniphy_rx_clk>, + <&uniphy_tx_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,gcc-ipq5018.h b/include/dt-bindings/clock/qcom,gcc-ipq5018.h new file mode 100644 index 000000000000..f3de2fdfeea1 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-ipq5018.h @@ -0,0 +1,183 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_5018_H +#define _DT_BINDINGS_CLOCK_IPQ_GCC_5018_H + +#define GPLL0_MAIN 0 +#define GPLL0 1 +#define GPLL2_MAIN 2 +#define GPLL2 3 +#define GPLL4_MAIN 4 +#define GPLL4 5 +#define UBI32_PLL_MAIN 6 +#define UBI32_PLL 7 +#define ADSS_PWM_CLK_SRC 8 +#define BLSP1_QUP1_I2C_APPS_CLK_SRC 9 +#define BLSP1_QUP1_SPI_APPS_CLK_SRC 10 +#define BLSP1_QUP2_I2C_APPS_CLK_SRC 11 +#define BLSP1_QUP2_SPI_APPS_CLK_SRC 12 +#define BLSP1_QUP3_I2C_APPS_CLK_SRC 13 +#define BLSP1_QUP3_SPI_APPS_CLK_SRC 14 +#define BLSP1_UART1_APPS_CLK_SRC 15 +#define BLSP1_UART2_APPS_CLK_SRC 16 +#define CRYPTO_CLK_SRC 17 +#define GCC_ADSS_PWM_CLK 18 +#define GCC_BLSP1_AHB_CLK 19 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 20 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 21 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 22 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 23 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 24 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 25 +#define GCC_BLSP1_UART1_APPS_CLK 26 +#define GCC_BLSP1_UART2_APPS_CLK 27 +#define GCC_BTSS_LPO_CLK 28 +#define GCC_CMN_BLK_AHB_CLK 29 +#define GCC_CMN_BLK_SYS_CLK 30 +#define GCC_CRYPTO_AHB_CLK 31 +#define GCC_CRYPTO_AXI_CLK 32 +#define GCC_CRYPTO_CLK 33 +#define GCC_CRYPTO_PPE_CLK 34 +#define GCC_DCC_CLK 35 +#define GCC_GEPHY_RX_CLK 36 +#define GCC_GEPHY_TX_CLK 37 +#define GCC_GMAC0_CFG_CLK 38 +#define GCC_GMAC0_PTP_CLK 39 +#define GCC_GMAC0_RX_CLK 40 +#define GCC_GMAC0_SYS_CLK 41 +#define GCC_GMAC0_TX_CLK 42 +#define GCC_GMAC1_CFG_CLK 43 +#define GCC_GMAC1_PTP_CLK 44 +#define GCC_GMAC1_RX_CLK 45 +#define GCC_GMAC1_SYS_CLK 46 +#define GCC_GMAC1_TX_CLK 47 +#define GCC_GP1_CLK 48 +#define GCC_GP2_CLK 49 +#define GCC_GP3_CLK 50 +#define GCC_LPASS_CORE_AXIM_CLK 51 +#define GCC_LPASS_SWAY_CLK 52 +#define GCC_MDIO0_AHB_CLK 53 +#define GCC_MDIO1_AHB_CLK 54 +#define GCC_PCIE0_AHB_CLK 55 +#define GCC_PCIE0_AUX_CLK 56 +#define GCC_PCIE0_AXI_M_CLK 57 +#define GCC_PCIE0_AXI_S_BRIDGE_CLK 58 +#define GCC_PCIE0_AXI_S_CLK 59 +#define GCC_PCIE0_PIPE_CLK 60 +#define GCC_PCIE1_AHB_CLK 61 +#define GCC_PCIE1_AUX_CLK 62 +#define GCC_PCIE1_AXI_M_CLK 63 +#define GCC_PCIE1_AXI_S_BRIDGE_CLK 64 +#define GCC_PCIE1_AXI_S_CLK 65 +#define GCC_PCIE1_PIPE_CLK 66 +#define GCC_PRNG_AHB_CLK 67 +#define GCC_Q6_AXIM_CLK 68 +#define GCC_Q6_AXIM2_CLK 69 +#define GCC_Q6_AXIS_CLK 70 +#define GCC_Q6_AHB_CLK 71 +#define GCC_Q6_AHB_S_CLK 72 +#define GCC_Q6_TSCTR_1TO2_CLK 73 +#define GCC_Q6SS_ATBM_CLK 74 +#define GCC_Q6SS_PCLKDBG_CLK 75 +#define GCC_Q6SS_TRIG_CLK 76 +#define GCC_QDSS_AT_CLK 77 +#define GCC_QDSS_CFG_AHB_CLK 78 +#define GCC_QDSS_DAP_AHB_CLK 79 +#define GCC_QDSS_DAP_CLK 80 +#define GCC_QDSS_ETR_USB_CLK 81 +#define GCC_QDSS_EUD_AT_CLK 82 +#define GCC_QDSS_STM_CLK 83 +#define GCC_QDSS_TRACECLKIN_CLK 84 +#define GCC_QDSS_TSCTR_DIV8_CLK 85 +#define GCC_QPIC_AHB_CLK 86 +#define GCC_QPIC_CLK 87 +#define GCC_QPIC_IO_MACRO_CLK 88 +#define GCC_SDCC1_AHB_CLK 89 +#define GCC_SDCC1_APPS_CLK 90 +#define GCC_SLEEP_CLK_SRC 91 +#define GCC_SNOC_GMAC0_AHB_CLK 92 +#define GCC_SNOC_GMAC0_AXI_CLK 93 +#define GCC_SNOC_GMAC1_AHB_CLK 94 +#define GCC_SNOC_GMAC1_AXI_CLK 95 +#define GCC_SNOC_LPASS_AXIM_CLK 96 +#define GCC_SNOC_LPASS_SWAY_CLK 97 +#define GCC_SNOC_UBI0_AXI_CLK 98 +#define GCC_SYS_NOC_PCIE0_AXI_CLK 99 +#define GCC_SYS_NOC_PCIE1_AXI_CLK 100 +#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 101 +#define GCC_SYS_NOC_USB0_AXI_CLK 102 +#define GCC_SYS_NOC_WCSS_AHB_CLK 103 +#define GCC_UBI0_AXI_CLK 104 +#define GCC_UBI0_CFG_CLK 105 +#define GCC_UBI0_CORE_CLK 106 +#define GCC_UBI0_DBG_CLK 107 +#define GCC_UBI0_NC_AXI_CLK 108 +#define GCC_UBI0_UTCM_CLK 109 +#define GCC_UNIPHY_AHB_CLK 110 +#define GCC_UNIPHY_RX_CLK 111 +#define GCC_UNIPHY_SYS_CLK 112 +#define GCC_UNIPHY_TX_CLK 113 +#define GCC_USB0_AUX_CLK 114 +#define GCC_USB0_EUD_AT_CLK 115 +#define GCC_USB0_LFPS_CLK 116 +#define GCC_USB0_MASTER_CLK 117 +#define GCC_USB0_MOCK_UTMI_CLK 118 +#define GCC_USB0_PHY_CFG_AHB_CLK 119 +#define GCC_USB0_SLEEP_CLK 120 +#define GCC_WCSS_ACMT_CLK 121 +#define GCC_WCSS_AHB_S_CLK 122 +#define GCC_WCSS_AXI_M_CLK 123 +#define GCC_WCSS_AXI_S_CLK 124 +#define GCC_WCSS_DBG_IFC_APB_BDG_CLK 125 +#define GCC_WCSS_DBG_IFC_APB_CLK 126 +#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK 127 +#define GCC_WCSS_DBG_IFC_ATB_CLK 128 +#define GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK 129 +#define GCC_WCSS_DBG_IFC_DAPBUS_CLK 130 +#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK 131 +#define GCC_WCSS_DBG_IFC_NTS_CLK 132 +#define GCC_WCSS_ECAHB_CLK 133 +#define GCC_XO_CLK 134 +#define GCC_XO_CLK_SRC 135 +#define GMAC0_RX_CLK_SRC 136 +#define GMAC0_TX_CLK_SRC 137 +#define GMAC1_RX_CLK_SRC 138 +#define GMAC1_TX_CLK_SRC 139 +#define GMAC_CLK_SRC 140 +#define GP1_CLK_SRC 141 +#define GP2_CLK_SRC 142 +#define GP3_CLK_SRC 143 +#define LPASS_AXIM_CLK_SRC 144 +#define LPASS_SWAY_CLK_SRC 145 +#define PCIE0_AUX_CLK_SRC 146 +#define PCIE0_AXI_CLK_SRC 147 +#define PCIE1_AUX_CLK_SRC 148 +#define PCIE1_AXI_CLK_SRC 149 +#define PCNOC_BFDCD_CLK_SRC 150 +#define Q6_AXI_CLK_SRC 151 +#define QDSS_AT_CLK_SRC 152 +#define QDSS_STM_CLK_SRC 153 +#define QDSS_TSCTR_CLK_SRC 154 +#define QDSS_TRACECLKIN_CLK_SRC 155 +#define QPIC_IO_MACRO_CLK_SRC 156 +#define SDCC1_APPS_CLK_SRC 157 +#define SYSTEM_NOC_BFDCD_CLK_SRC 158 +#define UBI0_AXI_CLK_SRC 159 +#define UBI0_CORE_CLK_SRC 160 +#define USB0_AUX_CLK_SRC 161 +#define USB0_LFPS_CLK_SRC 162 +#define USB0_MASTER_CLK_SRC 163 +#define USB0_MOCK_UTMI_CLK_SRC 164 +#define WCSS_AHB_CLK_SRC 165 +#define PCIE0_PIPE_CLK_SRC 166 +#define PCIE1_PIPE_CLK_SRC 167 +#define USB0_PIPE_CLK_SRC 168 +#define GCC_USB0_PIPE_CLK 169 +#define GMAC0_RX_DIV_CLK_SRC 170 +#define GMAC0_TX_DIV_CLK_SRC 171 +#define GMAC1_RX_DIV_CLK_SRC 172 +#define GMAC1_TX_DIV_CLK_SRC 173 +#endif diff --git a/include/dt-bindings/reset/qcom,gcc-ipq5018.h b/include/dt-bindings/reset/qcom,gcc-ipq5018.h new file mode 100644 index 000000000000..8f03c92fc23b --- /dev/null +++ b/include/dt-bindings/reset/qcom,gcc-ipq5018.h @@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_RESET_IPQ_GCC_5018_H +#define _DT_BINDINGS_RESET_IPQ_GCC_5018_H + +#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 0 +#define GCC_BLSP1_BCR 1 +#define GCC_BLSP1_QUP1_BCR 2 +#define GCC_BLSP1_QUP2_BCR 3 +#define GCC_BLSP1_QUP3_BCR 4 +#define GCC_BLSP1_UART1_BCR 5 +#define GCC_BLSP1_UART2_BCR 6 +#define GCC_BOOT_ROM_BCR 7 +#define GCC_BTSS_BCR 8 +#define GCC_CMN_BLK_BCR 9 +#define GCC_CMN_LDO_BCR 10 +#define GCC_CE_BCR 11 +#define GCC_CRYPTO_BCR 12 +#define GCC_DCC_BCR 13 +#define GCC_DCD_BCR 14 +#define GCC_DDRSS_BCR 15 +#define GCC_EDPD_BCR 16 +#define GCC_GEPHY_BCR 17 +#define GCC_GEPHY_MDC_SW_ARES 18 +#define GCC_GEPHY_DSP_HW_ARES 19 +#define GCC_GEPHY_RX_ARES 20 +#define GCC_GEPHY_TX_ARES 21 +#define GCC_GMAC0_BCR 22 +#define GCC_GMAC0_CFG_ARES 23 +#define GCC_GMAC0_SYS_ARES 24 +#define GCC_GMAC1_BCR 25 +#define GCC_GMAC1_CFG_ARES 26 +#define GCC_GMAC1_SYS_ARES 27 +#define GCC_IMEM_BCR 28 +#define GCC_LPASS_BCR 29 +#define GCC_MDIO0_BCR 30 +#define GCC_MDIO1_BCR 31 +#define GCC_MPM_BCR 32 +#define GCC_PCIE0_BCR 33 +#define GCC_PCIE0_LINK_DOWN_BCR 34 +#define GCC_PCIE0_PHY_BCR 35 +#define GCC_PCIE0PHY_PHY_BCR 36 +#define GCC_PCIE0_PIPE_ARES 37 +#define GCC_PCIE0_SLEEP_ARES 38 +#define GCC_PCIE0_CORE_STICKY_ARES 39 +#define GCC_PCIE0_AXI_MASTER_ARES 40 +#define GCC_PCIE0_AXI_SLAVE_ARES 41 +#define GCC_PCIE0_AHB_ARES 42 +#define GCC_PCIE0_AXI_MASTER_STICKY_ARES 43 +#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 44 +#define GCC_PCIE1_BCR 45 +#define GCC_PCIE1_LINK_DOWN_BCR 46 +#define GCC_PCIE1_PHY_BCR 47 +#define GCC_PCIE1PHY_PHY_BCR 48 +#define GCC_PCIE1_PIPE_ARES 49 +#define GCC_PCIE1_SLEEP_ARES 50 +#define GCC_PCIE1_CORE_STICKY_ARES 51 +#define GCC_PCIE1_AXI_MASTER_ARES 52 +#define GCC_PCIE1_AXI_SLAVE_ARES 53 +#define GCC_PCIE1_AHB_ARES 54 +#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 55 +#define GCC_PCIE1_AXI_SLAVE_STICKY_ARES 56 +#define GCC_PCNOC_BCR 57 +#define GCC_PCNOC_BUS_TIMEOUT0_BCR 58 +#define GCC_PCNOC_BUS_TIMEOUT1_BCR 59 +#define GCC_PCNOC_BUS_TIMEOUT2_BCR 60 +#define GCC_PCNOC_BUS_TIMEOUT3_BCR 61 +#define GCC_PCNOC_BUS_TIMEOUT4_BCR 62 +#define GCC_PCNOC_BUS_TIMEOUT5_BCR 63 +#define GCC_PCNOC_BUS_TIMEOUT6_BCR 64 +#define GCC_PCNOC_BUS_TIMEOUT7_BCR 65 +#define GCC_PCNOC_BUS_TIMEOUT8_BCR 66 +#define GCC_PCNOC_BUS_TIMEOUT9_BCR 67 +#define GCC_PCNOC_BUS_TIMEOUT10_BCR 68 +#define GCC_PCNOC_BUS_TIMEOUT11_BCR 69 +#define GCC_PRNG_BCR 70 +#define GCC_Q6SS_DBG_ARES 71 +#define GCC_Q6_AHB_S_ARES 72 +#define GCC_Q6_AHB_ARES 73 +#define GCC_Q6_AXIM2_ARES 74 +#define GCC_Q6_AXIM_ARES 75 +#define GCC_Q6_AXIS_ARES 76 +#define GCC_QDSS_BCR 77 +#define GCC_QPIC_BCR 78 +#define GCC_QUSB2_0_PHY_BCR 79 +#define GCC_SDCC1_BCR 80 +#define GCC_SEC_CTRL_BCR 81 +#define GCC_SPDM_BCR 82 +#define GCC_SYSTEM_NOC_BCR 83 +#define GCC_TCSR_BCR 84 +#define GCC_TLMM_BCR 85 +#define GCC_UBI0_AXI_ARES 86 +#define GCC_UBI0_AHB_ARES 87 +#define GCC_UBI0_NC_AXI_ARES 88 +#define GCC_UBI0_DBG_ARES 89 +#define GCC_UBI0_UTCM_ARES 90 +#define GCC_UBI0_CORE_ARES 91 +#define GCC_UBI32_BCR 92 +#define GCC_UNIPHY_BCR 93 +#define GCC_UNIPHY_AHB_ARES 94 +#define GCC_UNIPHY_SYS_ARES 95 +#define GCC_UNIPHY_RX_ARES 96 +#define GCC_UNIPHY_TX_ARES 97 +#define GCC_USB0_BCR 98 +#define GCC_USB0_PHY_BCR 99 +#define GCC_WCSS_BCR 100 +#define GCC_WCSS_DBG_ARES 101 +#define GCC_WCSS_ECAHB_ARES 102 +#define GCC_WCSS_ACMT_ARES 103 +#define GCC_WCSS_DBG_BDG_ARES 104 +#define GCC_WCSS_AHB_S_ARES 105 +#define GCC_WCSS_AXI_M_ARES 106 +#define GCC_WCSS_AXI_S_ARES 107 +#define GCC_WCSS_Q6_BCR 108 +#define GCC_WCSSAON_RESET 109 +#define GCC_UNIPHY_SOFT_RESET 110 +#define GCC_GEPHY_MISC_ARES 111 + +#endif -- cgit v1.2.3-59-g8ed1b From f8100504794f9d395f1e0d008033002bb5ba70c7 Mon Sep 17 00:00:00 2001 From: Sricharan Ramabadhran Date: Fri, 28 Jul 2023 14:03:09 +0530 Subject: dt-bindings: qcom: Add ipq5018 bindings Document the new ipq5018 SOC/board device tree bindings. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Sricharan Ramabadhran Link: https://lore.kernel.org/r/1690533192-22220-4-git-send-email-quic_srichara@quicinc.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index b1f2f015c127..adbfaea32343 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -30,6 +30,7 @@ description: | apq8084 apq8096 ipq4018 + ipq5018 ipq5332 ipq6018 ipq8074 @@ -105,6 +106,7 @@ description: | hk10-c2 idp liquid + rdp432-c2 mtp qrd rb2 @@ -341,6 +343,11 @@ properties: - qcom,ipq4019-dk04.1-c1 - const: qcom,ipq4019 + - items: + - enum: + - qcom,ipq5018-rdp432-c2 + - const: qcom,ipq5018 + - items: - enum: - qcom,ipq5332-ap-mi01.2 -- cgit v1.2.3-59-g8ed1b From 570006756a164526a784ba58e72844399f38366a Mon Sep 17 00:00:00 2001 From: Sricharan Ramabadhran Date: Fri, 28 Jul 2023 14:03:11 +0530 Subject: arm64: dts: Add ipq5018 SoC and rdp432-c2 board support Add initial device tree support for the Qualcomm IPQ5018 SoC and rdp432-c2 board. Few things like 'reboot' does not work because, couple of more 'SCM' APIS are needed to clear some TrustZone settings. Those will be posted separately. Reviewed-by: Krzysztof Kozlowski Co-developed-by: Varadarajan Narayanan Signed-off-by: Varadarajan Narayanan Co-developed-by: Gokul Sriram Palanisamy Signed-off-by: Gokul Sriram Palanisamy Signed-off-by: Sricharan Ramabadhran Link: https://lore.kernel.org/r/1690533192-22220-6-git-send-email-quic_srichara@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 72 +++++++ arch/arm64/boot/dts/qcom/ipq5018.dtsi | 250 +++++++++++++++++++++++++ 3 files changed, 323 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts create mode 100644 arch/arm64/boot/dts/qcom/ipq5018.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index f15548dbfa56..a4ac83a2d3a1 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8039-t2.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq5018-rdp432-c2.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp441.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp442.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts new file mode 100644 index 000000000000..e636a1cb9b77 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * IPQ5018 MP03.1-C2 board device tree source + * + * Copyright (c) 2023 The Linux Foundation. All rights reserved. + */ + +/dts-v1/; + +#include "ipq5018.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ5018/AP-RDP432.1-C2"; + compatible = "qcom,ipq5018-rdp432-c2", "qcom,ipq5018"; + + aliases { + serial0 = &blsp1_uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&blsp1_uart1 { + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdhc_1 { + pinctrl-0 = <&sdc_default_state>; + pinctrl-names = "default"; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + max-frequency = <192000000>; + bus-width = <4>; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&tlmm { + sdc_default_state: sdc-default-state { + clk-pins { + pins = "gpio9"; + function = "sdc1_clk"; + drive-strength = <8>; + bias-disable; + }; + + cmd-pins { + pins = "gpio8"; + function = "sdc1_cmd"; + drive-strength = <8>; + bias-pull-up; + }; + + data-pins { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + function = "sdc1_data"; + drive-strength = <8>; + bias-disable; + }; + }; +}; + +&xo_board_clk { + clock-frequency = <24000000>; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi new file mode 100644 index 000000000000..9f13d2dcdfd5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * IPQ5018 SoC device tree source + * + * Copyright (c) 2023 The Linux Foundation. All rights reserved. + */ + +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + #address-cells = <2>; + #size-cells = <2>; + + clocks { + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + xo_board_clk: xo-board-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-unified; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-ipq5018", "qcom,scm"; + }; + }; + + memory@40000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0x40000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + tz_region: tz@4ac00000 { + reg = <0x0 0x4ac00000 0x0 0x200000>; + no-map; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq5018-tlmm"; + reg = <0x01000000 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 47>; + interrupt-controller; + #interrupt-cells = <2>; + + uart1_pins: uart1-state { + pins = "gpio31", "gpio32", "gpio33", "gpio34"; + function = "blsp1_uart1"; + drive-strength = <8>; + bias-pull-down; + }; + }; + + gcc: clock-controller@1800000 { + compatible = "qcom,gcc-ipq5018"; + reg = <0x01800000 0x80000>; + clocks = <&xo_board_clk>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + sdhc_1: mmc@7804000 { + compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x7804000 0x1000>; + reg-names = "hc"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board_clk>; + clock-names = "iface", "core", "xo"; + non-removable; + status = "disabled"; + }; + + blsp1_uart1: serial@78af000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078af000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + reg = <0x0b000000 0x1000>, /* GICD */ + <0x0b002000 0x2000>, /* GICC */ + <0x0b001000 0x1000>, /* GICH */ + <0x0b004000 0x2000>; /* GICV */ + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0b00a000 0x1ffa>; + + v2m0: v2m@0 { + compatible = "arm,gic-v2m-frame"; + reg = <0x00000000 0xff8>; + msi-controller; + }; + + v2m1: v2m@1000 { + compatible = "arm,gic-v2m-frame"; + reg = <0x00001000 0xff8>; + msi-controller; + }; + }; + + timer@b120000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0b120000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + frame@b120000 { + reg = <0x0b121000 0x1000>, + <0x0b122000 0x1000>; + interrupts = , + ; + frame-number = <0>; + }; + + frame@b123000 { + reg = <0xb123000 0x1000>; + interrupts = ; + frame-number = <1>; + status = "disabled"; + }; + + frame@b124000 { + frame-number = <2>; + interrupts = ; + reg = <0x0b124000 0x1000>; + status = "disabled"; + }; + + frame@b125000 { + reg = <0x0b125000 0x1000>; + interrupts = ; + frame-number = <3>; + status = "disabled"; + }; + + frame@b126000 { + reg = <0x0b126000 0x1000>; + interrupts = ; + frame-number = <4>; + status = "disabled"; + }; + + frame@b127000 { + reg = <0x0b127000 0x1000>; + interrupts = ; + frame-number = <5>; + status = "disabled"; + }; + + frame@b128000 { + reg = <0x0b128000 0x1000>; + interrupts = ; + frame-number = <6>; + status = "disabled"; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; -- cgit v1.2.3-59-g8ed1b From 349a13a1e735ef84ff1af8e56a1309171f86f989 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Sat, 12 Aug 2023 00:47:32 +0100 Subject: arm64: dts: qcom: msm8916: Define CAMSS ports in core dtsi Each CSIPHY in CAMMS maps to a port here in the dtsi, since the number of CSIPHYs is fixed per SoC define the 8916 ports for both available PHYs. Signed-off-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230811234738.2859417-2-bryan.odonoghue@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index c4d673904698..33fb65d73104 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1712,6 +1712,14 @@ ports { #address-cells = <1>; #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; }; }; -- cgit v1.2.3-59-g8ed1b From 43a684580819e7f35b6cb38236be63c4cba26ef4 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Sat, 12 Aug 2023 00:47:33 +0100 Subject: arm64: dts: qcom: apq8016-sbc: Fix ov5640 regulator supply names The ov5640 driver expects DOVDD, AVDD and DVDD as regulator supply names. The ov5640 has depended on these names since the driver was committed upstream in 2017. Similarly apq8016-sbc.dtsi has had completely different regulator names since its own initial commit in 2020. Perhaps the regulators were left on in previous 410c bootloaders. In any case today on 6.5 we won't switch on the ov5640 without correctly naming the regulators. Fixes: 39e0ce6cd1bf ("arm64: dts: qcom: apq8016-sbc: Add CCI/Sensor nodes") Signed-off-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230811234738.2859417-3-bryan.odonoghue@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index f6eeb2598846..75b4e5ff7c95 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -282,9 +282,9 @@ clock-names = "xclk"; clock-frequency = <23880000>; - vdddo-supply = <&camera_vdddo_1v8>; - vdda-supply = <&camera_vdda_2v8>; - vddd-supply = <&camera_vddd_1v5>; + DOVDD-supply = <&camera_vdddo_1v8>; + AVDD-supply = <&camera_vdda_2v8>; + DVDD-supply = <&camera_vddd_1v5>; /* No camera mezzanine by default */ status = "disabled"; -- cgit v1.2.3-59-g8ed1b From 3652866ff493db60e2f767bd751fe15c1b4bd37a Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Sat, 12 Aug 2023 00:47:34 +0100 Subject: arm64: dts: qcom: apq8016-sbc: Fix ov5640 data-lanes declaration The yaml constraint for data-lanes is [1, 2] not [0, 2]. The driver itself doesn't do anything with the data-lanes declaration save count the number of specified data-lanes and calculate the link rate so, this change doesn't have any functional side-effects. Signed-off-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20230811234738.2859417-4-bryan.odonoghue@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index 75b4e5ff7c95..0481a4a82090 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -291,7 +291,7 @@ port { ov5640_ep: endpoint { - data-lanes = <0 2>; + data-lanes = <1 2>; remote-endpoint = <&csiphy0_ep>; }; }; -- cgit v1.2.3-59-g8ed1b From 775d2f3f76b1de6d440d6071c61023ea71d88f69 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Sat, 12 Aug 2023 00:47:35 +0100 Subject: arm64: dts: qcom: apq8016-sbc: Set ov5640 assigned-clock The driver for the ov5640 doesn't do a set-rate, instead it expects the clock to already be set at an appropriate rate. Similarly the yaml for ov5640 doesn't understand clock-frequency. Convert from clock-rate to assigned-clock and assigned-clock-rate to remediate. Signed-off-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230811234738.2859417-5-bryan.odonoghue@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index 0481a4a82090..ada077756762 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -280,7 +280,8 @@ clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; clock-names = "xclk"; - clock-frequency = <23880000>; + assigned-clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; + assigned-clock-rates = <23880000>; DOVDD-supply = <&camera_vdddo_1v8>; AVDD-supply = <&camera_vdda_2v8>; -- cgit v1.2.3-59-g8ed1b From 4facccb44a82129195878750eed8f9890091c1b8 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Sat, 12 Aug 2023 00:47:36 +0100 Subject: arm64: dts: qcom: apq8016-sbc: Rename ov5640 enable-gpios to powerdown-gpios There are two control lines controlled by GPIO going into ov5640 - Reset - Powerdown The driver and yaml expect "reset-gpios" and "powerdown-gpios" there has never been an "enable-gpios". Fixes: 39e0ce6cd1bf ("arm64: dts: qcom: apq8016-sbc: Add CCI/Sensor nodes") Signed-off-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230811234738.2859417-6-bryan.odonoghue@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index ada077756762..ddb19709a9ee 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -273,7 +273,7 @@ compatible = "ovti,ov5640"; reg = <0x3b>; - enable-gpios = <&tlmm 34 GPIO_ACTIVE_HIGH>; + powerdown-gpios = <&tlmm 34 GPIO_ACTIVE_HIGH>; reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&camera_rear_default>; -- cgit v1.2.3-59-g8ed1b From 6823df31587707f5534663f04f80e40df3e709c4 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Sat, 12 Aug 2023 00:47:37 +0100 Subject: arm64: dts: qcom: apq8016-sbc-d3-camera-mezzanine: Move default ov5640 to a standalone dts At the moment we define a single ov5640 sensor in the apq8016-sbc and disable that sensor. The sensor mezzanine for this is a D3 Engineering Dual ov5640 mezzanine card. Move the definition from the apq8016-sbc where it shouldn't be to a standalone dts. Enables the sensor by default, as we are adding a standalone mezzanine structure. Signed-off-by: Bryan O'Donoghue Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230811234738.2859417-7-bryan.odonoghue@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../dts/qcom/apq8016-sbc-d3-camera-mezzanine.dts | 81 ++++++++++++++++++++++ arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 73 ------------------- 3 files changed, 82 insertions(+), 73 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/apq8016-sbc-d3-camera-mezzanine.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index a4ac83a2d3a1..2cca20563a1d 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb +dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc-d3-camera-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8039-t2.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc-d3-camera-mezzanine.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc-d3-camera-mezzanine.dts new file mode 100644 index 000000000000..c08b4be5cc7e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc-d3-camera-mezzanine.dts @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Ltd. + */ + +/dts-v1/; + +#include "apq8016-sbc.dts" + +/ { + camera_vdddo_1v8: camera-vdddo-1v8 { + compatible = "regulator-fixed"; + regulator-name = "camera_vdddo"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + camera_vdda_2v8: camera-vdda-2v8 { + compatible = "regulator-fixed"; + regulator-name = "camera_vdda"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + camera_vddd_1v5: camera-vddd-1v5 { + compatible = "regulator-fixed"; + regulator-name = "camera_vddd"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; +}; + +&camss { + status = "okay"; + + ports { + port@0 { + reg = <0>; + csiphy0_ep: endpoint { + data-lanes = <0 2>; + remote-endpoint = <&ov5640_ep>; + }; + }; + }; +}; + +&cci { + status = "okay"; +}; + +&cci_i2c0 { + camera_rear@3b { + compatible = "ovti,ov5640"; + reg = <0x3b>; + + powerdown-gpios = <&tlmm 34 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_rear_default>; + + clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "xclk"; + assigned-clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; + assigned-clock-rates = <23880000>; + + DOVDD-supply = <&camera_vdddo_1v8>; + AVDD-supply = <&camera_vdda_2v8>; + DVDD-supply = <&camera_vddd_1v5>; + + port { + ov5640_ep: endpoint { + data-lanes = <1 2>; + remote-endpoint = <&csiphy0_ep>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index ddb19709a9ee..c3cd08aa5c85 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -34,30 +34,6 @@ stdout-path = "serial0"; }; - camera_vdddo_1v8: camera-vdddo-1v8 { - compatible = "regulator-fixed"; - regulator-name = "camera_vdddo"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - camera_vdda_2v8: camera-vdda-2v8 { - compatible = "regulator-fixed"; - regulator-name = "camera_vdda"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - camera_vddd_1v5: camera-vddd-1v5 { - compatible = "regulator-fixed"; - regulator-name = "camera_vddd"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - reserved-memory { ramoops@bff00000 { compatible = "ramoops"; @@ -250,55 +226,6 @@ label = "LS-UART1"; }; -&camss { - status = "okay"; - ports { - port@0 { - reg = <0>; - csiphy0_ep: endpoint { - data-lanes = <0 2>; - remote-endpoint = <&ov5640_ep>; - status = "okay"; - }; - }; - }; -}; - -&cci { - status = "okay"; -}; - -&cci_i2c0 { - camera_rear@3b { - compatible = "ovti,ov5640"; - reg = <0x3b>; - - powerdown-gpios = <&tlmm 34 GPIO_ACTIVE_HIGH>; - reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&camera_rear_default>; - - clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; - clock-names = "xclk"; - assigned-clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; - assigned-clock-rates = <23880000>; - - DOVDD-supply = <&camera_vdddo_1v8>; - AVDD-supply = <&camera_vdda_2v8>; - DVDD-supply = <&camera_vddd_1v5>; - - /* No camera mezzanine by default */ - status = "disabled"; - - port { - ov5640_ep: endpoint { - data-lanes = <1 2>; - remote-endpoint = <&csiphy0_ep>; - }; - }; - }; -}; - &lpass { status = "okay"; }; -- cgit v1.2.3-59-g8ed1b From c27c73bb560bae279deae8cd94554832cee88116 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Sat, 12 Aug 2023 00:47:38 +0100 Subject: arm64: dts: qcom: apq8016-sbc: Enable camss for non-mezzanine cases When we have no camera mezzanine attached it is still possible to run the test-pattern generator of the CSID block. As an example: media-ctl --reset yavta --no-query -w '0x009f0903 1' /dev/v4l-subdev2 yavta --list /dev/v4l-subdev2 media-ctl -d /dev/media0 -V '"msm_csid0":0[fmt:UYVY8_1X16/1920x1080 field:none]' media-ctl -l '"msm_csid0":1->"msm_ispif0":0[1]' media-ctl -d /dev/media0 -V '"msm_ispif0":0[fmt:UYVY8_1X16/1920x1080 field:none]' media-ctl -l '"msm_ispif0":1->"msm_vfe0_rdi0":0[1]' media-ctl -d /dev/media0 -V '"msm_vfe0_rdi0":0[fmt:UYVY8_1X16/1920x1080]' media-ctl -d /dev/media0 -p yavta -B capture-mplane --capture=5 -n 5 -I -f UYVY -s 1920x1080 --file=TPG-UYVU-1920x1080-000-#.bin /dev/video0 Signed-off-by: Bryan O'Donoghue Link: https://lore.kernel.org/r/20230811234738.2859417-8-bryan.odonoghue@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/apq8016-sbc.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index c3cd08aa5c85..4f5541e9be0e 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -226,6 +226,10 @@ label = "LS-UART1"; }; +&camss { + status = "okay"; +}; + &lpass { status = "okay"; }; -- cgit v1.2.3-59-g8ed1b From 76a6dd7bfcbb91217e4429d73c14ee67b441137d Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 11 Aug 2023 22:50:58 +0200 Subject: arm64: dts: qcom: sm8450: Add PRNG Add the Qualcomm Pseudo-Random Number Generator. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230811-topic-8450_prng-v1-3-01becceeb1ee@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 4bc1c46a5f44..48618e88a273 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1738,6 +1738,11 @@ }; }; + rng: rng@10c3000 { + compatible = "qcom,sm8450-prng-ee", "qcom,prng-ee"; + reg = <0 0x010c3000 0 0x1000>; + }; + pcie0: pci@1c00000 { compatible = "qcom,pcie-sm8450-pcie0"; reg = <0 0x01c00000 0 0x3000>, -- cgit v1.2.3-59-g8ed1b From 0354e2d4d203bcffb61d671265f9f0bc52b244ff Mon Sep 17 00:00:00 2001 From: Sridharan S N Date: Fri, 16 Jun 2023 14:02:37 +0530 Subject: arm64: dts: qcom: ipq5332: enable GPIO based LEDs and Buttons Add support for wlan-2g LED on GPIO 36 and wps buttons on GPIO 35. Signed-off-by: Sridharan S N Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230616083238.20690-2-quic_sridsn@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi | 42 ++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi index f13dea7d67fe..4870cdb764d0 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi @@ -19,6 +19,31 @@ chosen { stdout-path = "serial0"; }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; + + button-wps { + label = "wps"; + linux,code = ; + gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&gpio_leds_default>; + pinctrl-names = "default"; + + led-0 { + gpios = <&tlmm 36 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + }; }; &blsp1_uart0 { @@ -34,3 +59,20 @@ &xo_board { clock-frequency = <24000000>; }; + +/* PINCTRL */ +&tlmm { + gpio_keys_default: gpio-keys-default-state { + pins = "gpio35"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + gpio_leds_default: gpio-leds-default-state { + pins = "gpio36"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + }; +}; -- cgit v1.2.3-59-g8ed1b From 238e192bedd9b57f8ed026788956387350f2ccb9 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 3 Jul 2023 20:20:05 +0200 Subject: dt-bindings: clk: qcom,gcc-msm8998: Add missing GPU/MMSS GPLL0 legs GPLL0 has two separate outputs to both GPUSS and MMSS: one that's 2-divided and one that runs at the same rate as the GPLL0 itself. Add the missing ones to the binding. Acked-by: Krzysztof Kozlowski Reviewed-by: Jeffrey Hugo Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230622-topic-8998clk-v2-1-6222fbc2916b@linaro.org Signed-off-by: Bjorn Andersson --- include/dt-bindings/clock/qcom,gcc-msm8998.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/clock/qcom,gcc-msm8998.h b/include/dt-bindings/clock/qcom,gcc-msm8998.h index 1badb4f9c58f..b5456a64d421 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8998.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8998.h @@ -190,6 +190,9 @@ #define AGGRE2_SNOC_NORTH_AXI 181 #define SSC_XO 182 #define SSC_CNOC_AHBS_CLK 183 +#define GCC_MMSS_GPLL0_DIV_CLK 184 +#define GCC_GPU_GPLL0_DIV_CLK 185 +#define GCC_GPU_GPLL0_CLK 186 #define PCIE_0_GDSC 0 #define UFS_GDSC 1 -- cgit v1.2.3-59-g8ed1b From 00ada6afea88006187b38bd96b6d1b7d8e3d90cb Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 3 Jul 2023 20:20:11 +0200 Subject: arm64: dts: qcom: msm8998: Use the correct GPLL0 leg for GPUCC GPUCC has its own GPLL0 leg, switch to it to allow shutting it down when it's unused. Reviewed-by: Jeffrey Hugo Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230622-topic-8998clk-v2-7-6222fbc2916b@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index a41a34dbcc3c..4605dd3a942d 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -1580,7 +1580,7 @@ reg = <0x05065000 0x9000>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, - <&gcc GPLL0_OUT_MAIN>; + <&gcc GCC_GPU_GPLL0_CLK>; clock-names = "xo", "gpll0"; }; -- cgit v1.2.3-59-g8ed1b From 63f4e4b447c50ba7e5fc3929644d2d152acb6117 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 3 Jul 2023 20:20:12 +0200 Subject: arm64: dts: qcom: msm8998: Use the correct GPLL0_DIV leg for MMCC MMCC has its own GPLL0 legs - one for 1-1 and one for div-2 output. We've already been using the correct one in the non-div case, start doing so for the other one as well. Reviewed-by: Jeffrey Hugo Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230622-topic-8998clk-v2-8-6222fbc2916b@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 4605dd3a942d..3f0a13bdc323 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -2724,7 +2724,8 @@ "dsi1byte", "hdmipll", "dplink", - "dpvco"; + "dpvco", + "gpll0_div"; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GCC_MMSS_GPLL0_CLK>, <0>, @@ -2733,7 +2734,8 @@ <0>, <0>, <0>, - <0>; + <0>, + <&gcc GCC_MMSS_GPLL0_DIV_CLK>; }; mmss_smmu: iommu@cd00000 { -- cgit v1.2.3-59-g8ed1b From 6578747ae2d76ce739ba81ffffb18b2222a87efb Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 11 Aug 2023 19:35:27 +0200 Subject: arm64: dts: qcom: sm8450: Add RPMh stats SM8450 also exposes RPMh stats, hook them up for low power state monitoring. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230811-topic-8450_stats-v1-1-f26ae3fdf2cf@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 48618e88a273..2a60cf8bd891 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3146,6 +3146,11 @@ #clock-cells = <0>; }; + sram@c3f0000 { + compatible = "qcom,rpmh-stats"; + reg = <0 0x0c3f0000 0 0x400>; + }; + spmi_bus: spmi@c400000 { compatible = "qcom,spmi-pmic-arb"; reg = <0 0x0c400000 0 0x00003000>, -- cgit v1.2.3-59-g8ed1b From a3ce236364b82688ca4c7605f63c4efd68e9589c Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 9 Aug 2023 21:20:24 +0200 Subject: arm64: dts: qcom: msm8998: Drop bus clock reference from MMSS SMMU The MMSS SMMU has been abusingly consuming the exposed RPM interconnect clock. Drop it. Fixes: 05ce21b54423 ("arm64: dts: qcom: msm8998: Configure the multimedia subsystem iommu") Reviewed-by: Jeffrey Hugo Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230531-topic-8998_mmssclk-v3-1-ba1b1fd9ee75@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 3f0a13bdc323..fd24ebbda8ac 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -2745,10 +2745,10 @@ clocks = <&mmcc MNOC_AHB_CLK>, <&mmcc BIMC_SMMU_AHB_CLK>, - <&rpmcc RPM_SMD_MMAXI_CLK>, <&mmcc BIMC_SMMU_AXI_CLK>; - clock-names = "iface-mm", "iface-smmu", - "bus-mm", "bus-smmu"; + clock-names = "iface-mm", + "iface-smmu", + "bus-smmu"; #global-interrupts = <0>; interrupts = -- cgit v1.2.3-59-g8ed1b From 7f828f3207142351750e9545527341425187de7b Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 9 Aug 2023 21:20:25 +0200 Subject: arm64: dts: qcom: msm8998: Add missing power domain to MMSS SMMU The MMSS SMMU has its own power domain. Attach it so that we can drop the "keep it always-on" hack. Fixes: 05ce21b54423 ("arm64: dts: qcom: msm8998: Configure the multimedia subsystem iommu") Reviewed-by: Jeffrey Hugo Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230531-topic-8998_mmssclk-v3-2-ba1b1fd9ee75@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index fd24ebbda8ac..d478f14b1643 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -2772,6 +2772,8 @@ , , ; + + power-domains = <&mmcc BIMC_SMMU_GDSC>; }; remoteproc_adsp: remoteproc@17300000 { -- cgit v1.2.3-59-g8ed1b From 1020fca4f2381cb59ffb40bb81e41913d6193b97 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Mon, 7 Aug 2023 19:08:47 +0530 Subject: arm64: dts: qcom: sdx75: Add spmi node Add SPMI node to SDX75 dtsi. Signed-off-by: Rohit Agarwal Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/1691415534-31820-3-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdx75.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index 7d39a615f4f7..a08284759af2 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -469,6 +469,29 @@ interrupt-controller; }; + spmi_bus: spmi@c400000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0 0x0c400000 0x0 0x3000>, + <0x0 0x0c500000 0x0 0x400000>, + <0x0 0x0c440000 0x0 0x80000>, + <0x0 0x0c4c0000 0x0 0x10000>, + <0x0 0x0c42d000 0x0 0x4000>; + reg-names = "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + qcom,ee = <0>; + qcom,channel = <0>; + qcom,bus-id = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + tlmm: pinctrl@f000000 { compatible = "qcom,sdx75-tlmm"; reg = <0x0 0x0f000000 0x0 0x400000>; -- cgit v1.2.3-59-g8ed1b From e99a7a0c85cc59ca271505180932882794f54ec3 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Mon, 7 Aug 2023 19:08:48 +0530 Subject: arm64: dts: qcom: Add pinctrl gpio support for pm7250b Add pinctrl gpio dts node for pm7250b. Signed-off-by: Rohit Agarwal Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/1691415534-31820-4-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm7250b.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm7250b.dtsi b/arch/arm64/boot/dts/qcom/pm7250b.dtsi index 22c0d5266179..e8540c36bd99 100644 --- a/arch/arm64/boot/dts/qcom/pm7250b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm7250b.dtsi @@ -147,6 +147,16 @@ #size-cells = <0>; status = "disabled"; }; + + pm7250b_gpios: pinctrl@c000 { + compatible = "qcom,pm7250b-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + gpio-ranges = <&pm7250b_gpios 0 0 12>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; pmic@3 { -- cgit v1.2.3-59-g8ed1b From 5f78e80ca7222a0c8da014400591fc70c8f6434a Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Mon, 7 Aug 2023 19:08:49 +0530 Subject: arm64: dts: qcom: Add pm7550ba PMIC dtsi Add dtsi for pm7550ba PMIC found in Qualcomm platforms. Signed-off-by: Rohit Agarwal Link: https://lore.kernel.org/r/1691415534-31820-5-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pm7550ba.dtsi | 70 ++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pm7550ba.dtsi diff --git a/arch/arm64/boot/dts/qcom/pm7550ba.dtsi b/arch/arm64/boot/dts/qcom/pm7550ba.dtsi new file mode 100644 index 000000000000..8b00ece987d1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm7550ba.dtsi @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +/ { + thermal-zones { + pm7550ba-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pm7550ba_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus { + pm7550ba: pmic@7 { + compatible = "qcom,pm7550ba", "qcom,spmi-pmic"; + reg = <7 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm7550ba_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm7550ba_gpios: gpio@8800 { + compatible = "qcom,pm7550ba-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm7550ba_gpios 0 0 8>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm7550ba_eusb2_repeater: phy@fd00 { + compatible = "qcom,pm7550ba-eusb2-repeater", "qcom,pm8550b-eusb2-repeater"; + reg = <0xfd00>; + #phy-cells = <0>; + }; + }; +}; -- cgit v1.2.3-59-g8ed1b From 0d64992d8589f21ac4997ef0acbf0d23ccb1f259 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Mon, 7 Aug 2023 19:08:50 +0530 Subject: arm64: dts: qcom: Add pmx75 PMIC dtsi Add dtsi for pmx75 PMIC found in Qualcomm platforms. Signed-off-by: Rohit Agarwal Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/1691415534-31820-6-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/pmx75.dtsi | 64 +++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pmx75.dtsi diff --git a/arch/arm64/boot/dts/qcom/pmx75.dtsi b/arch/arm64/boot/dts/qcom/pmx75.dtsi new file mode 100644 index 000000000000..373e45f63dff --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmx75.dtsi @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +/ { + thermal-zones { + pmx75-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pmx75_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus { + pmx75: pmic@1 { + compatible = "qcom,pmx75", "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmx75_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmx75_gpios: gpio@8800 { + compatible = "qcom,pmx75-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmx75_gpios 0 0 16>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; -- cgit v1.2.3-59-g8ed1b From f890ef18640d44ad7b9cc593706c0cf6b7e44d20 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Mon, 7 Aug 2023 19:08:52 +0530 Subject: arm64: dts: qcom: sdx75-idp: Add pmics supported in SDX75 SDX75-idp features pmk8550, pmx75 and pm7550ba pmic, so include them. Signed-off-by: Rohit Agarwal Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/1691415534-31820-8-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdx75-idp.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdx75-idp.dts b/arch/arm64/boot/dts/qcom/sdx75-idp.dts index cbe5cdf5a228..0da8c98c202e 100644 --- a/arch/arm64/boot/dts/qcom/sdx75-idp.dts +++ b/arch/arm64/boot/dts/qcom/sdx75-idp.dts @@ -6,6 +6,9 @@ /dts-v1/; #include "sdx75.dtsi" +#include "pm7550ba.dtsi" +#include "pmk8550.dtsi" +#include "pmx75.dtsi" / { model = "Qualcomm Technologies, Inc. SDX75 IDP"; -- cgit v1.2.3-59-g8ed1b From 1862d0e3eb1fcc863eb8c212abf99ce2923ee363 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Mon, 7 Aug 2023 19:08:53 +0530 Subject: arm64: dts: qcom: sdx75: Add rpmhpd node Add rpmhpd node and opps for this node to the SDX75 dts. Signed-off-by: Rohit Agarwal Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/1691415534-31820-9-git-send-email-quic_rohiagar@quicinc.com [bjorn: include qcom-rpmpd.h as well] Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdx75.dtsi | 52 +++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index a08284759af2..e180aa4023ec 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -9,6 +9,8 @@ #include #include #include +#include +#include #include / { @@ -666,6 +668,56 @@ clock-names = "xo"; #clock-cells = <1>; }; + + rpmhpd: power-controller { + compatible = "qcom,sdx75-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp-16 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp-48 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp-64 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp-128 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp-192 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp-256 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp-320 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp-336 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp-384 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp-416 { + opp-level = ; + }; + }; + }; }; cpufreq_hw: cpufreq@17d91000 { -- cgit v1.2.3-59-g8ed1b From 8a2dc39d1043deeef20bd3065ba8f958f81855ef Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Mon, 7 Aug 2023 19:08:54 +0530 Subject: arm64: dts: qcom: sdx75-idp: Add regulator nodes Add all the regulators along with labels found on SDX75 IDP. Signed-off-by: Rohit Agarwal Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/1691415534-31820-10-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdx75-idp.dts | 227 +++++++++++++++++++++++++++++++++ 1 file changed, 227 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdx75-idp.dts b/arch/arm64/boot/dts/qcom/sdx75-idp.dts index 0da8c98c202e..10d15871f2c4 100644 --- a/arch/arm64/boot/dts/qcom/sdx75-idp.dts +++ b/arch/arm64/boot/dts/qcom/sdx75-idp.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include #include "sdx75.dtsi" #include "pm7550ba.dtsi" #include "pmk8550.dtsi" @@ -17,6 +18,232 @@ aliases { serial0 = &uart1; }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + vph_ext: vph-ext-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_ext"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + vreg_bob_3p3: pmx75-bob { + compatible = "regulator-fixed"; + regulator-name = "vreg_bob_3p3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + vin-supply = <&vph_ext>; + }; +}; + +&apps_rsc { + pmx75-rpmh-regulators { + compatible = "qcom,pmx75-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-l1-supply = <&vreg_s2b_1p224>; + vdd-l2-l18-supply = <&vreg_s2b_1p224>; + vdd-l3-supply = <&vreg_s7b_0p936>; + vdd-l4-l16-supply = <&vreg_s7b_0p936>; + vdd-l5-l6-supply = <&vreg_s4b_1p824>; + vdd-l7-supply = <&vreg_s7b_0p936>; + vdd-l8-l9-supply = <&vreg_s8b_0p824>; + vdd-l10-supply = <&vreg_bob_3p3>; + vdd-l11-l13-supply = <&vreg_bob_3p3>; + vdd-l12-supply = <&vreg_s2b_1p224>; + vdd-l14-supply = <&vreg_s3b_0p752>; + vdd-l15-supply = <&vreg_s2b_1p224>; + vdd-l17-supply = <&vreg_s8b_0p824>; + vdd-l19-supply = <&vreg_s7b_0p936>; + vdd-l20-l21-supply = <&vreg_s7b_0p936>; + + vreg_s2b_1p224: smps2 { + regulator-name = "vreg_s2b_1p224"; + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1350000>; + }; + + vreg_s3b_0p752: smps3 { + regulator-name = "vreg_s3b_0p752"; + regulator-min-microvolt = <684000>; + regulator-max-microvolt = <904000>; + }; + + vreg_s4b_1p824: smps4 { + regulator-name = "vreg_s4b_1p824"; + regulator-min-microvolt = <1824000>; + regulator-max-microvolt = <1904000>; + }; + + vreg_s7b_0p936: smps7 { + regulator-name = "vreg_s7b_0p936"; + regulator-min-microvolt = <352000>; + regulator-max-microvolt = <1060000>; + }; + + vreg_s8b_0p824: smps8 { + regulator-name = "vreg_s8b_0p824"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1100000>; + }; + + vreg_l1b_1p2: ldo1 { + regulator-name = "vreg_l1b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l2b_1p128: ldo2 { + regulator-name = "vreg_l2b_1p128"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1160000>; + regulator-initial-mode = ; + }; + + vreg_l3b_0p896: ldo3 { + regulator-name = "vreg_l3b_0p896"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1040000>; + regulator-initial-mode = ; + }; + + vreg_l4b_0p88: ldo4 { + regulator-name = "vreg_l4b_0p88"; + regulator-min-microvolt = <864000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l5b_1p776: ldo5 { + regulator-name = "vreg_l5b_1p776"; + regulator-min-microvolt = <1770000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l7b_0p904: ldo7 { + regulator-name = "vreg_l7b_0p904"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <960000>; + regulator-initial-mode = ; + }; + + vreg_l8b_0p8: ldo8 { + regulator-name = "vreg_l8b_0p8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vreg_l9b_0p752: ldo9 { + regulator-name = "vreg_l9b_0p752"; + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vreg_l10b_3p08: ldo10 { + regulator-name = "vreg_l10b_3p08"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3088000>; + regulator-initial-mode = ; + }; + + vreg_l11b_1p8: ldo11 { + regulator-name = "vreg_l11b_1p8"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + vreg_l12b_1p2: ldo12 { + regulator-name = "vreg_l12b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l13b_1p8: ldo13 { + regulator-name = "vreg_l13b_1p8"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + vreg_l14b_0p624: ldo14 { + regulator-name = "vreg_l14b_0p624"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vreg_l15b_1p2: ldo15 { + regulator-name = "vreg_l15b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l16b_0p912: ldo16 { + regulator-name = "vreg_l16b_0p912"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l17b_0p752: ldo17 { + regulator-name = "vreg_l17b_0p752"; + regulator-min-microvolt = <684000>; + regulator-max-microvolt = <957600>; + regulator-initial-mode = ; + }; + + vreg_l19b_0p952: ldo19 { + regulator-name = "vreg_l19b_0p952"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <960000>; + regulator-initial-mode = ; + }; + + vreg_l20b_0p912: ldo20 { + regulator-name = "vreg_l20b_0p912"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <952000>; + regulator-initial-mode = ; + }; + + vreg_l21b_0p856: ldo21 { + regulator-name = "vreg_l21b_0p856"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = ; + }; + }; }; &chosen { -- cgit v1.2.3-59-g8ed1b From bd3b4ac11845b428996cfd2c7b8302ba6a07340d Mon Sep 17 00:00:00 2001 From: David Wronek Date: Sat, 5 Aug 2023 15:09:37 +0200 Subject: arm64: dts: qcom: msm8996: Fix dsi1 interrupts Fix IRQ flags mismatch which was keeping dsi1 from probing by changing interrupts = <4> to interrupts = <5>. Fixes: 2752bb7d9b58 ("arm64: dts: qcom: msm8996: add second DSI interface") Signed-off-by: David Wronek Acked-by: Yassine Oudjana Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230805130936.359860-2-davidwronek@gmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 6f7065e8fd6c..c8e0986425ab 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1126,7 +1126,7 @@ reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; - interrupts = <4>; + interrupts = <5>; clocks = <&mmcc MDSS_MDP_CLK>, <&mmcc MDSS_BYTE1_CLK>, -- cgit v1.2.3-59-g8ed1b From ff88e1c9dd8cbdbf5487a0e807866049cc5bb4d9 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Sat, 5 Aug 2023 14:26:44 +0200 Subject: arm64: dts: qcom: msm8998: Add DPU1 nodes Add the required nodes to support the display hardware on msm8998. Signed-off-by: AngeloGioacchino Del Regno [konrad: update the commit msg and AGdR's email, rebase] Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230805-topic-8998_dpu-v1-1-9d402dc1ecc0@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 283 +++++++++++++++++++++++++++++++++- 1 file changed, 279 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index d478f14b1643..f180047cacb0 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -316,6 +316,25 @@ }; }; + dsi_opp_table: opp-table-dsi { + compatible = "operating-points-v2"; + + opp-131250000 { + opp-hz = /bits/ 64 <131250000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-210000000 { + opp-hz = /bits/ 64 <210000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-312500000 { + opp-hz = /bits/ 64 <312500000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -2728,16 +2747,272 @@ "gpll0_div"; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GCC_MMSS_GPLL0_CLK>, - <0>, - <0>, - <0>, - <0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi1_phy 1>, + <&mdss_dsi1_phy 0>, <0>, <0>, <0>, <&gcc GCC_MMSS_GPLL0_DIV_CLK>; }; + mdss: display-subsystem@c900000 { + compatible = "qcom,msm8998-mdss"; + reg = <0x0c900000 0x1000>; + reg-names = "mdss"; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_MDP_CLK>; + clock-names = "iface", + "bus", + "core"; + + power-domains = <&mmcc MDSS_GDSC>; + iommus = <&mmss_smmu 0>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@c901000 { + compatible = "qcom,msm8998-dpu"; + reg = <0x0c901000 0x8f000>, + <0x0c9a8e00 0xf0>, + <0x0c9b0000 0x2008>, + <0x0c9b8000 0x1040>; + reg-names = "mdp", + "regdma", + "vbif", + "vbif_nrt"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MNOC_AHB_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "mnoc", + "core", + "vsync"; + + assigned-clocks = <&mmcc MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmpd MSM8998_VDDMX>; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-171430000 { + opp-hz = /bits/ 64 <171430000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-275000000 { + opp-hz = /bits/ 64 <275000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-330000000 { + opp-hz = /bits/ 64 <330000000>; + required-opps = <&rpmpd_opp_nom>; + }; + + opp-412500000 { + opp-hz = /bits/ 64 <412500000>; + required-opps = <&rpmpd_opp_turbo>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + + dpu_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + }; + }; + + mdss_dsi0: dsi@c994000 { + compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0c994000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_BYTE0_INTF_CLK>, + <&mmcc MDSS_PCLK0_CLK>, + <&mmcc MDSS_ESC0_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&mmcc BYTE0_CLK_SRC>, + <&mmcc PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmpd MSM8998_VDDCX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@c994400 { + compatible = "qcom,dsi-phy-10nm-8998"; + reg = <0x0c994400 0x200>, + <0x0c994600 0x280>, + <0x0c994a00 0x1e0>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss_dsi1: dsi@c996000 { + compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0c996000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&mmcc MDSS_BYTE1_CLK>, + <&mmcc MDSS_BYTE1_INTF_CLK>, + <&mmcc MDSS_PCLK1_CLK>, + <&mmcc MDSS_ESC1_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&mmcc BYTE1_CLK_SRC>, + <&mmcc PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmpd MSM8998_VDDCX>; + + phys = <&mdss_dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@c996400 { + compatible = "qcom,dsi-phy-10nm-8998"; + reg = <0x0c996400 0x200>, + <0x0c996600 0x280>, + <0x0c996a00 0x10e>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", + "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + }; + mmss_smmu: iommu@cd00000 { compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; reg = <0x0cd00000 0x40000>; -- cgit v1.2.3-59-g8ed1b From 7868ed0144b33903e16a50485775f669c109e41a Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 3 Aug 2023 15:05:26 +0200 Subject: arm64: dts: qcom: sc8280xp-x13s: Unreserve NC pins Pins 83-86 and 158-160 are NC, so there's no point in keeping them reserved. Take care of that. Fixes: 32c231385ed4 ("arm64: dts: qcom: sc8280xp: add Lenovo Thinkpad X13s devicetree") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230803-topic-x13s_pin-v1-1-fae792274e89@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index ffcca4f028e7..16e784acc7b3 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -1244,7 +1244,7 @@ }; &tlmm { - gpio-reserved-ranges = <70 2>, <74 6>, <83 4>, <125 2>, <128 2>, <154 7>; + gpio-reserved-ranges = <70 2>, <74 6>, <125 2>, <128 2>, <154 4>; bt_default: bt-default-state { hstp-bt-en-pins { -- cgit v1.2.3-59-g8ed1b From 1c63dd1c5fdafa8854526d7d60d2b741c813678d Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 5 Aug 2023 11:01:33 +0200 Subject: arm64: dts: qcom: sc8280xp-x13s: Add camera activity LED Disappointigly, the camera activity LED is implemented in software. Hook it up as a gpio-led and (until we have camera *and* a "camera on" LED trigger) configure it as a panic indicator. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230805-topic-x13s_cam_led-v1-1-443d752158c4@linaro.org Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 16e784acc7b3..38edaf51aa34 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -12,6 +12,7 @@ #include #include #include +#include #include #include "sc8280xp.dtsi" @@ -78,6 +79,21 @@ }; }; + leds { + compatible = "gpio-leds"; + + led-camera-indicator { + label = "white:camera-indicator"; + function = LED_FUNCTION_INDICATOR; + color = ; + gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + /* Reuse as a panic indicator until we get a "camera on" trigger */ + panic-indicator; + }; + }; + pmic-glink { compatible = "qcom,sc8280xp-pmic-glink", "qcom,pmic-glink"; -- cgit v1.2.3-59-g8ed1b From 4fb40b22e97ecea2d18a0c450c24388909e5b44c Mon Sep 17 00:00:00 2001 From: Nikita Travkin Date: Tue, 8 Aug 2023 15:10:13 +0500 Subject: arm64: dts: qcom: sc7180: Split up TF-A related PSCI configuration When initially submitted, the sc7180 support only targeted CROS devices that make use of alternative TF-A firmware and not the official Qualcomm firmware. The PSCI implementations in those firmwares differ however so devices that use qcom firmware, like WoA laptops such as aspire1 need different setup. This commit adjusts the SoC dtsi to the OSI mode PSCI setup, common to the Qualcomm firmware and introduces new sc7180-firmware-tfa.dtsi that overrides the PSCI setup for the PC mode and uses TF-A specific psci-suspend-param. This dtsi is added to all boards that appear to use TF-A. Signed-off-by: Nikita Travkin Link: https://lore.kernel.org/r/20230808-sc7180-tfa-fw-v1-1-666d5d8467e5@trvn.ru Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc7180-firmware-tfa.dtsi | 107 ++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7180-idp.dts | 1 + arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 1 + arch/arm64/boot/dts/qcom/sc7180.dtsi | 127 +++++++++++++++++----- 4 files changed, 206 insertions(+), 30 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-firmware-tfa.dtsi diff --git a/arch/arm64/boot/dts/qcom/sc7180-firmware-tfa.dtsi b/arch/arm64/boot/dts/qcom/sc7180-firmware-tfa.dtsi new file mode 100644 index 000000000000..ee35a454dbf6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-firmware-tfa.dtsi @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Devices that use SC7180 with TrustedFirmware-A + * need PSCI PC mode instead of the OSI mode provided + * by Qualcomm firmware. + */ + +&CPU0 { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; +}; + +&CPU1 { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; +}; + +&CPU2 { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; +}; + +&CPU3 { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; +}; + +&CPU4 { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; +}; + +&CPU5 { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; +}; + +&CPU6 { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + + cpu-idle-states = <&BIG_CPU_SLEEP_0 + &BIG_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; +}; + +&CPU7 { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + + cpu-idle-states = <&BIG_CPU_SLEEP_0 + &BIG_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; +}; + +/delete-node/ &domain_idle_states; + +&idle_states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + idle-state-name = "cluster-power-down"; + arm,psci-suspend-param = <0x40003444>; + entry-latency-us = <3263>; + exit-latency-us = <6562>; + min-residency-us = <9926>; + local-timer-stop; + }; +}; + +/delete-node/ &CPU_PD0; +/delete-node/ &CPU_PD1; +/delete-node/ &CPU_PD2; +/delete-node/ &CPU_PD3; +/delete-node/ &CPU_PD4; +/delete-node/ &CPU_PD5; +/delete-node/ &CPU_PD6; +/delete-node/ &CPU_PD7; +/delete-node/ &CLUSTER_PD; + +&apps_rsc { + /delete-property/ power-domains; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts index a1c50be4ad95..0146fb0036d4 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts @@ -11,6 +11,7 @@ #include #include #include "sc7180.dtsi" +#include "sc7180-firmware-tfa.dtsi" #include "pm6150.dtsi" #include "pm6150l.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index af16e36bcb40..5a33e16a8b67 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -13,6 +13,7 @@ #include #include "sc7180.dtsi" +#include "sc7180-firmware-tfa.dtsi" /* PMICs depend on spmi_bus label and so must come after sc7180.dtsi */ #include "pm6150.dtsi" #include "pm6150l.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 9af94e267f84..a79c0f2e1879 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -79,9 +79,8 @@ reg = <0x0 0x0>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; capacity-dmips-mhz = <415>; dynamic-power-coefficient = <137>; operating-points-v2 = <&cpu0_opp_table>; @@ -109,9 +108,8 @@ reg = <0x0 0x100>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; capacity-dmips-mhz = <415>; dynamic-power-coefficient = <137>; next-level-cache = <&L2_100>; @@ -134,9 +132,8 @@ reg = <0x0 0x200>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; capacity-dmips-mhz = <415>; dynamic-power-coefficient = <137>; next-level-cache = <&L2_200>; @@ -159,9 +156,8 @@ reg = <0x0 0x300>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; capacity-dmips-mhz = <415>; dynamic-power-coefficient = <137>; next-level-cache = <&L2_300>; @@ -184,9 +180,8 @@ reg = <0x0 0x400>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; capacity-dmips-mhz = <415>; dynamic-power-coefficient = <137>; next-level-cache = <&L2_400>; @@ -209,9 +204,8 @@ reg = <0x0 0x500>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; capacity-dmips-mhz = <415>; dynamic-power-coefficient = <137>; next-level-cache = <&L2_500>; @@ -234,9 +228,8 @@ reg = <0x0 0x600>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; - cpu-idle-states = <&BIG_CPU_SLEEP_0 - &BIG_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <480>; next-level-cache = <&L2_600>; @@ -259,9 +252,8 @@ reg = <0x0 0x700>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; - cpu-idle-states = <&BIG_CPU_SLEEP_0 - &BIG_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <480>; next-level-cache = <&L2_700>; @@ -314,7 +306,7 @@ }; }; - idle-states { + idle_states: idle-states { entry-method = "psci"; LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { @@ -356,15 +348,34 @@ min-residency-us = <5555>; local-timer-stop; }; + }; - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "arm,idle-state"; + domain_idle_states: domain-idle-states { + CLUSTER_SLEEP_PC: cluster-sleep-0 { + compatible = "domain-idle-state"; + idle-state-name = "cluster-l3-power-collapse"; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <2752>; + exit-latency-us = <3048>; + min-residency-us = <6118>; + }; + + CLUSTER_SLEEP_CX_RET: cluster-sleep-1 { + compatible = "domain-idle-state"; + idle-state-name = "cluster-cx-retention"; + arm,psci-suspend-param = <0x41001244>; + entry-latency-us = <3638>; + exit-latency-us = <4562>; + min-residency-us = <8467>; + }; + + CLUSTER_AOSS_SLEEP: cluster-sleep-2 { + compatible = "domain-idle-state"; idle-state-name = "cluster-power-down"; - arm,psci-suspend-param = <0x40003444>; + arm,psci-suspend-param = <0x4100b244>; entry-latency-us = <3263>; exit-latency-us = <6562>; - min-residency-us = <9926>; - local-timer-stop; + min-residency-us = <9826>; }; }; }; @@ -567,6 +578,61 @@ psci { compatible = "arm,psci-1.0"; method = "smc"; + + CPU_PD0: cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + }; + + CPU_PD1: cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + }; + + CPU_PD2: cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + }; + + CPU_PD3: cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + }; + + CPU_PD4: cpu4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + }; + + CPU_PD5: cpu5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + }; + + CPU_PD6: cpu6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; + }; + + CPU_PD7: cpu7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; + }; + + CLUSTER_PD: cpu-cluster0 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_PC + &CLUSTER_SLEEP_CX_RET + &CLUSTER_AOSS_SLEEP>; + }; }; reserved_memory: reserved-memory { @@ -3597,6 +3663,7 @@ , , ; + power-domains = <&CLUSTER_PD>; rpmhcc: clock-controller { compatible = "qcom,sc7180-rpmh-clk"; -- cgit v1.2.3-59-g8ed1b From befa79798a614215521811e84e3b783a2a685595 Mon Sep 17 00:00:00 2001 From: "Lin, Meng-Bo" Date: Sat, 12 Aug 2023 07:16:56 +0000 Subject: arm64: dts: qcom: msm8916-samsung-e5: Add touchscreen Similar to A5, E5 uses a Melfas MMS345L touchscreen that is connected to blsp_i2c5. Add it to the device tree. Signed-off-by: Lin, Meng-Bo Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230812071448.4710-1-linmengbo0689@protonmail.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/msm8916-samsung-e5.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-e5.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-e5.dts index 777eb934eb4b..fad2535255f7 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-e5.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-e5.dts @@ -22,3 +22,23 @@ compatible = "samsung,e5", "qcom,msm8916"; chassis-type = "handset"; }; + +&blsp_i2c5 { + status = "okay"; + + touchscreen@48 { + compatible = "melfas,mms345l"; + reg = <0x48>; + + interrupts-extended = <&tlmm 13 IRQ_TYPE_EDGE_FALLING>; + + touchscreen-size-x = <720>; + touchscreen-size-y = <1280>; + + avdd-supply = <®_vdd_tsp_a>; + vdd-supply = <&pm8916_l6>; + + pinctrl-0 = <&ts_int_default>; + pinctrl-names = "default"; + }; +}; -- cgit v1.2.3-59-g8ed1b From b51ee205dc4f21ca26dd8ca6e17a1580e14f57c5 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 11 Aug 2023 22:48:35 +0200 Subject: arm64: dts: qcom: sdm670: Add PDC Add support for the PDC to enable deep sleep wakeup from external sources. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230811-topic-tlmm_wakeup-v1-2-5616a7da1fff@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index 0ac39d3d68ca..a6b260e661ac 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -1323,6 +1323,16 @@ }; }; + pdc: interrupt-controller@b220000 { + compatible = "qcom,sdm670-pdc", "qcom,pdc"; + reg = <0 0x0b220000 0 0x30000>; + qcom,pdc-ranges = <0 480 40>, <41 521 7>, <49 529 4>, + <54 534 24>, <79 559 30>, <115 630 7>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0 0x0c440000 0 0x1100>, -- cgit v1.2.3-59-g8ed1b From 57ff519a644cb5be33b28b7848ddde648a60d262 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 11 Aug 2023 22:48:36 +0200 Subject: arm64: dts: qcom: sc8280xp: Hook up PDC as wakeup-parent of TLMM Some TLMM pins are wakeup-capable. Describe the relationship between these two peripherals to enable this functionality. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230811-topic-tlmm_wakeup-v1-3-5616a7da1fff@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 0756b7c141ff..cad59af7ccef 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -4059,6 +4059,7 @@ interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 230>; + wakeup-parent = <&pdc>; }; apps_smmu: iommu@15000000 { -- cgit v1.2.3-59-g8ed1b From a74883a0de4ecee0c5a07ec732dd75acedb57723 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 11 Aug 2023 22:48:37 +0200 Subject: arm64: dts: qcom: sa8775p: Hook up PDC as wakeup-parent of TLMM Some TLMM pins are wakeup-capable. Describe the relationship between these two peripherals to enable this functionality. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230811-topic-tlmm_wakeup-v1-4-5616a7da1fff@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 73fd8a0c0320..9f4f58e831a4 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -1943,6 +1943,7 @@ interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 149>; + wakeup-parent = <&pdc>; }; apps_smmu: iommu@15000000 { -- cgit v1.2.3-59-g8ed1b From 71f080633d1ee1233759484d790e86847d2434a5 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 11 Aug 2023 22:48:38 +0200 Subject: arm64: dts: qcom: sdm670: Hook up PDC as wakeup-parent of TLMM Some TLMM pins are wakeup-capable. Describe the relationship between these two peripherals to enable this functionality. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230811-topic-tlmm_wakeup-v1-5-5616a7da1fff@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index a6b260e661ac..84cd2e39266f 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -1123,6 +1123,7 @@ interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 151>; + wakeup-parent = <&pdc>; qup_i2c0_default: qup-i2c0-default-state { pins = "gpio0", "gpio1"; -- cgit v1.2.3-59-g8ed1b From 902824035fa5f2d2e9d20937cec331cbe52a1ab4 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 11 Aug 2023 22:48:39 +0200 Subject: arm64: dts: qcom: sm6350: Hook up PDC as wakeup-parent of TLMM Some TLMM pins are wakeup-capable. Describe the relationship between these two peripherals to enable this functionality. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230811-topic-tlmm_wakeup-v1-6-5616a7da1fff@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 8f66306d1de3..8fd6f4d03490 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -2261,6 +2261,7 @@ interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 157>; + wakeup-parent = <&pdc>; cci0_default: cci0-default-state { pins = "gpio39", "gpio40"; -- cgit v1.2.3-59-g8ed1b From 110e70fccce4f22b53986ae797d665ffb1950aa6 Mon Sep 17 00:00:00 2001 From: Amit Pundir Date: Wed, 26 Jul 2023 18:57:19 +0530 Subject: arm64: dts: qcom: sdm845-db845c: Mark cont splash memory region as reserved Adding a reserved memory region for the framebuffer memory (the splash memory region set up by the bootloader). It fixes a kernel panic (arm-smmu: Unhandled context fault at this particular memory region) reported on DB845c running v5.10.y. Cc: stable@vger.kernel.org # v5.10+ Reviewed-by: Caleb Connolly Signed-off-by: Amit Pundir Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230726132719.2117369-2-amit.pundir@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 14f9afbd75e5..c7eba6c491be 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -101,6 +101,14 @@ }; }; + reserved-memory { + /* Cont splash region set up by the bootloader */ + cont_splash_mem: framebuffer@9d400000 { + reg = <0x0 0x9d400000 0x0 0x2400000>; + no-map; + }; + }; + lt9611_1v8: lt9611-vdd18-regulator { compatible = "regulator-fixed"; regulator-name = "LT9611_1V8"; @@ -513,6 +521,7 @@ }; &mdss { + memory-region = <&cont_splash_mem>; status = "okay"; }; -- cgit v1.2.3-59-g8ed1b