From 7101ab97e3b00ec1c68d09826bb0521d17783673 Mon Sep 17 00:00:00 2001 From: Huang Rui Date: Wed, 18 May 2022 21:19:32 +0800 Subject: drm/amdgpu/pm: implement the SMU_MSG_EnableGfxImu function GC v11_0_1 asic needs to issue the EnableGfxImu message after start IMU. Signed-off-by: Huang Rui Reviewed-by: Tim Huang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 14 ++++++++++++++ drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 2 ++ drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 9 ++++++++- drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 7 +++++++ drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 2 ++ drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 10 ++++++++++ drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c | 1 + 7 files changed, 44 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c index d1bf073adf54..956b6ce81c84 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c @@ -107,6 +107,20 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block return ret; } +int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev) +{ + struct smu_context *smu = adev->powerplay.pp_handle; + int ret = -EOPNOTSUPP; + + mutex_lock(&adev->pm.mutex); + ret = smu_set_gfx_power_up_by_imu(smu); + mutex_unlock(&adev->pm.mutex); + + msleep(10); + + return ret; +} + int amdgpu_dpm_baco_enter(struct amdgpu_device *adev) { const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h index 3e78b3057277..524fb09437e5 100644 --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h @@ -386,6 +386,8 @@ int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev); int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, enum pp_mp1_state mp1_state); +int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev); + int amdgpu_dpm_baco_exit(struct amdgpu_device *adev); int amdgpu_dpm_baco_enter(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index a601024ba4de..ae595ee544dc 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -134,6 +134,14 @@ int smu_get_dpm_freq_range(struct smu_context *smu, return ret; } +int smu_set_gfx_power_up_by_imu(struct smu_context *smu) +{ + if (!smu->ppt_funcs && !smu->ppt_funcs->set_gfx_power_up_by_imu) + return -EOPNOTSUPP; + + return smu->ppt_funcs->set_gfx_power_up_by_imu(smu); +} + static u32 smu_get_mclk(void *handle, bool low) { struct smu_context *smu = handle; @@ -2467,7 +2475,6 @@ static int smu_set_power_profile_mode(void *handle, return smu_bump_power_profile_mode(smu, param, param_size); } - static int smu_get_fan_control_mode(void *handle, u32 *fan_mode) { struct smu_context *smu = handle; diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index a6a7b6c33683..c3d5a616e572 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -697,6 +697,11 @@ struct pptable_funcs { */ int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable); + /** + * @set_gfx_power_up_by_imu: Enable GFX engine with IMU + */ + int (*set_gfx_power_up_by_imu)(struct smu_context *smu); + /** * @read_sensor: Read data from a sensor. * &sensor: Sensor to read data from. @@ -1438,6 +1443,8 @@ int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max); +int smu_set_gfx_power_up_by_imu(struct smu_context *smu); + int smu_set_ac_dc(struct smu_context *smu); int smu_allow_xgmi_power_down(struct smu_context *smu, bool en); diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h index 036fd2810ecc..08270d8528d9 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h @@ -292,6 +292,8 @@ int smu_v13_0_baco_enter(struct smu_context *smu); int smu_v13_0_baco_exit(struct smu_context *smu); +int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu); + int smu_v13_0_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c index 7be4f6875a7b..a56dddc9fb88 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c @@ -2297,6 +2297,16 @@ int smu_v13_0_baco_exit(struct smu_context *smu) SMU_BACO_STATE_EXIT); } +int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu) +{ + uint16_t index; + + index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, + SMU_MSG_EnableGfxImu); + + return smu_cmn_send_msg_without_waiting(smu, index, 0); +} + int smu_v13_0_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], uint32_t size) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c index 5a17b51aa0f9..29fcce04a91a 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_4_ppt.c @@ -1030,6 +1030,7 @@ static const struct pptable_funcs smu_v13_0_4_ppt_funcs = { .force_clk_levels = smu_v13_0_4_force_clk_levels, .set_performance_level = smu_v13_0_4_set_performance_level, .set_fine_grain_gfx_freq_parameters = smu_v13_0_4_set_fine_grain_gfx_freq_parameters, + .set_gfx_power_up_by_imu = smu_v13_0_set_gfx_power_up_by_imu, }; void smu_v13_0_4_set_ppt_funcs(struct smu_context *smu) -- cgit v1.2.3-59-g8ed1b