From f92013259d32c903d360039ff26a659f8f1552f5 Mon Sep 17 00:00:00 2001 From: Jitao Shi Date: Wed, 7 Aug 2019 16:46:43 +0800 Subject: dt-bindings: display: mediatek: update dsi supported chips Update device tree binding documentation for the dsi for Mediatek MT8183 SoCs. Signed-off-by: Jitao Shi Acked-by: Rob Herring Signed-off-by: CK Hu --- Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree/bindings/display/mediatek') diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt index fadf327c7cdf..a19a6cc375ed 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt @@ -7,7 +7,7 @@ channel output. Required properties: - compatible: "mediatek,-dsi" - the supported chips are mt2701 and mt8173. + the supported chips are mt2701, mt8173 and mt8183. - reg: Physical base address and length of the controller's registers - interrupts: The interrupt signal from the function block. - clocks: device clocks @@ -26,7 +26,7 @@ The MIPI TX configuration module controls the MIPI D-PHY. Required properties: - compatible: "mediatek,-mipi-tx" - the supported chips are mt2701 and mt8173. + the supported chips are mt2701, mt8173 and mt8183. - reg: Physical base address and length of the controller's registers - clocks: PLL reference clock - clock-output-names: name of the output clock line to the DSI encoder -- cgit v1.2.3-59-g8ed1b